W79E4051AKG_技术文档

Preliminary W79E4051/W79E2051 Data Sheet

8-BIT MICROCONTROLLER

Table of Contents-

1

2

3

GENERAL DESCRIPTION ......................................................................................................... 4

FEATURES ................................................................................................................................. 5

PARTS INFORMATION LIST ..................................................................................................... 7

3.1

Lead Free (RoHS) Parts information list......................................................................... 7

4

5

6

PIN CONFIGURATION............................................................................................................... 8

PIN DESCRIPTION..................................................................................................................... 9

FUNCTIONAL DESCRIPTION.................................................................................................. 10

6.1

6.2

6.3

6.4

6.5

6.6

6.7

On-Chip Flash EPROM ................................................................................................ 10

I/O Ports........................................................................................................................ 10

Serial I/O....................................................................................................................... 10

Timers........................................................................................................................... 10

Interrupts....................................................................................................................... 10

Data Pointers ................................................................................................................ 10

Architecture................................................................................................................... 11

6.7.1 ALU ................................................................................................................................11

6.7.2 Accumulator ...................................................................................................................11

6.7.3 B Register.......................................................................................................................11

6.7.4 Program Status Word:....................................................................................................11

6.7.5 Scratch-pad RAM...........................................................................................................11

6.7.6 Stack Pointer..................................................................................................................11

7

MEMORY ORGANIZATION...................................................................................................... 12

7.1

7.2

7.3

7.4

7.5

7.6

Program Memory (on-chip Flash)................................................................................. 12

Data Flash Memory ...................................................................................................... 12

Scratch-pad RAM and Register Map............................................................................ 13

Working Registers ........................................................................................................ 14

Bit addressable Locations............................................................................................. 15

Stack............................................................................................................................. 15

8

9

SPECIAL FUNCTION REGISTERS ......................................................................................... 16

INSTRUCTION.......................................................................................................................... 37

9.1

Instruction Timing ......................................................................................................... 45

10

11

POWER MANAGEMENT.......................................................................................................... 46

10.1 Idle Mode ...................................................................................................................... 46

10.2 Power Down Mode ....................................................................................................... 46

RESET CONDITIONS............................................................................................................... 48

11.1 Sources of reset............................................................................................................ 48

11.1.1 External Reset..............................................................................................................48

11.1.2 Power-On Reset (POR)................................................................................................48

11.1.3 Brown-Out Reset (BOR)...............................................................................................48

11.1.4 Watchdog Timer Reset.................................................................................................48

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Preliminary W79E4051/W79E2051 Data Sheet

11.2 Reset State ................................................................................................................... 48

INTERRUPTS ........................................................................................................................... 51

12.1 Interrupt Sources .......................................................................................................... 51

12.2 Priority Level Structure ................................................................................................. 52

12.3 Response Time............................................................................................................. 54

PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 55

12

13

13.1 Timer/Counters 0 & 1.................................................................................................... 55

13.2 Time-Base Selection..................................................................................................... 55

13.2.1 Mode 0 .........................................................................................................................55

13.2.2 Mode 1 .........................................................................................................................56

13.2.3 Mode 2 .........................................................................................................................56

13.2.4 Mode 3 .........................................................................................................................57

NVM MEMORY......................................................................................................................... 58

14

15

WATCHDOG TIMER................................................................................................................. 59

15.1 WATCHDOG CONTROL.............................................................................................. 60

15.2 CLOCK CONTROL of Watchdog.................................................................................. 60

SERIAL PORT (UART) ............................................................................................................. 62

16.1 MODE 0 ........................................................................................................................ 62

16.2 MODE 1 ........................................................................................................................ 63

16.3 MODE 2 ........................................................................................................................ 65

16.4 MODE 3 ........................................................................................................................ 66

16.5 Framing Error Detection ............................................................................................... 67

16.6 Multiprocessor Communications................................................................................... 67

PULSE WIDTH MODULATED OUTPUTS (PWM) ................................................................... 69

ANALOG COMPARATORS...................................................................................................... 71

18.1 Comparator Interrupt with Debouncing......................................................................... 72

18.2 Application circuit.......................................................................................................... 73

TIME ACCESS PROCTECTION .............................................................................................. 74

I/O PORT MODE SETTING...................................................................................................... 76

20.1 Quasi-Bidirectional Output Configuration ..................................................................... 76

20.2 Open Drain Output Configuration ................................................................................. 77

OSCILLATOR ........................................................................................................................... 78

21.1 On-Chip RC Oscillator Option....................................................................................... 78

21.2 External Clock Input Option.......................................................................................... 78

POWER MONITORING FUNCTION ........................................................................................ 79

22.1 Brownout Detect and Reset.......................................................................................... 79

ICP (IN-CIRCUIT PROGRAM) FLASH MODE ......................................................................... 81

CONFIG BITS ........................................................................................................................... 82

24.1 CONFIG0...................................................................................................................... 82

24.2 CONFIG1...................................................................................................................... 83

ELECTRICAL CHARACTERISTICS......................................................................................... 84

25.1 Absolute Maximum Ratings.......................................................................................... 84

16

17

18

19

20

21

22

23

24

25

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Preliminary W79E4051/W79E2051 Data Sheet

25.2 DC ELECTRICAL CHARACTERISTICS ...................................................................... 85

25.3 The COMPARATOR ELECTRICAL CHARACTERISTICS .......................................... 87

25.4 AC ELECTRICAL CHARACTERISTICS ...................................................................... 88

25.5 EXTERNAL CLOCK CHARACTERISTICS .................................................................. 88

25.6 RC OSC AND AC CHARACTERISTICS...................................................................... 89

TYPICAL APPLICATION CIRCUITS ........................................................................................ 90

PACKAGE DIMENSIONS......................................................................................................... 91

27.1 20-pin SOP ................................................................................................................... 91

27.2 20-pin DIP..................................................................................................................... 92

27.3 20-pin SSOP................................................................................................................. 93

REVISION HISTORY................................................................................................................ 94

26

27

28

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Preliminary W79E4051/W79E2051 Data Sheet

1

GENERAL DESCRIPTION

The W79E4051/2051 series are an 8-bit Turbo 51 microcontroller which has an in-system

programmable Flash EPROM which Flash EPROM can program by ICP (In Circuit Program) Writer.

The instruction set of the W79E4051/2051 series are fully compatible with the standard 8052. The

W79E4051/2051 series contain a 4K/2K bytes of program Flash EPROM; a 256 bytes of RAM; 128

bytes data Flash EPROM for customer data storage; two 8-bit bi-directional and bit-addressable I/O

ports; two 16-bit timer/counters; an enhanced full duplex serial port; 1 channel PWM by 10-bit counter,

Brownout voltage detection/reset, Power on reset detection and one analog comparator. These

peripherals are supported by 9 sources of four-level interrupt capability. To facilitate programming and

verification, the Flash EPROM inside the W79E4051/2051 series allow the program memory to be

programmed and read electronically. Once the code is confirmed, the user can protect the code for

security.

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Preliminary W79E4051/W79E2051 Data Sheet

2

•

FEATURES

Fully static design 8-bit Turbo 51 CMOS microcontroller up to 24MHz

Single power: 2.4~5.5V Up to 12MHz, 4.5~5.5V up to 24MHz

Flexible CPU clock source configurable by config bit and software:

•

- High speed external oscillator: upto 24MHz Crystal and resonator (enabled by config bit).

- Internal RC oscillator: 22.1184/11.0592MHz with ±2% accuracy (selectable by config bit), at

5.0 voltage and 25℃condition, for W79E2051R and W79E4051R

•

Instruction-set compatible with MCS-51

4K/2K bytes of Program Flash EPROM, with ICP and external writer programmable mode.

256 bytes of on-chip RAM

W79E4051/2051 supports 128 bytes Data Flash EPROM for customer data storage used and 10K

writer cycles.

- 8 pages. Page size is 16 bytes.

- Data Flash program/erase V_DD=3.0V to 5.5V

•

One 8-bit bi-directional port(Port1), one 7-bit bi-directional port(Port3) and one 2-bit bi-

directional port(P2.0 and P2.1 shared with XT1 and XT2 pins)

•

I/O capable of driving LED max. 20mA per pin, max to 80mA for total pins.

Two 16-bit timer/counters

9 Interrupt source with four levels of priority

One enhanced full duplex serial port with framing error detection and automatic address

recognition

•

One channel 10-bit PWM output

One analog Comparator

Built-in Power Management

- Power on reset flag

- Brownout voltage detect/reset

Operating Temperature: -40~85℃

Packages:

•

- Lead Free (RoHS) PDIP 20:

- Lead Free (RoHS) SOP 20:

- Lead Free (RoHS) SSOP 20:

- Lead Free (RoHS) PDIP 20:

- Lead Free (RoHS) SOP 20:

- Lead Free (RoHS) SSOP 20:

- Lead Free (RoHS) PDIP 20:

- Lead Free (RoHS) SOP 20:

- Lead Free (RoHS) SSOP 20:

W79E4051AKG

W79E4051ASG

W79E4051ARG

W79E2051AKG

W79E2051ASG

W79E2051ARG

W79E4051RAKG

W79E4051RASG

W79E4051RARG

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Preliminary W79E4051/W79E2051 Data Sheet

- Lead Free (RoHS) PDIP 20:

W79E2051RAKG

W79E2051RASG

W79E2051RARG

- Lead Free (RoHS) SOP 20:

- Lead Free (RoHS) SSOP 20:

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Preliminary W79E4051/W79E2051 Data Sheet

3

PARTS INFORMATION LIST

3.1 Lead Free (RoHS) Parts information list

Table 3-1: Lead Free (RoHS) Parts information list

PROGRAM

FLASH

EPROM

DATA

FLASH

EPROM

INTERNAL RC

OSCILLATOR

ACCURACY¹

PART NO.

RAM

PACKAGE

W79E4051AKG

W79E4051ASG

W79E4051ARG

W79E2051AKG

W79E2051ASG

W79E2051ARG

W79E4051RAKG

W79E4051RASG

W79E4051RARG

W79E2051RAKG

W79E2051RASG

W79E2051RARG

4KB

2KB

4KB

2KB

256B

128B

PDIP-20 Pin

SOP-20 Pin

SSOP-20 Pin

PDIP-20 Pin

SOP-20 Pin

SSOP-20 Pin

PDIP-20 Pin

SOP-20 Pin

SSOP-20 Pin

PDIP-20 Pin

SOP-20 Pin

SSOP-20 Pin

22MHz ± 25%

22.1184MHz ± 2%

Note:

1. Factory calibration condition: V_DD=5.0V, TA = 25°C

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Preliminary W79E4051/W79E2051 Data Sheet

4

PIN CONFIGURATION

20 PIN

DIP/SOP

1

2

20

19

18

17

16

15

14

13

10

11

MODE/RST

RXD/P3.0

TXD/P3.1

VCC

P1.7

3

P1.6

4

XTAL2/P2.0

XTAL1/P2.1

INT0/P3.2

INT1/P3.3

T0/P3.4

P1.5

5

P1.4

6

P1.3

7

P1.2

8

P1.1/AN1-

P1.0/AN0+

P3.7

9

PWM0/T1/P3.5

GND

10

Table 4-1: Pin Configuration

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Preliminary W79E4051/W79E2051 Data Sheet

5

PIN DESCRIPTION

SYMBOL Alternate Alternate Alternate

Type DESCRIPTIONS

function 2 function 3

(ICP mode)

Function 1

P2.1

X1

I/O

I

CRYSTAL1: This is the crystal

oscillator input. This pin may be

driven by an external clock or

configurable i/o pin.

P2.0

VDD

X2/CLKOUT

I/O O CRYSTAL2: This is the crystal

oscillator output. It is the inversion of

XTAL1. Also a configurable i/o pin.

-

P

POWER SUPPLY: Supply voltage for

operation.

VSS

RST

P

I

GROUND: Ground potential.

MODE

RESET: A high on this pin for two

machine cycles while the oscillator is

running resets the

device.

MODE: used in ICP mode.

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

AN0+

AN1-

I/O, D Port1:

8-bit bi-directional I/O port with

I/O, D

I/O

S

internal weakly pull-ups. P1.0~P1.1

are open-drain mode after reset.

Multifunction pins:

AN0+ and AN1- are analog

comparator inputs.

Data and SCK are used in ICP mode.

Data

SCK

RXD

TXD

/INT0

/INT1

T0

Port3:

7-bit bi-directional I/O port, P3.0~P3.7

except P3.6, with internal weakly pull-

ups. P3.6 is internal wired to analog

comparator output.

Multifunction pins for TXD & RXD

(UART),/INT0-1, T0, T1/PWM0.

T1

PWM0

I/O

* Note : TYPE P: Power, I: input, O: output, I/O: bi-directional, S: internal Signal.

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Preliminary W79E4051/W79E2051 Data Sheet

6

FUNCTIONAL DESCRIPTION

The W79E4051/2051 architecture consist of a 4T 8051 core controller surrounded by various

registers, 4K/2K bytes AP Flash EPROM, 256 bytes of RAM, 128 bytes Data Flash EPROM, three

general purpose I/O ports, two timer/counters, one serial port, Flash EPROM program by Writer and

ICP.

6.1 On-Chip Flash EPROM

The W79E4051/2051 includes one 4K/2K bytes of main Flash EPROM for application program. A

Writer or ICP programming board is required to program the AP Flash EPROM and Data Flash

EPROM.

This ICP (In-Circuit Programming) feature makes the job easy and efficient when the application’s

firmware needs to be updated frequently. In some applications, the in-circuit programming feature

makes it possible for the end-user to easily update the system firmware without opening the chassis.

6.2 I/O Ports

W79E4051/2051 has one 8-bit, one 7-bit and one 2-bit ports using on-chip oscillator by reset options.

Except P1.0 and P1.1, all ports are in quasi-bidrectional structure that the internal weakly pull-ups are

present as the port registers are set to logic one. P1.0~P1.1, the alternate function are analog

comparator inputs, stays in PMOS-off open-drain mode after CPU reset.

6.3 Serial I/O

The W79E4051/2051 has one serial port that is functionally similar to the serial port of the original

8051 family. However the serial port on the W79E4051/2051 can operate in different modes in order to

obtain timing similarity as well. The Serial port has the enhanced features of Automatic Address

recognition and Frame Error detection.

6.4 Timers

The W79E4051/2051 has two 16-bit timers that are functionally and similar to the timers of the 8051

family. When used as timers, user has a choice to set 12 or 6 clocks per count that emulates the

timing of the original 8051. Each timer’s count value is stored in two SFR locations that can be written

or read by software. There are also some other SFRs associated with the timers that control their

mode and operation.

6.5 Interrupts

The Interrupt structure in the W79E4051/2051 is slightly different from that of the standard 8051. Due

to the presence of additional features and peripherals, the number of interrupt sources and vectors

has been increased.

6.6 Data Pointers

The data pointer of W79E4051/2051 is similar to standard 8051 but has dual 16-bit Data Pointers

(DPTR) by setting DPS of AUXR2.0. In addition there is an added instruction, DEC DPTR (op-code

A5H), which helps in improving programming flexibility for the user.

DPS=0

DPTR

AUXR2.0

DPS

DPS=1

DPTR

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Preliminary W79E4051/W79E2051 Data Sheet

Table 6-1: Data Pointer

6.7 Architecture

The W79E4051/2051 is based on the standard MCS-51 device. It is built around an 8-bit ALU that

uses internal registers for temporary storage and control of the peripheral devices. It can execute the

standard MCS-51 instruction set.

6.7.1 ALU

The ALU is the heart of the W79E4051/2051. It is responsible for the arithmetic and logical functions.

It is also used in decision making, in case of jump instructions, and is also used in calculating jump

address. The user cannot directly use the ALU, but the Instruction Decoder reads the op-code,

decodes it, and sequences the data through the ALU and its associated registers to generate the

required result. The ALU mainly uses the ACC which is a special function register (SFR) on the chip.

Another SFR, namely B register is also used in Multiply and Divide instructions. The ALU generates

several status signals which are stored in the Program Status Word register (PSW).

6.7.2 Accumulator

The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations

in the W79E4051/2051. Since the Accumulator is directly accessible by the CPU, most of the high

speed instructions make use of the ACC as one argument.

6.7.3 B Register

This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all

other instructions it can be used simply as a general purpose register.

6.7.4 Program Status Word:

This is an 8-bit SFR that is used to store the status bits of the ALU. It holds the Carry flag, the Auxiliary

Carry flag, General purpose flags, the Register Bank Select, the Overflow flag, and the Parity flag.

6.7.5 Scratch-pad RAM

The W79E4051/2051 has a 256 byte on-chip scratch-pad RAM. This can be used by the user for

temporary storage during program execution. A certain section of this RAM is bit addressable, and can

be directly addressed for this purpose.

6.7.6 Stack Pointer

The W79E4051/2051 has an 8-bit Stack Pointer which points to the top of the Stack. This stack

resides in the Scratch Pad RAM in the W79E4051/2051. Hence the size of the stack is limited by the

size of this RAM.

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Preliminary W79E4051/W79E2051 Data Sheet

7

MEMORY ORGANIZATION

The W79E4051/2051 series separate the memory into two separate sections, the Program Memory

and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data

Memory is used to store data or for memory mapped devices.

7.1 Program Memory (on-chip Flash)

The Program Memory on the W79E4051/2051 series can be up to 4K/2K bytes long. All instructions

are fetched for execution from this memory area. The MOVC instruction can also access this memory

region.

7.2 Data Flash Memory

The Data Flash EPROM on the W79E4051/2051 series is 128 bytes long with page size of 16 bytes.

The W79E4051/2051 series read the content of data memory by using “MOVC A, @A+DPTR”. To

write data is by NVMADDRL, NVMDATA and NVMCON SFR’s registers.

128 bytes NVM

16 bytes/page

FFFFh

FC7Fh

Page 7

Unused

FC70h

FC6Fh

Code Memory

Page 6

FC60h

FC5Fh

Page 5

FC50h

FC4Fh

FC7Fh

128 Bytes

NVM

Page 4

Page 3

Page 2

Page 1

Page 0

FC40h

FC3Fh

Data Memory

FC00h

FC30h

FC2Fh

FC20h

FC1Fh

Unused

Code Memory

FC10h

FC0Fh

FC00h

NVM Data Memory Area

0FFFh/07FFh

0000h

4K/2K Bytes

On-Chip

Code Memory

CONFIG1

CONFIG0

W79E4051/2051 On-chip Flash Memory Space

Table 7-1 W79E4051/2051 On-chip Flash Memory Map

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Preliminary W79E4051/W79E2051 Data Sheet

7.3 Scratch-pad RAM and Register Map

As mentioned before the W79E4051/2051 series have separate Program and Data Memory areas.

The on-chip 256 bytes scratch pad RAM is built in W79E4051/2051. There are also several Special

Function Registers (SFRs) which can be accessed by software. The SFRs can be accessed only by

direct addressing, while the on-chip RAM can be accessed by either direct or indirect addressing.

FFH

SFR

Indirect

Direct

RAM

Addressing

Only

80H

7FH

Direct

&

Indirect

RAM

Addressing

00H

256 bytes RAM and SFR Data Memory Space

Table 7-2 W79E4051/2051 256 bytes RAM and SFR memory map

Since the scratch-pad RAM is 256 bytes it can be used only when data contents are small. There are

several other special purpose areas within the scratch-pad RAM. These are illustrated in next figure.

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Preliminary W79E4051/W79E2051 Data Sheet

FFH

Indirect RAM

80H

7FH

Direct RAM

30H

2FH 7F 7E 7D 7C 7B 7A 79

2EH 77 76 75 74 73 72 71

2DH 6F 6E 6D 6C 6B 6A 69

2CH 67 66 65 64 63 62 61

2BH 5F 5E 5D 5C 5B 5A 59

2AH 57 56 55 54 53 52 51

29H 4F 4E 4D 4C 4B 4A 49

47 46 45

41

27H 3F 3E 3D 3C 3B 3A 39

26H 34 33

25H 2F 2E 2D 2C 2B 2A 29

24H 27 26 25 24 23 22 21

23H 1F 1E 1D 1C 1B 1A 19

22H 17 16 15 14 13 12 11

21H 0F 0E 0D 0C 0B 0A 09

78

70

68

60

58

50

48

40

38

30

28

20

18

10

08

00

28H

44

43

42

37

36

35

32

31

20H 07

1FH

06

05

04

03

02

01

Bank 3

Bank 2

Bank 1

Bank 0

18H

17H

10H

0FH

08H

07H

00H

Table 7-3 Scratch-pad RAM

7.4

Working Registers

There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as

Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate

instructions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at

one time the W79E4051/2051 series can work with only one particular bank. The bank selection is

done by setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the address for

indirect accessing.

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Preliminary W79E4051/W79E2051 Data Sheet

7.5 Bit addressable Locations

The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means

that a bit in this area can be individually addressed. In addition some of the SFRs are also bit

addressable. The instruction decoder is able to distinguish a bit access from a byte access by the type

of the instruction itself. In the SFR area, any existing SFR whose address ends in a 0 or 8 is bit

addressable.

7.6 Stack

The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP),

which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the

return address is placed on the stack. There is no restriction as to where the stack can begin in the

RAM. By default however, the Stack Pointer contains 07h at reset. The user can then change this to

any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and

then address saved onto the stack. Conversely, while popping from the stack the contents will be read

first, and then the SP is decreased.

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Preliminary W79E4051/W79E2051 Data Sheet

8

SPECIAL FUNCTION REGISTERS

The W79E4051/2051 series uses Special Function Registers (SFRs) to control and monitor

peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by

direct addressing only. Some of the SFRs are bit addressable. This is very useful in cases where

users wish to modify a particular bit without changing the others. The SFRs that are bit addressable

are those whose addresses end in 0 or 8. The W79E4051/2051 series contain all the SFRs present in

the standard 8052. However some additional SFRs are added. In some cases the unused bits in the

original 8052, have been given new functions. The list of the SFRs is as follows.

IP1

F8

F0

E8

E0

D8

D0

B

PCMPIDS

IP1H

EIE

ACC

WDCON

PSW

PWMPL

PWMPH

PWM0L

PWM0H

PWMCON1

PWMCON3

C8

C0

B8

B0

A8

A0

98

90

88

80

NVMCON

NVMDATA

TA

NVMADDRL

IP0

SADEN

SADDR

SBUF

P3

P1M1

IP0H

IE

P2

AUXR1

AUXR2

SCON

P1

ACCK

ACSR

TCON

TMOD

SP

TL0

TL1

TH0

TH1

CKCON

CLKREG

PCON

DPL

DPH

Table 8-1: Special Function Register Location Table

Note:

1. The SFRs in the column with dark borders are bit-addressable

2. The table is condensed with eight locations per row. Empty locations indicate that these are no

registers at these addresses.

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Preliminary W79E4051/W79E2051 Data Sheet

Special Function Registers:

SYMBOL

IP1

DEFINITION

ADDRESS

MSB

(FF)

-

(F7)

(EF)

-

BIT ADDRESS, SYMBOL

LSB

(F8)

-

B0

(F0)

(E8)

-

(E0)

PWM0I

RESET

x000 xxxxB

Interrupt priority 1

F8H

(FE)

(FD)

(FC)

(FB)

(FA)

-

(F2)

(EA)

-

(E2)

-

(F9)

-

B1

(F1)

(E9)

-

(E1)

-

PBOV

PBOVH

-

PPWM

PPWMH

-

PWDI

PWDIH

-

IP1H

PCMPIDS

B

Interrupt high priority 1

F7H

x000 xxxxB

xxxx 0000B

00000000B

xx000 xxxxB

Port Comparator Input Disable F6H

B register

Interrupt enable 1

F0H

E8H

(F6)

(F5)

(F4)

(EC)

EWDI

(F3)

(EB)

-

EIE

(EE)

EBOV

(E6)

(ED)

EPWM

ACC

Accumulator

E0H

(E7)

(E5)

(E4)

CLRPWM

PWM0.4

(E3)

-

00000000B

0000 0000B

PWMCON1

PWM0L

PWMPL

PWM CONTROL REGISTER 1 DCH

PWM 0 LOW BITS REGISTER DAH

PWMRUN load

PWM0.7 PWM0.6

PWMF

PWM0.5

PWM0.3 PWM0.2 PWM0.1 PWM0.0

PWM COUNTER LOW

REGISTER

D9H

PWMP0.7 PWMP0.6 PWMP0.5 PWMP0.4 PWMP0.3 PWMP0.2 PWMP0.1 PWMP0.0 0000 0000B

WDCON

WATCH-DOG CONTROL

D8H

(DF)

WDRUN

-

(DE)

(DD)

WD1

-

(DC)

WD0

PWM0OE

-

(DB)

WDIF

-

(DA)

WTRF

-

(D9)

EWRST WDCLR

FP1 FP0

PWM0.9 PWM0.8

(D8)

0X00 0000B

-

PWMCON3

PWM0H

PWM CONTROL REGISTER 3 D7H

PWM 0 HIGH BITS

REGISTER

PWM COUNTER HIGH

REGISTER

0000 XX00B

XXXX XX00B

D2H

D1H

D0H

PWMPH

PSW

-

PWMP0.9 PWMP0.8 XXXX XX00B

(D7)

CY

(D6)

AC

(D5)

F0

(D4)

RS1

(D3)

RS0

(D2)

OV

(D1)

F1

(D0)

P

00000000B

Program status word

NVMDATA

NVMCON

TA

NVM Data

NVM Control

Timed Access Protection

NVM byte address

CFH

CEH

C7H

C6H

00000000B

00xxxxxxB

11111111B

EER

TA.7

EWR

TA.6

-

TA.5

TA.4

TA.3

TA.2

TA.1

TA.0

NVMADDRL

NVMADDR NVMADDR. NVMADDR NVMADDR NVMADD NVMADD NVMADD NVMADDR 00000000B

.7

6

.5

.4

R.3

R.2

R.1

.0

SADEN

IP0

Slave address mask

Interrupt priority 0

B9H

B8H

00000000B

x0x00000B

(BF)

-

(BE)

PC

PCH

-

(BD)

-

(B5)

T1

(BC)

PS

PSH

-

(B4)

T0

(BB)

PT1

PT1H

-

(B3)

INT1

(BA)

PX1

PX1H

-

(B2)

INT0

(B9)

PT0

PT0H

P1M1.1

(B1)

(B8)

PX0

PX0H

P1M1.0

(B0)

IP0H

P1M1

P3

Interrupt high priority 0

Port1 Mode 1

Port 3

B7H

B3H

B0H

x0x00000B

xxxx xx00B

11111111B

(B7)

(B6)

TXD

RXD

SADDR

IE

Slave address

Interrupt enable

A9H

A8H

00000000B

00x00000B

(AF)

EA

(AE)

EC

(AD)

-

(AC)

ES

(AB)

ET1

(AA)

EX1

(A9)

ET0

(A8)

EX0

AUXR2

AUXR1

P2

AUX function register 2

AUX function register 1

Port 2

A3H

A2H

A0H

DPS

BOS

(A0)

P2.0

xxxx xxx0B

0x00 0xx0B

xxxx xxxxB

BOF

(A7)

-

BOD²

(A6)

-

BOI

(A5)

-

LPBOV

(A4)

-

SRST

(A3)

-

BOV1³

(A2)

-

BOV0³

(A1)

P2.1

XTAL1

XTAL2

CLKOUT

SBUF

SCON

Serial buffer

Serial control

99H

98H

xxxxxxxxB

00000000B

(9F)

SM0/FE

-

(9E)

SM1

-

(9D)

SM2

CIPE

(9C)

REN

CF

(9B)

TB8

CEN

(9A)

RB8

CM2

(99)

TI

CM1

(98)

RI

CM0

ACSR

ACCK

Analog Comparator Control & 97H

Status Register

Analog Comparator Debounce 96H

Clock Control

xx000000B

0000 0000B

ENCLK

-

CPCK2

CPCK1

CPCK0

P1

Port 1

90H

8FH

8EH

8DH

8CH

8BH

8AH

89H

88H

(97)

(96)

(95)

(94)

T1M

(93)

T0M

(92)

(91)

(90)

11111111B

Xxxx x00xB

xxx00xxxB

00000000B

CLKREG

CKCON

TH1

TH0

TL1

TL0

TMOD

TCON

PWDEX1 PWDEX0

-

Clock control

Timer high 1

Timer high 0

Timer low 1

Timer low 0

Timer mode

Timer control

-

GATE

(8F)

TF1

C/T1#

(8E)

TR1

M1

(8D)

TF0

M0

GATE

(8B)

IE1

C/T0#

(8A)

IT1

M1

(89)

IE0

PD

M0

(8C)

TR0

POR

(88)

IT0

IDL

PCON

DPH

DPL

SP

Power control

Data pointer high

Data pointer low

Stack pointer

87H

83H

82H

81H

SMOD

SMOD0

GF1

GF0

00xx0000B

00000000B

00000111B

Table 8-2: Special Function Registers

Publication Release Date: April 16, 2009

Revision A06

- 17 -

Preliminary W79E4051/W79E2051 Data Sheet

Note :

1. In column BIT_ADDRESS, SYMBOL, containing ( ) item means the bit address.

2. BOD is initialized at reset with the inversed value of bit CBOD in config0-bits.

3. (BOV1,BOV0) are initialized at reset with the reversed value of config0-bits (CBOV1,CBOV0)

- 18 -

Preliminary W79E4051/W79E2051 Data Sheet

STACK POINTER

Bit:

7

6

5

4

3

2

1

0

SP.7

SP.6

SP.5

SP.4

SP.3

SP.2

SP.1

SP.0

Mnemonic: SP

Address: 81h

BIT NAME

FUNCTION

7-0 SP.[7:0] The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In

other words it always points to the top of the stack.

DATA POINTER LOW

Bit:

7

6

5

4

3

2

1

0

DPL.7

DPL.6

DPL.5

DPL.4

DPL.3

DPL.2

DPL.1

DPL.0

Mnemonic: DPL

BIT NAME FUNCTION

Address: 82h

7-0 DPL.[7:0] This is the low byte of the standard 8052 16-bit data pointer.

DATA POINTER HIGH

Bit:

7

6

5

4

3

2

1

0

DPH.7

DPH.6

DPH.5

DPH.4

DPH.3

DPH.2

DPH.1

DPH.0

Mnemonic: DPH

BIT NAME FUNCTION

Address: 83h

7-0 DPH.[7:0] This is the high byte of the standard 8052 16-bit data pointer.

POWER CONTROL

Bit:

7

6

5

-

4

3

2

1

0

SMOD

SMOD0

POR

GF1

GF0

PD

IDL

Mnemonic: PCON

BIT NAME FUNCTION

1: This bit doubles the serial port baud rate in mode 1, 2, and 3.

Address: 87h

7

6

SMOD

0

0: Framing Error Detection Disable. SCON.7 (SM0/FE) bit is used as SM0

(standard 8052 function).

1: Framing Error Detection Enable. SCON.7 (SM0/FE) bit is used to reflect as

Frame Error (FE) status flag.

5

4

-

Reserved

POR

0: Cleared by software.

1: Set automatically when a power-on reset has occurred.

General purpose user flags.

3

2

1

GF1

GF0

PD

1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are

stopped and program execution is frozen.

Publication Release Date: April 16, 2009

- 19 -

Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

0

IDL

1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock stopped,

so program execution is frozen. But the clock to the serial, timer and interrupt

blocks is not stopped, and these blocks continue operating.

TIMER CONTROL

Bit:

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Mnemonic: TCON

BIT NAME FUNCTION

Address: 88h

7

TF1

Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared

automatically when the program does a timer 1 interrupt service routine. Software

can also set or clear this bit.

6

5

TR1

TF0

Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter on

or off.

Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared

automatically when the program does a timer 0 interrupt service routine. Software

can also set or clear this bit.

4

3

TR0

IE1

Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on

or off.

Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on

INT1. This bit is cleared by hardware when the service routine is vectored to only if

the interrupt was edge triggered. Otherwise it follows the inverse of the pin.

2

1

IT1

IE0

Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level

triggered external inputs.

Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected

onINT0 . This bit is cleared by hardware when the service routine is vectored to

only if the interrupt was edge triggered. Otherwise it follows the inverse of the pin.

0

IT0

Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level

triggered external inputs.

TIMER MODE CONTROL

Bit:

7

6

5

4

3

2

1

0

GATE

M1

M0

GATE

M1

M0

C/T

TIMER1

TIMER0

Mnemonic: TMOD

BIT NAME FUNCTION

Address: 89h

7

GATE

Gating control: When this bit is set, Timer/counter 1 is enabled only while the INT1

pin is high and the TR1 control bit is set. When cleared, the INT1 pin has no effect,

and Timer 1 is enabled whenever TR1 control bit is set.

6

5

Timer or Counter Select: When clear, Timer 1 is incremented by the internal clock.

When set, the timer counts falling edges on the T1 pin.

C/T

M1

Timer 1 mode select bit 1. See table below.

- 20 -

Preliminary W79E4051/W79E2051 Data Sheet

4

3

M0

Timer 1 mode select bit 0. See table below.

GATE

Gating control: When this bit is set, Timer/counter 0 is enabled only while the INT0

pin is high and the TR0 control bit is set. When cleared, the INT0 pin has no

effect, and Timer 0 is enabled whenever TR0 control bit is set.

2

Timer or Counter Select: When clear, Timer 0 is incremented by the internal clock.

When set, the timer counts falling edges on the T0 pin.

C/T

1

0

M1

M0

Timer 0 mode select bit 1. See table below.

Timer 0 mode select bit 0. See table below.

M1, M0: Mode Select bits:

M1

0

M0 MODE

Mode 0: 8-bit timer/counter TLx serves as 5-bit pre-scale.

Mode 1: 16-bit timer/counter, no pre-scale.

0

1

0

1

0

Mode 2: 8-bit timer/counter with auto-reload from THx.

1

Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer0

control bits. TH0 is an 8-bit timer only controlled by Timer1 control bits. (Timer 1)

Timer/Counter 1 is stopped.

1

TIMER 0 LSB

Bit:

7

6

5

4

3

2

1

0

TL0.7

TL0.6

TL0.5

TL0.4

TL0.3

TL0.2

TL0.1

TL0.0

Mnemonic: TL0

Address: 8Ah

BIT NAME

FUNCTION

7-0 TL0.[7:0] Timer 0 LSB.

TIMER 1 LSB

Bit:

7

6

5

4

3

2

1

0

TL1.7

TL1.6

TL1.5

TL1.4

TL1.3

TL1.2

TL1.1

TL1.0

Mnemonic: TL1

Address: 8Bh

BIT NAME

FUNCTION

7-0 TL1.[7:0] Timer 1 LSB.

TIMER 0 MSB

Bit:

7

6

5

4

3

2

1

0

TH0.7

TH0.6

TH0.5

TH0.4

TH0.3

TH0.2

TH0.1

TH0.0

Mnemonic: TH0

BIT NAME FUNCTION

7-0 TH0.[7:0] Timer 0 MSB.

Address: 8Ch

Publication Release Date: April 16, 2009

Revision A06

- 21 -

Preliminary W79E4051/W79E2051 Data Sheet

TIMER 1 MSB

Bit:

7

6

5

4

3

2

1

0

TH1.7

TH1.6

TH1.5

TH1.4

TH1.3

TH1.2

TH1.1

TH1.0

Mnemonic: TH1

BIT NAME FUNCTION

Address: 8Dh

7-0 TH1.[7:0] Timer 1 MSB.

CLOCK CONTROL

Bit:

7

-

6

-

5

-

4

3

2

-

1

-

0

-

T1M

T0M

Mnemonic: CKCON

Address: 8Eh

BIT NAME

7-5 -

FUNCTION

Reserved.

Timer 1 clock select:

4

T1M

0: Timer 1 uses a divide by 12 clocks.

1: Timer 1 uses a divide by 6 clocks.

Timer 0 clock select:

3

T0M

-

0: Timer 0 uses a divide by 12 clocks.

1: Timer 0 uses a divide by 6 clocks.

2-0

Reserved.

CLOCK REGISTER

Bit:

7

-

6

-

5

-

4

-

3

-

2

1

0

-

PWDEX1

PWDEX0

Mnemonic: CLDREG

Address: 8Fh

BIT NAME

FUNCTION

7-5

2

-

Reserved.

PWDEX1 Power Down Exit Mode.

PWDEX0 Power Down Exit Mode.

1

0

-

Reserved.

Power Down Exit Mode:

PWDEX1 PWDEX0 Power Down Exit Mode

0

1

0

1

x

Wake up from Power Down is internally timed.

INT0 or INT1 must be configured for low-level trigger mode.

Wake up from Power Down is externally controlled.

INT0 or INT1 must be configured for low-level trigger mode.

Wake up from Power Down immediately.

INT0 or INT1 can be configured for low-level or edge trigger mode.

- 22 -

Preliminary W79E4051/W79E2051 Data Sheet

PORT 1

Bit:

7

6

5

4

3

2

1

0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

Mnemonic: P1

Address: 90h

P1.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port

read access, however in case of read-modify-write instructions, the port latch is read. These alternate

functions are described below:

BIT NAME

FUNCTION

AN1+

1

0

P1.1

P1.0

AN0-

ANALOG COMPARATOR DEBOUNCE CLOCK CONTROL

Bit:

7

6

-

5

-

4

-

3

-

2

1

0

ENCLK

CPCK2

CPCK1

CPCK0

Mnemonic: ACCK

BIT NAME FUNCTION

Address: 96h

7

ENCLK

1: Enable clock output to the XTAL2 pin (P2.0) when CPU clock is from the

external OSC or on-chip RC oscillator. The frequency of the clock output is 1/4

of the CPU clock rate.

6-3

2

-

Reserved.

CPCK2

CPCK1

CPCK0

See as below table.

1

0

Comparator Debouncing Time Setting:

CPCK2 CPCK 1 CPCK 0 Debouncing Time

0

1

0

1

0

1

0

1

0

1

0

1

0

(3/F_DB)*2~(4/F_DB)*2

(3/F_DB)*4~(4/F_DB)*4

(3/F_DB)*8~(4/F_DB)*8

(3/F_DB)*16~(4/F_DB)*16

(3/F_DB)*32~(4/F_DB)*32

(3/F_DB)*64~(4/F_DB)*64

(3/F_DB)*128~(4/F_DB)*128

ANALOG COMPARATOR CONTROL & STATUS REGISTER

Bit:

7

-

6

-

5

4

3

2

1

0

CIPE

CF

CEN

CM2

CM1

CM0

Mnemonic: ACSR

Address: 97h

Publication Release Date: April 16, 2009

Revision A06

- 23 -

Preliminary W79E4051/W79E2051 Data Sheet

BIT NAME

FUNCTION

7-6

5

-

Reserved.

CIPE

Comparator Enabled in Idle and Power down Mode.

0: Comparator disabled in idle and power down mode. (default)

1: Comparator enabled in idle and power down mode.

4

CF

Comparator Interrupt Flag. Set by hardware when the comparator output meet

the conditions specified by the CM[2:0] bits and CEN is set. The flag must be

cleared by software. The interrupt may be enabled/disabled by setting/clearing

bit 6 of IE.

3

CEN

Enable Comparator. Set this bit to enable the comparator. Clearing this bit will

force the comparator output low and prevent further events from setting CF.

2

1

0

CM2

CM1

CM0

See as below table.

Comparator Interrupt Mode Setting:

CM2

CM1

CM0

Interrupt Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Negative (Low) level

Positive edge

Toggle with debounce

Positive edge with debounce

Negative edge

Toggle

Negative edge with debounce

Positive (High) level

SERIAL PORT CONTROL

Bit:

7

6

5

4

3

2

1

0

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

Mnemonic: SCON

BIT NAME FUNCTION

Address: 98h

7

SM0/FE

Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON

SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is

described below. When used as FE, this bit will be set to indicate an invalid stop

bit. This bit must be manually cleared in software to clear the FE condition.

6

5

SM1

SM2

Serial Port mode select bit 1. See table below.

Multiple processors communication. Setting this bit to 1 enables the

multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2

is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In

mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not

received. In mode 0, the SM2 bit controls the serial port clock. If set to 0, then

the serial port runs at a divide by 12 clock of the oscillator. This gives

compatibility with the standard 8052. When set to 1, the serial clock become

- 24 -

Preliminary W79E4051/W79E2051 Data Sheet

divide by 4 of the oscillator clock. This results in faster synchronous serial

communication.

4

REN

Receive enable:

0: Disable serial reception.

1: Enable serial reception.

3

2

1

TB8

RB8

TI

This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared

by software as desired.

In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is

the stop bit that was received. In mode 0 it has no function.

Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time

in mode 0, or at the beginning of the stop bit in all other modes during serial

transmission. This bit must be cleared by software.

SM1, SM0: Mode Select bits:

Mode SM0

SM1

Description

Length

Baud Rate

0

1

2

3

0

1

0

1

0

1

Synchronous

Asynchronous

8

Tclk divided by 4 or 12

Variable

10

11

Tclk divided by 32 or 64

Variable

SERIAL DATA BUFFER

Bit:

7

6

5

4

3

2

1

0

SBUF.7

SBUF.6

SBUF.5

SBUF.4

SBUF.3

SBUF.2

SBUF.1

SBUF.0

Mnemonic: SBUF

Address: 99h

BIT NAME

FUNCTION

7~0 SBUF

Serial data on the serial port is read from or written to this location. It actually

consists of two separate internal 8-bit registers. One is the receive resister, and

the other is the transmit buffer. Any read access gets data from the receive data

buffer, while write access is to the transmit data buffer.

PORT 2

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

0

P2.1

P2.0

Mnemonic: P2

Address: A0h

BIT NAME

ALTERNATE FUNCTION

Reserved

7-2

1

-

P2.1

P2.0

XTAL1 clock input pin.

0

XTAL2 or CLKOUT pin by alternative.

AUX FUNCTION REGISTER 1

Publication Release Date: April 16, 2009

Revision A06

- 25 -

Preliminary W79E4051/W79E2051 Data Sheet

Bit:

7

6

5

4

3

2

1

0

BOF

BOD

BOI

LPBOV

SRST

BOV1

BOV0

BOS

Mnemonic: AUXR1

BIT NAME FUNCTION

Address: A2h

Brown Out Flag

0: Cleared by software.

7

6

BOF

BOD

1: Set automatically when a brownout reset or interrupt has occurred. Also set at

power on.

Brown Out Disable:

BOD is initialized at reset with the inversed value of bit CBOD in config0-bits.

0: Enable Brownout Detect function.

1: Disable Brownout Detect function and save power.

Brown Out Interrupt:

0: Disable Brownout Detect Interrupt function and it will cause chip reset when

BOF is set.

5

BOI

1: This prevents Brownout Detection from causing a chip reset and allows the

Brownout Detect function to be used as an interrupt.

Low Power Brown Out Detect control:

0: If bit BOD=0, the Brown Out detection is always active.

4

3

LPBOV

SRST

1: If bit BOD=0, the Brown Out detection repeats to senses the voltage for

64/f_BRCthen turn off detector for 960/f_BRC, therefore, it saves 15/16 of the

Brownout circuit power.

Software reset:

This bit has TA(Time Accessed) protection in write access.

1: reset the chip as if a hardware reset occurred.

Brownout voltage selection bits:

(BOV1,BOV0) are initialized at reset with the reversed value of bits

(CBOV1,CBOV0) in config0-bits

BOV.1

BOV.0 Brownout Voltage

BOV1,

BOV0

2~1

0

1

0

1

0

1

Brownout voltage is 2.4V

Brownout voltage is 2.7V

Brownout voltage is 3.8V

Brownout voltage is 4.5V

Brownout Status bit(Read only)

0: V_DDis above V_BOR+

0

BOS

1: V_DDis below V_BOR-

Brownout Voltage Selection

BOV0 Brownout Voltage

BOV1

0

1

0

1

0

Brownout voltage is 2.4V

Brownout voltage is 2.7V

Brownout voltage is 3.8V

- 26 -

Preliminary W79E4051/W79E2051 Data Sheet

1

Brownout voltage is 4.5V

All the bits in this SFR have unrestricted read access. SRST require Timed Access procedure to write.

The remaining bits have unrestricted write accesses. Please refer TA register description.

AUX FUNCTION REGISTER 2

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

DPS

Mnemonic: AUXR2

BIT NAME FUNCTION

Reserved

Dual Data Pointer Select

Address: A3h

7-1

0

-

DPS

0: To select DPTR of standard 8051.

1: To select DPTR1

INTERRUPT ENABLE

Bit:

7

6

5

-

4

3

2

1

0

EA

EC

ES

ET1

EX1

ET0

EX0

Mnemonic: IE

Address: A8h

BIT NAME

FUNCTION

7

6

5

4

3

2

1

0

EA

Global enable. Enable/Disable all interrupts.

Enable analog comparator interrupt.

Reserved.

EC

-

ES

Enable Serial Port 0 interrupt.

Enable Timer 1 interrupt.

ET1

EX1

ET0

EX0

Enable external interrupt 1.

Enable Timer 0 interrupt.

Enable external interrupt 0.

SLAVE ADDRESS

Bit:

7

6

5

4

3

2

1

0

SADDR.7

SADDR.6

SADDR.5

SADDR.4

SADDR.3

SADDR.2

SADDR.1

SADDR.0

Mnemonic: SADDR

BIT NAME FUNCTION

Address: A9h

7~0

SADDR

The SADDR should be programmed to the given or broadcast address for serial

port to which the slave processor is designated.

PORT 3

Bit:

7

6

5

4

3

2

1

0

Publication Release Date: April 16, 2009

Revision A06

- 27 -

Preliminary W79E4051/W79E2051 Data Sheet

P3.7

CMP_O

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

Mnemonic: P3

Address: B0h

P3.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port

read access, however in case of read-modify-write instructions, the port latch is read. These

alternate functions are described below:

BIT NAME

FUNCTION

7

6

5

4

3

P3.7

-

CMP_O

P3.5

Read only. This bit stores the hardware comparator result.

T1 or PWM output

T0

P3.4

P3.3

INT1

2

P3.2

INT0

TX

1

0

P3.1

P3.0

RX

Port1 Output Mode 1

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

0

P1M1.1

P1M1.0

Mnemonic: P1M1

Address: B3h

BIT NAME

FUNCTION

7-2 Reserved

1

P1M1.1

0: P1.1 is in open drain mode. (Default)

1: P1.1 is in Quasi-bidirection mode

0: P1.0 is in open drain mode. (Default)

1: P1.0 is in Quasi-bidirection mode

0

P1M1.0

Interrupt High Priority 0

Bit:

7

-

6

5

-

4

3

2

1

0

PCH

PSH

PT1H

PX1H

PT0H

PX0H

Mnemonic: IP0H

BIT NAME FUNCTION

Reserved

Address: B7h

7

6

5

4

3

2

1

0

-

PCH

-

1: To set interrupt high priority of analog comparator is highest priority level.

Reserved.

PSH

PT1H

PX1H

PT0H

PX0H

1: To set interrupt high priority of Serial port 0 is highest priority level.

1: To set interrupt high priority of Timer 1 is highest priority level.

1: To set interrupt high priority of External interrupt 1 is highest priority level.

1: To set interrupt high priority of Timer 0 is highest priority level.

1: To set interrupt high priority of External interrupt 0 is highest priority level.

- 28 -

Preliminary W79E4051/W79E2051 Data Sheet

Interrupt Priority 0

Bit:

7

6

5

4

3

2

1

0

-

PC

-

PS

PT1

PX1

PT0

PX0

Address: B8h

Mnemonic: IP0

BIT NAME

FUNCTION

This bit is un-implemented and will read high.

7

6

5

4

3

2

1

0

-

PC

-

1: To set interrupt priority of analog comparator is higher priority level.

This bit is un-implemented and will read high.

PS

PT1

PX1

PT0

PX0

1: To set interrupt priority of Serial port 0 is higher priority level.

1: To set interrupt priority of Timer 1 is higher priority level.

1: To set interrupt priority of External interrupt 1 is higher priority level.

1: To set interrupt priority of Timer 0 is higher priority level.

1: To set interrupt priority of External interrupt 0 is higher priority level.

SLAVE ADDRESS MASK ENABLE

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Mnemonic: SADEN

Address: B9h

BIT NAME

FUNCTION

7~0 SADEN

This register enables the Automatic Address Recognition feature of the Serial

port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will

be compared with the incoming serial data. When SADEN is 0, then the bit

becomes a "don't care" in the comparison. This register enables the Automatic

Address Recognition feature of the Serial port 0. When all the bits of SADEN are

0, interrupt will occur for any incoming address.

NVM BYTE ADDRESS

Bit:

7

6

5

4

3

2

1

0

NVMADD

R.7

NVMADD

R.6

NVMADD

R.5

NVMADD

R.4

NVMADD

R.3

NVMADD

R.2

NVMADD

R.1

NVMADD

R.0

Mnemonic: NVMADDRL

Address: C6h

BIT NAME

NVMADDR.7

FUNCTION

7

Must be 0.

6~0 NVMADDR.[6:0] The NVM low byte address:

The register indicates NVM data memory address on On-Chip code

memory space.

Publication Release Date: April 16, 2009

- 29 -

Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

TIMED ACCESS

Bit:

7

6

5

4

3

2

1

0

TA.7

TA.6

TA.5

TA.4

TA.3

TA.2

TA.1

TA.0

Mnemonic: TA

Address: C7h

BIT NAME

FUNCTION

7-0 TA.[7:0]

The Timed Access register:

The Timed Access register controls the access to protected bits. To access

protected bits, the user must first write AAH to the TA. This must be immediately

followed by a write of 55H to TA. Now a window is opened in the protected bits

for three machine cycles, during which the user can write to these bits.

NVM CONTROL

Bit:

7

6

5

-

4

-

3

-

2

-

1

-

0

-

EER

EWR

Mnemonic: NVMCON

Address: CEh

BIT

NAME

FUNCTION

NVM page(n) erase bit:

0: Without erase NVM page(n).

7

EER

1: Set this bit to erase page(n) of NVM. The NVM has 8 pages and each page

have 16 bytes data memory. Initiate page select by programming NVMADDRL

registers, which will automaticly enable page area. When user set this bit, the

page erase process will begin and program counter will halt at this instruction.

After the erase process is completed, program counter will continue executing

next instruction.

6

EWR

NVM data write bit:

0: Without write NVM data.

1: Set this bit to write NVM bytes and program counter will halt at this instruction.

After write is finished, program counter will kept next instruction then executed.

5-0

-

Reserved.

NVM DATA

Bit:

7

6

5

4

3

2

1

0

NVMDAT

A.7

NVMDAT

A.6

NVMDAT

A.5

NVMDAT

A.4

NVMDAT

A3

NVMDAT

A.2

NVMDAT

A.1

NVMDAT

A.0

Mnemonic: NVMDATA

BIT NAME FUNCTION

Address: CFh

7~0 NVMDATA[7:0] The NVM data write register. The read NVM data is by MOVC instruction.

PROGRAM STATUS WORD

Bit:

7

6

5

4

3

2

1

0

CY

AC

F0

RS1

RS0

OV

F1

P

- 30 -

Preliminary W79E4051/W79E2051 Data Sheet

Mnemonic: PSW

Address: D0h

BIT NAME FUNCTION

7

CY

Carry flag:

Set for an arithmetic operation which results in a carry being generated from the

ALU. It is also used as the accumulator for the bit operations.

6

5

AC

F0

Auxiliary carry:

Set when the previous operation resulted in a carry from the high order nibble.

User flag 0:

The General purpose flag that can be set or cleared by the user.

Register bank select bits:

4

3

2

RS1

RS0

OV

Register bank select bits:

Overflow flag:

Set when a carry was generated from the seventh bit but not from the 8^thbit as a

result of the previous operation, or vice-versa.

1

0

F1

P

User Flag 1:

The General purpose flag that can be set or cleared by the user by software.

Parity flag:

Set/cleared by hardware to indicate odd/even number of 1’s in the accumulator.

RS.1-0: Register bank selection bits:

RS1

RS0

Register bank Address

0

1

0

1

0

1

0

1

2

3

00-07h

08-0Fh

10-17h

18-1Fh

PWM COUNTER HIGH BITS REGISTER

Bit:

7

-

6

-

5

-

4

3

-

2

-

1

0

-

PWMP.9

PWMP.8

Mnemonic: PWMPH

Address: D1h

BIT NAME

FUNCTION

7-2

1-0

-

Reserved.

PWMP.[9:8] The PWM Counter Register bits 9~8.

PWM 0 HIGH BITS REGISTER

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

0

PWM0.9

PWM0.8

Mnemonic: PWM0H

Address: D2h

BIT NAME

FUNCTION

Publication Release Date: April 16, 2009

Revision A06

- 31 -

Preliminary W79E4051/W79E2051 Data Sheet

7~2

-

Reserved.

1~0 PWM0.9~8 The PWM 0 Register bit 9~8.

PWM CONTROL REGISTER 3

Bit:

7

-

6

-

5

-

4

3

-

2

-

1

0

PWM0OE

FP1

FP0

Mnemonic: PWMCON3

Name Function

Address: D7h

Bit

7

6

5

PWM0 output enable bit.

PWM0OE 0: PWM0 output disabled.

4

1: PWM0 output enabled. If P3.5 is set to high PWM0 will output through P3.5.

Reserved.

3~2

-

Select PWM frequency pre-scale select bits. The clock source of pre-scaler is in

phase with Fosc if PWMRUN=1, otherwise it is disabled.

1~0 FP1~0

FP1~0: PWM Prescaler select bits:

FP[1:0]

00

Fpwm

FOSC

01

FOSC/2

FOSC/4

FOSC/16

10

11

WATCHDOG CONTROL

Bit:

7

6

-

5

4

3

2

1

0

WDRUN

WD1

WD0

WDIF

WTRF

EWRST

WDCLR

Mnemonic: WDCON

Address: D8h

BIT

7

NAME

FUNCTION

0: The Watchdog is stopped.

1: The Watchdog is running.

Reserved.

WDRUN

-

6

- 32 -

Preliminary W79E4051/W79E2051 Data Sheet

Watchdog Timer Time-out Select bits. These bits determine the time-out period of

the watchdog timer. The reset time-out period is 512 clocks longer than the

watchdog time-out.

WD1

WD0

Interrupt time-

out

Reset

time-out

5~4 WD1~WD0

0

1

0

1

0

1

2¹⁷

2²⁰

2²³

2²⁶

2¹⁷+ 512

2²⁰+ 512

2²³+ 512

2²⁶+ 512

Watchdog Timer Interrupt flag:

0: If the interrupt is not enabled, then this bit indicates that the time-out period has

elapsed. This bit must be cleared by software.

3

WDIF

1: If the watchdog interrupt is enabled, hardware will set this bit to indicate that the

watchdog interrupt has occurred.

Watchdog Timer Reset flag:

1: Hardware will set this bit when the watchdog timer causes a reset. Software can

read it but must clear it manually. A power-fail reset will also clear the bit. This

bit helps software in determining the cause of a reset. If EWRST = 0, the

watchdog timer will have no affect on this bit.

2

1

WTRF

0: Disable Watchdog Timer Reset.

1: Enable Watchdog Timer Reset.

Reset Watchdog Timer:

EWRST

This bit helps in putting the watchdog timer into a know state. It also helps in

resetting the watchdog timer before a time-out occurs. Failing to set the EWRST

before time-out will cause an interrupt (if EWDI (EIE.4) is set), and 512 clocks

after that a watchdog timer reset will be generated (if EWRST is set). This bit is

self-clearing by hardware.

0

WDCLR

The WDCON SFR is set to a 0x000000B on a power-on-reset. WTRF (WDCON.2) is set to a 1 on

a Watchdog timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by

an external reset. EWRST (WDCON.1) is set to 0 on all resets.

All the bits in this SFR have unrestricted read access. WDRUN, EWRST, WDIF and WDCLR

require Timed Access procedure to write. The remaining bits have unrestricted write accesses.

Please refer TA register description.

TA

REG

C7H

D8H

WDCON

MOV

SETB

ORL

REG

TA, #AAH

TA, #55H

WDCON.0

; To access protected bits

; Reset watchdog timer

WDCON, #00110000B

TA, #AAH

; Select 26 bits watchdog timer

MOV

ORL

TA, #55H

WDCON, #00000010B

; Enable watchdog

Publication Release Date: April 16, 2009

Revision A06

- 33 -

Preliminary W79E4051/W79E2051 Data Sheet

PWM COUNTER LOW BITS REGISTER

Bit:

7

6

5

4

3

2

1

0

PWMP.7

PWMP.6

PWMP.5

PWP.4

PWMP.3

PWMP.2

PWMP.1

Mnemonic: PWMPL

Name Function

7~0 PWMP PWM Counter Low Bits Register.

Address: D9h

Bit

PWM 0 LOW BITS REGISTER

Bit:

7

6

5

4

3

2

1

0

PWM0.7

PWM0.6

PWM0.5

PWM0.4

PWM0.3

PWM0.2

PWM0.1

Mnemonic: PWM0L

Name Function

7~0 PWM0 PWM 0 Low Bits Register.

Address: DAh

Bit

PWM CONTROL REGISTER 1

Bit:

7

6

5

4

3

-

2

-

1

-

0

PWMRUN Load

PWMF

CLRPWM

PWM0I

Mnemonic: PWMCON1

Address: DCh

Bit

Name

Function

Enable PWM running bit

7

PWMRUN 0: The PWM is not running.

1: The PWM counter is running.

Enable PWM counter and register re-load

0: The registers value of PWMP and Comparators are never loaded to counter

and Comparator registers.

6

Load

1: The PWMP register will be load value to counter register after counter

underflow and hardware will clear by next clock cycle.

PWM underflow flag.

0: No underflow.

5

PWMF

1: PWM 10-bit down counter underflows (PWM interrupt is requested if PWM

interrupt is enabled).

Clear PWM counter

4

CLRPWM 1: Clear 10-bit PWM counter to 000H.

It is automatically cleared by hardware.

3~1

0

-

Reserved

Inverse PWM output level

0: PWM0 output is non-inverted.

1: PWM0 output is inverted.

PWM0I

- 34 -

Preliminary W79E4051/W79E2051 Data Sheet

ACCUMULATOR

Bit:

7

6

5

4

3

2

1

0

ACC.7

ACC.6

ACC.5

ACC.4

ACC.3

ACC.2

ACC.1

ACC.0

Mnemonic: ACC

Name Function

7-0 ACC The A or ACC register is the standard 8052 accumulator.

Address: E0h

Bit

INTERRUPT ENABLE REGISTER 1

Bit:

7

-

6

5

4

3

-

2

-

1

-

0

-

EBOV

EPWM

EWDI

Mnemonic: EIE

Address: E8h

BIT NAME

FUNCTION

7

6

-

Reserved.

EBOV

0: Disable Brownout interrupt.

1: Enable Brownout interrupt.

5

EPWM

EWDI

-

0: Disable PWM underflow interrupt.

1: Enable PWM underflow interrupt.

0: Disable Watchdog Timer Interrupt.

1: Enable Watchdog Timer Interrupt.

Reserved.

4

3-0

B REGISTER

Bit:

7

6

5

4

3

2

1

0

B.7

B.6

B.5

B.4

B.3

B.2

B.1

B.0

Mnemonic: B

Address: F0h

Bit

7-0

Name

Function

B

The B register is the standard 8052 register that serves as a second accumulator.

PORT COMPARATOR INPUT DISABLE

Bit:

7

6

5

4

-

3

-

2

-

1

0

-

Bit1

Bit0

Mnemonic: PCMPIDS

Address: F6h

Bit

Name

Function

Reserved

7-2

1

-

PCMPIDS.1 P1.1 digital input disable bit.

0: Default (With digital/analog input).

1: Disable Digital Input of Comparator Input 1(Negative end)

Publication Release Date: April 16, 2009

Revision A06

- 35 -

Preliminary W79E4051/W79E2051 Data Sheet

0

PCMPIDS.0 P1.0 digital input disable bit.

0: Default (With digital/analog input).

1: Disable Digital Input of Comparator Input 1(Positive end)

INTERRUPT HIGH PRIORITY 1

Bit:

7

-

6

5

4

3

-

2

-

1

-

0

-

PBOVH

PPWMH

PWDIH

Mnemonic: IP1H

Address: F7h

BIT NAME

FUNCTION

7

-

Reserved.

6

PBOVH

PPWMH

PWDIH

-

1: To set interrupt priority of Brownout interrupt is highest priority level.

1: To set interrupt priority of PWM underflow is highest priority level.

1: To set interrupt high priority of Watchdog is highest priority level.

Reserved.

5

4

3-0

EXTENDED INTERRUPT PRIORITY

Bit:

7

-

6

5

4

3

-

2

-

1

-

0

-

PBOV

PPWM

PWDI

Mnemonic: IP1

Address: F8h

BIT NAME

FUNCTION

7

-

Reserved.

6

PBOV

PPWM

PWDI

-

1: To set interrupt priority of Brownout interrupt is higher priority level.

1: To set interrupt priority of PWM underflow is higher priority level.

1: To set interrupt priority of Watchdog is higher priority level.

Reserved.

5

4

3-0

- 36 -

Preliminary W79E4051/W79E2051 Data Sheet

9

INSTRUCTION

The W79E4051/2051 series execute all the instructions of the standard 8052 family. The operations of

these instructions, as well as their effects on flag and status bits, are exactly same. However, the

timing of these instructions is different in two ways. Firstly, the machine cycle is four clock periods,

while the standard-8051/52 machine cycle is twelve clock periods. Secondly, it can fetch only once per

machine cycle (i.e., four clocks per fetch), while the standard 8051/52 can fetch twice per machine

cycle (i.e., six clocks per fetch).

The timing differences create an advantage for the W79E4051/2051 series. There is only one fetch

per machine cycle, so the number of machine cycles is usually equal to the number of operands in the

instruction. (Jumps and calls do require an additional cycle to calculate the new address.) As a result,

the W79E4051/2051 series reduces the number of dummy fetches and wasted cycles, and therefore

improves overall efficiency, compared to the standard 8051/52.

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

NOP

00

28

29

2A

2B

2C

2D

2E

2F

26

27

25

24

38

39

3A

3B

3C

3D

3E

3F

36

1

2

1

2

1

4

8

4

12

3

ADD A, R0

ADD A, R1

ADD A, R2

ADD A, R3

ADD A, R4

ADD A, R5

ADD A, R6

ADD A, R7

ADD A, @R0

ADD A, @R1

ADD A, direct

ADD A, #data

ADDC A, R0

ADDC A, R1

ADDC A, R2

ADDC A, R3

ADDC A, R4

ADDC A, R5

ADDC A, R6

ADDC A, R7

ADDC A, @R0

3

1.5

3

Publication Release Date: April 16, 2009

Revision A06

- 37 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

ADDC A, @R1

ADDC A, direct

ADDC A, #data

SUBB A, R0

SUBB A, R1

SUBB A, R2

SUBB A, R3

SUBB A, R4

SUBB A, R5

SUBB A, R6

SUBB A, R7

SUBB A, @R0

SUBB A, @R1

SUBB A, direct

SUBB A, #data

INC A

37

35

34

98

99

9A

9B

9C

9D

9E

9F

96

97

95

94

04

08

09

0A

0B

0C

0D

0E

0F

06

07

05

A3

14

18

19

1A

1B

1C

1

2

1

2

1

2

1

2

1

2

1

2

1

4

8

4

8

4

8

4

12

24

12

3

1.5

3

1.5

3

INC R0

3

INC R1

3

INC R2

3

INC R3

3

INC R4

3

INC R5

3

INC R6

3

INC R7

3

INC @R0

INC @R1

INC direct

INC DPTR

DEC A

3

1.5

3

DEC R0

3

DEC R1

3

DEC R2

3

DEC R3

3

DEC R4

3

- 38 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

DEC R5

1D

1E

1F

16

17

15

A4

84

D4

58

59

5A

5B

5C

5D

5E

5F

56

57

55

54

52

53

48

49

4A

4B

4C

4D

4E

4F

46

47

1

2

1

2

3

1

2

5

1

2

3

1

4

8

20

4

8

12

4

12

48

12

24

12

3

DEC R6

3

DEC R7

3

DEC @R0

DEC @R1

DEC direct

MUL AB

3

1.5

2.4

3

DIV AB

DA A

ANL A, R0

ANL A, R1

ANL A, R2

ANL A, R3

ANL A, R4

ANL A, R5

ANL A, R6

ANL A, R7

ANL A, @R0

ANL A, @R1

ANL A, direct

ANL A, #data

ANL direct, A

ANL direct, #data

ORL A, R0

ORL A, R1

ORL A, R2

ORL A, R3

ORL A, R4

ORL A, R5

ORL A, R6

ORL A, R7

ORL A, @R0

ORL A, @R1

3

1.5

2

3

Publication Release Date: April 16, 2009

Revision A06

- 39 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

ORL A, direct

ORL A, #data

ORL direct, A

ORL direct, #data

XRL A, R0

XRL A, R1

XRL A, R2

XRL A, R3

XRL A, R4

XRL A, R5

XRL A, R6

XRL A, R7

XRL A, @R0

XRL A, @R1

XRL A, direct

XRL A, #data

XRL direct, A

XRL direct, #data

CLR A

45

44

42

43

68

69

6A

6B

6C

6D

6E

6F

66

67

65

64

62

63

E4

F4

23

33

03

13

C4

E8

E9

EA

EB

EC

ED

EE

EF

E6

2

3

1

2

3

1

2

3

1

2

3

1

8

12

4

8

12

4

12

24

12

24

12

1.5

2

3

1.5

2

3

CPL A

3

RL A

3

RLC A

3

RR A

3

RRC A

3

SWAP A

3

MOV A, R0

MOV A, R1

MOV A, R2

MOV A, R3

MOV A, R4

MOV A, R5

MOV A, R6

MOV A, R7

MOV A, @R0

3

- 40 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

MOV A, @R1

MOV A, direct

MOV A, #data

MOV R0, A

E7

E5

74

1

2

1

2

1

2

1

2

1

2

1

2

4

8

4

8

4

8

12

3

1.5

3

F8

F9

FA

FB

FC

FD

FE

FF

A8

A9

AA

AB

AC

AD

AE

AF

78

MOV R1, A

3

MOV R2, A

3

MOV R3, A

3

MOV R4, A

3

MOV R5, A

3

MOV R6, A

3

MOV R7, A

3

MOV R0, direct

MOV R1, direct

MOV R2, direct

MOV R3, direct

MOV R4, direct

MOV R5, direct

MOV R6, direct

MOV R7, direct

MOV R0, #data

MOV R1, #data

MOV R2, #data

MOV R3, #data

MOV R4, #data

MOV R5, #data

MOV R6, #data

MOV R7, #data

MOV @R0, A

MOV @R1, A

MOV @R0, direct

MOV @R1, direct

MOV @R0, #data

MOV @R1, #data

1.5

3

79

7A

7B

7C

7D

7E

7F

F6

F7

A6

A7

76

3

1.5

77

Publication Release Date: April 16, 2009

Revision A06

- 41 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

MOV direct, A

MOV direct, R0

MOV direct, R1

MOV direct, R2

MOV direct, R3

MOV direct, R4

MOV direct, R5

MOV direct, R6

MOV direct, R7

MOV direct, @R0

MOV direct, @R1

MOV direct, direct

MOV direct, #data

MOV DPTR, #data 16

MOVC A, @A+DPTR

MOVC A, @A+PC

MOVX A, @R0

MOVX A, @R1

MOVX A, @DPTR

MOVX @R0, A

MOVX @R1, A

MOVX @DPTR, A

PUSH direct

F5

88

2

3

1

2

1

2

8

12

24

12

1.5

2

8

1.5

89

2

8

1.5

8A

8B

8C

8D

8E

8F

86

2

8

1.5

2

8

1.5

2

8

1.5

2

8

1.5

2

8

1.5

2

8

1.5

2

8

1.5

87

2

8

1.5

85

3

12

2

75

3

12

2

90

3

12

2

93

2

8

3

83

2

8

3

E2

E3

E0

F2

F3

F0

C0

D0

C8

C9

CA

CB

CC

CD

CE

CF

C6

C7

2 - 9

8 - 36

3 - 0.66

2 - 9

8 - 36

3 - 0.66

2 - 9

8 - 36

3 - 0.66

2 - 9

8 - 36

3 - 0.66

2 - 9

8 - 36

3 - 0.66

2 - 9

2

8 - 36

3 - 0.66

8

4

3

POP direct

2

XCH A, R0

1

XCH A, R1

1

XCH A, R2

1

XCH A, R3

1

XCH A, R4

1

XCH A, R5

1

XCH A, R6

1

XCH A, R7

1

XCH A, @R0

1

XCH A, @R1

1

- 42 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

XCHD A, @R0

XCHD A, @R1

XCH A, direct

CLR C

D6

D7

C5

C3

C2

D3

D2

B3

B2

82

B0

72

A0

A2

92

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

4

8

4

8

4

8

4

8

6

8

6

8

12

24

12

24

3

1.5

3

CLR bit

1.5

3

SETB C

SETB bit

1.5

3

CPL C

CPL bit

1.5

3

ANL C, bit

ANL C, /bit

ORL C, bit

ORL C, /bit

MOV C, bit

MOV bit, C

ACALL addr11

3

1.5

3

71, 91, B1,

11, 31, 51,

D1, F1

2

LCALL addr16

RET

12

22

32

3

1

2

4

2

3

16

8

24

1.5

3

RETI

8

3

AJMP ADDR11

01, 21, 41,

61, 81, A1,

C1, E1

12

2

LJMP addr16

JMP @A+DPTR

SJMP rel

JZ rel

02

73

80

60

70

40

50

20

30

10

3

1

2

3

4

2

3

4

16

6

24

1.5

3

12

16

2

JNZ rel

2

JC rel

2

JNC rel

2

JB bit, rel

JNB bit, rel

JBC bit, rel

1.5

Publication Release Date: April 16, 2009

Revision A06

- 43 -

Preliminary W79E4051/W79E2051 Data Sheet

Op-code

HEX Code

Bytes

W79E4051 W79E4051 8032

W79E4051/205

1 series vs.

8032 Speed

Ratio

/2051

Clock

series

Machine

Cycle

series

Clock

cycles

CJNE A, direct, rel

CJNE A, #data, rel

CJNE @R0, #data, rel

CJNE @R1, #data, rel

CJNE R0, #data, rel

CJNE R1, #data, rel

CJNE R2, #data, rel

CJNE R3, #data, rel

CJNE R4, #data, rel

CJNE R5, #data, rel

CJNE R6, #data, rel

CJNE R7, #data, rel

DJNZ R0, rel

B5

B4

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

D8

D9

DD

DA

DB

DC

DE

DF

D5

3

2

3

4

3

4

16

12

16

24

1.5

2

DJNZ R1, rel

2

DJNZ R5, rel

2

DJNZ R2, rel

2

DJNZ R3, rel

2

DJNZ R4, rel

2

DJNZ R6, rel

2

DJNZ R7, rel

2

DJNZ direct, rel

1.5

Table 9-1: Instruction Set for W79E4051/2051

- 44 -

Preliminary W79E4051/W79E2051 Data Sheet

9.1 Instruction Timing

In W79E4051/2051 series, each machine cycle is four clock periods long. Each clock period is called a

state, and each machine cycle consists of four states: C1, C2 C3 and C4, in order. Both clock edges

are used for internal timing, so the duty cycle of the clock should be as close to 50% as possible to

avoid timing conflicts.

The W79E4051/2051 series does one op-code fetch per machine cycle, so, in most instructions, the

number of machine cycles required is equal to the number of bytes in the instruction. There are 256

available op-codes. 128 of them are single-cycle instructions, so many op-codes are executed in just

four clocks period. Some of the other op-codes are two-cycle instructions, and most of these have

two-byte op-codes. However, there are some instructions that have one-byte instructions yet take two

cycles to execute.

Publication Release Date: April 16, 2009

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Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

10 POWER MANAGEMENT

The W79E4051/2051 series has several features that help the user to control the power consumption

of the device. These modes are discussed in the next two sections.

10.1 Idle Mode

The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the

idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle

mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer, PWM, Analog

Comparator(CIPE=1) and Serial port blocks. This forces the CPU state to be frozen; the Program

counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold

their contents. The port pins hold the logical states they had at the time Idle was activated. The Idle

mode can be terminated in two ways. Since the interrupt controller is still active, the activation of any

enabled interrupt can wake up the processor. This will automatically clear the Idle bit, terminate the

Idle mode, and the Interrupt Service Routine (ISR) will be executed. After the ISR, execution of the

program will continue from the instruction which put the device into Idle Mode.

The Idle mode can also be exited by activating the reset. The device can put into reset either by

applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The

external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be

recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the

SFRs are set to the reset condition. Since the clock is already running there is no delay and execution

starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out

will cause a watchdog timer interrupt which will wake up the device. The software must reset the

Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.

When the W79E4051/2051 series are exiting from an Idle Mode with a reset, the instruction following

the one which put the device into Idle Mode is not executed. So there is no danger of unexpected

writes.

P1.0 and P1.1 should be set to 1 if external pull-ups are applied, or set to 0 if without external pull-ups,

or configured to quasi I/O mode by setting P1M1 bit0 and bit1 to high.

10.2 Power Down Mode

The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does

this will be the last instruction to be executed before the device goes into Power Down mode. In the

Power Down mode, all the clocks are stopped and the device comes to a halt. All activity, exception of

Brownout reset, INT1,

INT0 , watchdog timer(Config0.WDTCK=0) and Analog Comparator(CIPE=1),

is completely stopped and the power consumption is reduced to the lowest possible value. The port

pins output the values held by their respective SFRs.

Before CPU enters power-down mode, P1.0 and P1.1 should be set to 1 if external pull-ups are

applied, or set to 0 if without external pull-ups, or configured to quasi I/O mode by setting P1M1 bit0

and bit1 to high.

An external reset can be used to exit the Power down state. The high on RST pin terminates the

Power Down mode, and restarts the clock. The program execution will restart from 0000h. In the

Power down mode, the clock is stopped, so the Watchdog timer cannot be used to provide the reset to

exit Power down mode when its clock source is external OSC or crystal.

The sources that can wake up from the power down mode are external interrupts, brownout reset

(BOR), watchdog timer interrupt (if Config0 bit WDTCK = 0) and Analog Comparator(if SFR bit

- 46 -

Preliminary W79E4051/W79E2051 Data Sheet

CIPE=1). The W79E4051/2051 series can be waken up from the Power Down mode by forcing the

above sources activation, provided the corresponding interrupt is enabled, while the global enable

(EA) bit is set. If these conditions are met, then interrupt event will re-start the oscillator. The device

will then execute the interrupt service routine for the corresponding external interrupt. After the

interrupt service routine is completed, the program execution returns to the instruction after one which

put the device into Power Down mode and continues from there. During Power down mode, if

AUXR1.LPBOV = 1 and AUXR1.BOD = 0, the internal RC clock will be enabled and hence save

power.

In W79E4051/2051 series either a low-level or a falling-edge at external interrupt pin, INT1 or

INT0 will re-start the oscillator. W79E4051/2051 provides 3 wake-up modes, selected by SFR

bits PWDEX1 and PWDEX0, that the external interrupt pins can terminate power-down mode.

Refer to the table below.

PWDEX[1:0] TRIGGER

TYPE

FUNCTION TO TERMINATE POWER-DOWN MODE

0, 0

Low-level

INT0, INT1

(Mode1)

Keep low over

Tpd

Oscillator re-start,

Program resume

0, 1

Low-level

INT0, INT1

Oscillator re-start,

Program resume

(Mode2)

Keep low over

Tpd

CPU keep in

power-down mode

1, x

Low-level

and

Falling-

edge

INT0, INT1

(Mode3)

Oscillator re-start,

Program resume

Low-level

Falling-edge

In mode1 and mode2, the external interrupt pin must keep low longer than Tpd otherwise CPU stays

in power-down mode continuously. Tpd is about 2mS counted by built-in RC oscillator.

Publication Release Date: April 16, 2009

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Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

11 RESET CONDITIONS

The user has several hardware related options for placing the W79E4051/2051 series into reset

condition. In general, most register bits go to their reset value irrespective of the reset condition, but

there are a few flags whose state depends on the source of reset. The user can use these flags to

determine the cause of reset using software.

11.1 Sources of reset

11.1.1 External Reset

The device samples the RST pin every machine cycle during state C4. The RST pin must be held high

for at least two machine cycles before the reset circuitry applies an internal reset signal. Thus, this

reset is a synchronous operation and requires the clock to be running.

The device remains in the reset state as long as RST pin is high and remains high up to two machine

cycles after RST is deactivated. Then, the device begins program execution at 0000h. There are no

flags associated with the external reset, but, since the other two reset sources do have flags, the

external reset is the cause if those flags are clear.

11.1.2 Power-On Reset (POR)

If the power supply falls below V_RST, the device goes into the reset state. When the power supply

returns to proper levels, the device performs a power-on reset and sets the POR flag. The software

should clear the POR flag, or it will be difficult to determine the source of future resets. V_RSTis about

2.0V.

11.1.3 Brown-Out Reset (BOR)

If the power supply falls below brownout voltage of V_BOV, the device goes into the reset state. When

the power supply returns to proper levels, the device performs a brownout reset.

11.1.4 Watchdog Timer Reset

The Watchdog Timer is a free-running timer with programmable time-out intervals. The program must

clear the Watchdog Timer before the time-out interval is reached to restart the count. If the time-out

interval is reached, an interrupt flag is set. 512 clocks later, if the Watchdog Reset is enabled and the

Watchdog Timer has not been cleared, the Watchdog Timer generates a reset. The reset condition is

maintained by the hardware for two machine cycles, and the WTRF bit in WDCON is set. Afterwards,

the device begins program execution at 0000h.

11.2 Reset State

When the device is reset, most registers return to their initial state. The Watchdog Timer is disabled if

the reset source was a power-on reset. The port registers are set to FFh, which puts most of the port

pins in a high state. The Program Counter is set to 0000h, and the stack pointer is reset to 07h. After

this, the device remains in the reset state as long as the reset conditions are satisfied.

Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains

above approximately 2V, the minimum operating voltage for the RAM. If VDD falls below 2V, the RAM

contents are also lost. In either case, the stack pointer is always reset, so the stack contents are lost.

The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset. The

WDCON SFR is set to a 0x00 0000B on the reset. WTRF (WDCON.2) is set to a 1 on a Watchdog

timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by external reset.

EWRST (WDCON.1) is cleared by any reset. Software or any reset will clear WDIF (WDCON.3) bit.

- 48 -

Preliminary W79E4051/W79E2051 Data Sheet

Some of the bits in the WDCON SFR (WDRUN, WDCLR, EWRST, WDIF, WD0 and WD1) have

unrestricted read access which required Timed Access procedure to write. The remaining bits have

unrestricted write accesses. Please refer TA register description.

Figure 11-1: Internal reset and VDD monitor timing diagram

Publication Release Date: April 16, 2009

- 49 -

Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

V_BO3.8(BOR Enable)

VDD Power

0.7VDD

External RST Pin

0.3VDD

At least 4 clocks

System Normal Run

System Status

System within Power Down Mode

System not in Power Down Mode

System in reset

Crystal 65536 clocks

Internal RC 256 clocks

Crystal 65536 clocks

Internal RC 256 clocks

Figure 11-2: External reset timing diagram

- 50 -

Preliminary W79E4051/W79E2051 Data Sheet

12 INTERRUPTS

The W79E4051/2051 series have 9 interrupts source that are IE0, BOF, WDIF, TF0, CF, IE1, TF1,

TI+RI and PWMF. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and

enable bit. In addition, the interrupts can be globally enabled or disabled.

If an external interrupt is requested when the W79E4051/2051 series are put into Power Down or Idle

mode, the interrupt will cause the processor to wake up and resume operation.

12.1 Interrupt Sources

The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, programmable

through bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to

generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine

cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected

and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the

external interrupts are sampled every machine cycle, they have to be held high or low for at least one

complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the

level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is

serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the

interrupt continues to be held low even after the service routine is completed, then the processor may

acknowledge another interrupt request from the same source.

The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the

overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware

when the timer interrupt is serviced. The Watchdog timer can be used as a system monitor or a simple

timer. In either case, when the time-out count is reached, the Watchdog Timer interrupt flag WDIF

(WDCON.3) is set. If the interrupt is enabled by the enable bit EIE.4, then an interrupt will occur.

PWM interrupt is generated when its’ 10-bit down counter underflows. PWMF flag is set and PWM

interrupt is generated if enabled. PWMF is set by hardware and can only be cleared by software.

The comparator can generate interrupt after comparator output has occurs by CF flag. This bit is not

automatically cleared by the hardware, and the user will have to clear this bit using software.

The Serial block can generate interrupt on reception or transmission. There are two interrupt sources

from the Serial block, which are obtained by the RI and TI bits in the SCON SFR. These bits are not

automatically cleared by the hardware, and the user will have to clear these bits using software.

Brownout detect can cause brownout flag, BOF, to be asserted if power voltage drop below brownout

voltage level. Interrupt will occur if BOI (AUXR1.5), EBOV (EIE.6) and global interrupt enable are set.

All the bits that generate interrupts can be set or reset by software, and thereby software initiated

interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or

clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to

disable all interrupts.

Publication Release Date: April 16, 2009

- 51 -

Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled

interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will

execute an internally generated LCALL instruction which will vector the process to the appropriate

interrupt vector address. The conditions for generating the LCALL are;

1. An interrupt of equal or higher priority is not currently being serviced.

2. The current polling cycle is the last machine cycle of the instruction currently being execute.

3. The current instruction does not involve a write to IE, IP and IPH, registers and is not a RETI.

If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is

repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt

flag is active in one cycle but not responded to, and is not active when the above conditions are met,

the denied interrupt will not be serviced. This means that active interrupts are not remembered; every

polling cycle is new.

The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate

service routine. This may or may not clear the flag which caused the interrupt. In case of Timer

interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the

appropriate timer service routine. In case of external interrupt, INT0 and INT1, the flags are cleared

only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. The

hardware LCALL behaves exactly like the software LCALL instruction. This instruction saves the

Program Counter contents onto the Stack, but does not save the Program Status Word PSW. The PC

is reloaded with the vector address of that interrupt which caused the LCALL. These address of vector

for the different sources are as follows:

VECTOR LOCATIONS FOR INTERRUPT SOURCES

SOURCE

VECTOR ADDRESS SOURCE

VECTOR ADDRESS

000Bh

External Interrupt 0

External Interrupt 1

Serial Port

0003h

0013h

0023h

0033h

0043h

0053h

0063h

Timer 0 Overflow

Timer 1 Overflow

001Bh

Brownout Interrupt

002Bh

Analog Comparator

-

003Bh

-

004Bh

Watchdog Timer

-

005Bh

PWM Period Interrupt

006Bh

Table 12-1: Vector locations for interrupt sources

Execution continues from the vectored address till an RETI instruction is executed. On execution of

the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the

stack. The user must take care that the status of the stack is restored to what it was after the hardware

LCALL, if the execution is return to the interrupted program. The processor does not notice anything if

the stack contents are modified and will proceed with execution from the address put back into PC.

Note that a RET instruction would perform exactly the same process as a RETI instruction, but it

would not inform the Interrupt Controller that the interrupt service routine is completed, and would

leave the controller still thinking that the service routine is underway.

12.2 Priority Level Structure

- 52 -

Preliminary W79E4051/W79E2051 Data Sheet

The W79E4051/2051 series uses a four priority level interrupt structure (highest, high, low and lowest)

and supports up to 9 interrupt sources. The interrupt sources can be individually set to either high or

low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt.

However there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy

comes into play when the interrupt controller has to resolve simultaneous requests having the same

priority level. This hierarchy is defined as table below. This allows great flexibility in controlling and

handling many interrupt sources.

Priority Bits

Interrupt Priority Level

IPxH

IPx

0

1

Level 0 (lowest priority)

Level 1

1

0

Level 2

1

Level 3 (highest priority)

Table 12-2: Four-level interrupt priority

Each interrupt source can be individually programmed to one of four priority levels by setting or

clearing bits in the IPx and IPxH registers. An interrupt service routine in progress can be interrupted

by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest

priority interrupt service cannot be interrupted by any other interrupt source. So, if two requests of

different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are received simultaneously, an internal polling sequence

determines which request is serviced. This is called the arbitration ranking. Note that the arbitration

ranking is only used to resolve simultaneous requests of the same priority level.

As below Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,

arbitration ranking, and whether each interrupt may wake up the CPU from Power Down mode.

Source

Flag

Vector

Interrupt

Priority

Arbitration Power

Flag

cleared by

Down

address

Enable Bits

Ranking

Wakeup

Edge:

Hardware,

Software;

External

Interrupt 0

IE0

0003H

002BH

EX0 (IE0.0)

IP0H.0, IP0.0

1(highest)

Yes

Level:

Follow the

inverse of pin

Brownout

Detect

BOF

EBOV (EIE.6) IP1H.6, IP1.6 Software

2

3

4

Yes

Yes⁽¹⁾

No

Watchdog Timer WDIF 0053H

Timer 0

EWDI (EIE.4) IP1H.4, IP1.4 Software

Hardware,

TF0

000BH

ET0 (IE.1)

IP0H.1, IP0.1

Interrupt

Software

Edge:

External

Interrupt 1

Hardware,

Software;

IE1

0013H

EX1 (IE.2)

IP0H.2, IP0.2

5

Yes

Level:

Publication Release Date: April 16, 2009

Revision A06

- 53 -

Preliminary W79E4051/W79E2051 Data Sheet

Source

Flag

Vector

Interrupt

Priority

Arbitration Power

Flag

cleared by

Down

address

Enable Bits

Ranking

Wakeup

Follow the

inverse of pin

Timer 1

Interrupt

Hardware,

Software

TF1

001BH

ET1 (IE.3)

ES (IE.4)

EC (IE.6)

IP0H.3, IP0.3

6

No

Serial Port Tx

and Rx

TI & RI 0023H

CF 0033H

PWMF 006BH

IP0H.4, IP0.4 Software

IP0H.6, IP0.6 Software

7

No

Comparator

Interrupt

8

Yes⁽²⁾

No

PWM Period

Interrupt

EPWM (EIE.5) IP1H.5, IP1.5 Software

9(lowest)

Table 12-3: Vector location for Interrupt sources and power down wakeup

Note:

1. The Watchdog Timer can wake up Power Down Mode when its clock source is from internal RC.

2. The comparator can wake up Power Down Mode when bit ACSR.5(CIPE) is set to high.

12.3 Response Time

The response time for each interrupt source depends on several factors, such as the nature of the

interrupt and the instruction underway. In the case of external interrupts INT0 to RI+TI, they are

sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or

reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has

occurred. These flag values are polled only in the next machine cycle. If a request is active and all

three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes

four machine cycles to be completed. Thus there is a minimum time of five machine cycles between

the interrupt flag being set and the interrupt service routine being executed.

A longer response time should be anticipated if any of the three conditions are not met. If a higher or

equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the

service routine currently being executed. If the polling cycle is not the last machine cycle of the

instruction being executed, then an additional delay is introduced. The maximum response time (if no

other interrupt is in service) occurs if the W79E4051/2051 series are performing a write to IE, IP and

IPH and then executes a MUL or DIV instruction. From the time an interrupt source is activated, the

longest reaction time is 12 machine cycles. This includes 1 machine cycle to detect the interrupt, 2

machine cycles to complete the IE, IP or IPH access, 5 machine cycles to complete the MUL or DIV

instruction and 4 machine cycles to complete the hardware LCALL to the interrupt vector location.

Thus in a single-interrupt system the interrupt response time will always be more than 5 machine

cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycles is 48 clock

cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96

machine cycles. This is a 50% reduction in terms of clock periods.

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Preliminary W79E4051/W79E2051 Data Sheet

13 PROGRAMMABLE TIMERS/COUNTERS

The W79E4051/2051 series have two 16-bit programmable timer/counters and one programmable

Watchdog Timer. The Watchdog Timer is operationally quite different from the other two timers.

13.1 Timer/Counters 0 & 1

W79E4051/2051 has two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit registers

which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits register,

and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and TL1. The

two can be configured to operate either as timers, counting machine cycles or as counters counting

external inputs.

When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to

be thought of as 1/12 of the system clock or 1/6 of the system clock. In the "Counter" mode, the

register is incremented on the falling edge of the external input pin, T0 in case of Timer 0, and T1 for

Timer 1. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high

in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized

and the count register is incremented. Since it takes two machine cycles to recognize a negative

transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock

frequency. In either the "Timer" or "Counter" mode, the count register will be updated at C3.

Therefore, in the "Timer" mode, the recognized negative transition on pin T0 and T1 can cause the

count register value to be updated only in the machine cycle following the one in which the negative

edge was detected.

The "Timer" or "Counter" function is selected by the " C/T " bit in the TMOD Special Function Register.

Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for

Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each

Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done

by bits M0 and M1 in the TMOD SFR.

13.2 Time-Base Selection

W79E4051/2051 provides users with two modes of operation for the timer. The timers can be

programmed to operate like the standard 8051 family, counting at the rate of 1/12 of the clock speed.

This will ensure that timing loops on W79E4051/2051 and the standard 8051 can be matched. This is

the default mode of operation of the W79E4051/2051 timers. The user also has the option to count in

the 2-times mode, where the timers will increment at the rate of 1/6 clock speed. This will straight-

away increase the counting speed three times. This selection is done by the T0M and T1M bit in

CKCON SFR. A reset sets these bits to 0, and the timers then operate in the standard 8051 mode.

The user should set these bits to 1 if the timers are to operate in turbo mode.

13.2.1 Mode 0

In Mode 0, the timer/counter is a 13-bit counter. The 13-bit counter consists of THx (8 MSB) and the

five lower bits of TLx (5 LSB). The upper three bits of TLx are ignored. The timer/counter is enabled

when TRx is set and either GATE is 0 or INTx is 1. When C/T is 0, the timer/counter counts clock

cycles; when C/T is 1, it counts falling edges on T0 (Timer 0) or T1 (Timer 1). For clock cycles, the

time base may be 1/12 or 1/6 clock speed, and the falling edge of the clock increments the counter.

When the 13-bit value moves from 1FFFh to 0000h, the timer overflow flag TFx is set, and an interrupt

occurs if enabled. This is illustrated in next figure below.

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Preliminary W79E4051/W79E2051 Data Sheet

T0M=CKCON.3

(T1M=CKCON.4)

1/12

1/6

C/T=TMOD.2

(C/T=TMOD.6)

0

TL0

(TL1)

Fosc

1

0

4

7

1

T0=P3.4

TF0

(T1=P3.5)

(TF1)

TR0=TCON.4

TR1=TCON.6

Interrupt

TFx

GATE=TMOD.3

(GATE=TMOD.7)

TH0

(TH1)

/INT0=P3.2

(/INT1=P3.3)

Timer/Counter 0/1 Mode 0

Figure 13-1: Timer/Counters 0 & 1 in Mode 0

13.2.2 Mode 1

Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13-

bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer

moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if

enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in

Mode 0. The gate function operates similarly to that in Mode 0.

T0M=CKCON.3

(T1M=CKCON.4)

1/12

C/T=TMOD.2

(C/T=TMOD.6)

0

TL0

(TL1)

Fosc

1

0

4

7

1/6

1

T0=P3.4

TF0

(T1=P3.5)

(TF1)

TR0=TCON.4

TR1=TCON.6

Interrupt

TFx

GATE=TMOD.3

(GATE=TMOD.7)

TH0

(TH1)

/INT0=P3.2

(/INT1=P3.3)

Timer/Counter 0/1 Mode 1

Figure 13-2: Timer/Counters 0 & 1 in Mode 1

13.2.3 Mode 2

In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as an 8-bit count

register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx

bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues

from here. The reload operation leaves the contents of the THx register unchanged. Counting is

enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1

mode 2 allows counting of either clock cycles (clock/12 or clock/6) or pulses on pin Tn.

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Preliminary W79E4051/W79E2051 Data Sheet

T0M=CKCON.3

(T1M=CKCON.4)

1/12

1/6

0

C/T=TMOD.2

(C/T=TMOD.6)

0

TL0

(TL1)

Fcpu

TF0

1

(TF1)

0

7

Interrupt

TFx

1

T0=P3.4

(T1=P3.5)

TR0=TCON.4

TR1=TCON.6

GATE=TMOD.3

(GATE=TMOD.7)

TH0

/INT0=P3.2

(TH1)

(/INT1=P3.3)

Timer 0/1 Mode 2 (8-bit Auto-reload Mode)

Figure 13-3: Timer/Counter 0 & 1 in Mode 2

13.2.4 Mode 3

Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply

freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count

registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0

control bits C/T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12) or

1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle counter

(clock/12) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is used in cases

where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used in Modes 0, 1

and 2, but its flexibility is somewhat limited. While its basic functionality is maintained, it no longer has

control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer/counter

and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by switching it

out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port.

T0M=CKCON.3

(T1M=CKCON.4)

1/12

0

C/T=TMOD.2

Fcpu

0

1

TL0

1/6

0

7

Interrupt

TF0

TF1

1

T0=P3.4

TR0=TCON.4

GATE=TMOD.3

/INT0=P3.2

TH0

0

7

Interrupt

TR1=TCON.6

Timer 0/1 Mode 3 (Two 8-bit Counters)

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Revision A06

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Preliminary W79E4051/W79E2051 Data Sheet

Figure 13-4: Timer/Counter Mode 3

14 NVM MEMORY

The W79E4051/2051 series have NVM data memory of 128 bytes for customer’s data store used. The

NVM data memory has 8 pages area and each page has 16 bytes. The page addresses are shown on

Figure 14-1

The NVM memory can be read/write by customer program to access. Read NVM data is by MOVC

A,@A+DPTR instruction, and write data is by SFR of NVMADDRL, NVMDATA and NVMCON. Before

write data to NVM memory, the page must be erased by providing page address on NVMADDRL,

which high and low byte address of On-Chip Code Memory space will decode, then set EER of

NVMCON.7. This will automatically hold fetch program code and PC Counter, and execute page

erase. After finished, this bit will be cleared by hardware. The erase time is ~ 5ms.

For writing data to NVM memory, user must set address and data to NVMADDRL and NVMDATA,

then set EWR of NVMCON.6 to initiate NVM data write. The uC will hold program code and PC

Counter, and then write data to mapping address. Upon write completion, the EWR bit will be cleared

by hardware, the uC will continue execute next instruction. The program time is ~50us.

128 bytes NVM

16 bytes/page

FFFFh

FC7Fh

Page 7

Unused

FC70h

FC6Fh

Code Memory

Page 6

FC60h

FC5Fh

Page 5

FC50h

FC4Fh

FC7Fh

128 Bytes

NVM

Page 4

Page 3

Page 2

Page 1

Page 0

FC40h

FC3Fh

Data Memory

FC00h

FC30h

FC2Fh

FC20h

FC1Fh

Unused

Code Memory

FC10h

FC0Fh

FC00h

NVM Data Memory Area

0FFFh/07FFh

0000h

4K/2K Bytes

On-Chip

Code Memory

CONFIG1

CONFIG0

W79E4051/2051 On-chip Flash Memory Space

Figure 14-1: W79E4051/2051 Memory Map

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Preliminary W79E4051/W79E2051 Data Sheet

15 WATCHDOG TIMER

The Watchdog Timer is a free-running Timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the

system clock. The divider output is selectable and determines the time-out interval. When the time-out

occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if

it is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set.

The interrupt and reset functions are independent of each other and may be used separately or

together depending on the user’s software.

Time-Out

500KHz RC

26-bits Counter

(WDCON.3)

Selector

Oscillator

00

01

10

11

WDIF

/Enable

0

16

19

22

25

Interrupt

(Security Bit)

WDTE

17

20

23

EWDI

(EIE.4)

MUX

(WDCON.2)

uC clock

WTRF

WDRUN

(WDCON.7)

512 clock

delay

Reset

WDCLR

(Reset Watchdog)

(WDCON.0)

WD1,WD0

(WDCON.5/4)

EWRST

(WDCON.1)

Figure 15-1: Watchdog Timer

The Watchdog Timer should first be restarted by using WDCLR. This ensures that the timer starts

from a known state. The WDCLR bit is used to restart the Watchdog Timer. This bit is self clearing, i.e.

after writing a 1 to this bit the software will automatically clear it. The Watchdog Timer will now count

clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (WDCON.5 and

WDCON.4). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set.

After the time-out has occurred, the Watchdog Timer waits for an additional 512 WDT clock cycles. If

the Watchdog Reset EWRST (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no

WDCLR, a system reset due to Watchdog Timer will occur. This will last for two machine cycles, and

the Watchdog Timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the

Watchdog was the cause of the reset.

When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the

WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a

time-out and the WDCLR allows software to restart the timer. The Watchdog Timer can also be used

as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an

interrupt will occur if the global interrupt enable EA is set.

The main use of the Watchdog Timer is as a system monitor. This is important in real-time control

applications. In case of some power glitches or electro-magnetic interference, the processor may

begin to execute errant code. If this is left unchecked the entire system may crash. Using the

watchdog timer interrupt during software development will allow the user to select ideal watchdog

reset locations. The code is first written without the watchdog interrupt or reset. Then the Watchdog

interrupt is enabled to identify code locations where interrupt occurs. The user can now insert

instructions to reset the Watchdog Timer, which will allow the code to run without any Watchdog Timer

interrupts. Now the Watchdog Timer reset is enabled and the Watchdog interrupt may be disabled. If

any errant code is executed now, then the reset Watchdog Timer instructions will not be executed at

the required instants and Watchdog reset will occur.

The Watchdog Timer time-out selection will result in different time-out values depending on the clock

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Preliminary W79E4051/W79E2051 Data Sheet

speed. The reset, when enabled, will occur when 512 clocks after time-out has occurred.

WD1

WD0

Interrupt Reset

Number of

Clocks

Time

@ 10 MHz

time-out

2¹⁷+ 512

2²⁰+ 512

2²³+ 512

2²⁶+ 512

0

1

0

1

0

1

2¹⁷

2²⁰

2²³

2²⁶

131072

13.11 mS

1048576

8388608

67108864

104.86 mS

838.86 mS

6710.89 mS

Table 15-1: Time-out values for the Watchdog Timer

The Watchdog Timer will be disabled by a power-on/fail reset. The Watchdog Timer reset does not

disable the Watchdog Timer, but will restart it. In general, software should restart the timer to put it into

a known state. The control bits that support the Watchdog Timer are discussed below.

15.1 WATCHDOG CONTROL

WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the

Watchdog Timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the global

interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this

bit.

WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.

This bit is useful for determined the cause of a reset. Software must read it, and clear it manually. A

Power-fail reset will clear this bit. If EWRST = 0, then this bit will not be affected by the Watchdog

Timer.

EWRST: WDCON.1 - Enable Watchdog Timer Reset. This bit when set to 1 will enable the Watchdog

Timer reset function. Setting this bit to 0 will disable the Watchdog Timer reset function, but will leave

the timer running.

WDCLR: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog Timer and to

restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically

clear it. If the Watchdog Timer reset is enabled, then the WDCLR has to be set by the user within 512

clocks of the time-out. If this is not done then a Watchdog Timer reset will occur.

15.2 CLOCK CONTROL of Watchdog

WD1, WD0: WDCON.5, WDCON.4 - Watchdog Timer Mode select bits. These two bits select the

time-out interval for the watchdog timer. The reset time is 512 clocks longer than the interrupt time-out

value.

The default Watchdog time-out is 2¹⁷clocks, which is the shortest time-out period. The WDRUN, WD1,

WD0, EWRST, WDIF and WDCLR bits are protected by the Timed Access procedure. This prevents

software from accidentally enabling or disabling the watchdog timer. More importantly, it makes it

highly improbable that errant code can enable or disable the Watchdog Timer.

The security bit WDTCK is located at bit 7 of CONFIG register. This bit is used to configure the clock

source of watchdog timer from either the internal RC or the uC clock.

When WDTCK bit is cleared and 500KHz clock is used to run the watchdog timer, there is a chance

that the watchdog timer would hang as the counter does not increment. This problem arises when the

watchdog is set to run, (WDCON.7, WDRUN), the WDCLR bit (WDCON.0) is set to clear the

watchdog timer and the next instruction is to set the PCON register for CPU to go into idle or power-

down state. The reason this happens because the setting/clearing of WDCLR bit and the watchdog

counter are running on different clock domains, CPU clock and internal RC clock respectively. When

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Preliminary W79E4051/W79E2051 Data Sheet

WDCLR bit is set, to reset it, the counter must be non-zero. Since the counter is running off a much

slower clock, the counter may not have time to increment before the CPU clock halts as it entered the

idle/power-down mode. This results in the WDCLR bit is always set & the watchdog counter

remaining at zero. The solution to this problem is to monitor the WDCLR bit, ensuring that it’s cleared

before issue the instruction for the CPU to go into idle/power-down mode.

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Preliminary W79E4051/W79E2051 Data Sheet

16 SERIAL PORT (UART)

The UART in this device is a full duplex port. It provides the user with additional features such as the

Frame Error Detection and the Automatic Address Recognition. The serial port is capable of

synchronous as well as asynchronous communication. In Synchronous mode the device generates

the clock and operates in a half duplex mode. In the asynchronous mode, full duplex operation is

available. This means that it can simultaneously transmit and receive data. The transmit register and

the receive buffer are both addressed as SBUF Special Function Register. However any write to

SBUF will be to the transmit register, while a read from SBUF will be from the receiver buffer register.

The serial port can operate in four different modes as described below.

16.1 MODE 0

This mode provides synchronous communication with external devices. In this mode serial data is

transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is

provided by the device whether it is transmitting or receiving. This mode is therefore a half duplex

mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is

transmitted/received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. This Baud

Rate is determined by the SM2 bit (SCON.5). When this bit is set to 0, then the serial port runs at 1/12

of the clock. When set to 1, the serial port runs at 1/4 of the clock. This additional facility of

programmable baud rate in mode 0 is the only difference between the standard 8051 and

W79E4051/2051.

The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.

The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of this

device and the device at the other end of the line. Any instruction that causes a write to SBUF will start

the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all 8

bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling

edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high

again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on

TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures

that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift

clock on TxD or latched when the TxD clock is low.

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Preliminary W79E4051/W79E2051 Data Sheet

Transmit Shift Register

Internal

Data Bus

Write to

PARIN

SBUF

Fcpu

LOAD SOUT

CLOCK

RXD

1/12

1/4

TX START

TX CLOCK

TX SHIFT

TI

_SM20

1

Serial Interrupt

TXD

RI

RX CLOCK

SHIFT CLOCK

RI

REN

RX

START

LOAD SBUF

RX SHIFT

Read SBUF

Serial Controllor

CLOCK

SIN

Internal

Data Bus

SBUF

PAROUT

RXD

Figure 16-1: Serial Port Mode 0

The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive

data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch

data on the rising edge of shift clock. The external device should therefore present data on the falling

edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set

in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is

cleared by software.

16.2 MODE 1

In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of

10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB

first), and a stop bit (1). On received, the stop bit goes into RB8 in the SFR SCON. The baud rate in

this mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow.

Since the Timer 1 can be set to different reload values, a wide variation in baud rates is possible.

Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following

the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next

rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide-by-16 counter

and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is

transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will

be at the 10th rollover of the divide by 16 counter after a write to SBUF.

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,

with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD

line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the

divide–by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of

the divide-by-16 counter.

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Preliminary W79E4051/W79E2051 Data Sheet

The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a

best of three bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By

using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise

rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then

this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks

for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also

detected and shifted into the SBUF.

After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded

and RI is set. However certain conditions must be met before the loading and setting of RI can be

done.

1. RI must be 0 and

2. Either SM2 = 0, or the received stop bit = 1.

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.

Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to

looking for a 1-to-0 transition on the RxD pin.

Transmit Shift Register

Timer 1

Overflow

1

0

STOP

Internal

Data Bus

PARIN

Write to

SBUF

SOUT

TXD

START

LOAD

1/2

CLOCK

TX START

TX CLOCK

TX SHIFT

SMOD 0

1

1/16

Serial

Controllor

TI

Serial Interrupt

RX CLOCK

RI

LOAD SBUF

RX SHIFT

SAMPLE

1-To-0

DETECTOR

RX

START

Read SBUF

Internal

Data Bus

SBUF

RB8

CLOCK PAROUT

BIT

DETECTOR

RXD

SIN

D8

Receive Shift Register

Figure 16-2: Serial Port Mode 1

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Preliminary W79E4051/W79E2051 Data Sheet

16.3 MODE 2

This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional

description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first),

a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is

programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in

PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at

C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1

following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the

divide-by-16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are

transmitted, the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put

out on TxD pin. This will be at the 11th rollover of the divide-by-16 counter after a write to SBUF.

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,

with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD

line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the

divide- by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of

the divide-by-16 counter. The 16 states of the counter effectively divide the bit time into 16 slices. The

bit detection is done on a best of three bases. The bit detector samples the RxD pin, at the 8th, 9th

and 10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is

done to improve the noise rejection feature of the serial port.

Transmit Shift Register

1

STOP

D8

Clock/2

TB8

Internal

Data Bus

PARIN

TXD

Write to

SBUF

SOUT

0

START

LOAD

1/2

CLOCK

TX START

TX CLOCK

TX SHIFT

SMOD 0

1

1/16

Serial

Controllor

TI

Serial Interrupt

RX CLOCK

RI

LOAD SBUF

RX SHIFT

SAMPLE

1-To-0

DETECTOR

RX

START

Read SBUF

Internal

Data Bus

SBUF

RB8

CLOCK PAROUT

BIT

DETECTOR

RXD

SIN

D8

Receive Shift Register

Figure 16-3: Serial Port Mode 2

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Preliminary W79E4051/W79E2051 Data Sheet

If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,

and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.

If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF.

After shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded

and RI is set. However certain conditions must be met before the loading and setting of RI can be

done.

1. RI must be 0 and

2. Either SM2 = 0, or the received stop bit = 1.

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.

Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to

looking for a 1-to-0 transition on the RxD pin.

16.4 MODE 3

This mode is similar to Mode 2 in all aspects, except that the baud rate is programmable. The user

must first initialize the Serial related SFR SCON before any communication can take place. This

involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3

are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination

register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a

clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the

incoming start bit if REN = 1. The external device will start the communication by transmitting the start

bit.

Transmit Shift Register

1

STOP

D8

Timer 1

Overflow

TB8

Internal

Data Bus

PARIN

TXD

Write to

SBUF

SOUT

0

START

LOAD

1/2

CLOCK

TX START

TX CLOCK

TX SHIFT

SMOD 0

1

1/16

Serial

Controllor

TI

Serial Interrupt

RX CLOCK

RI

LOAD SBUF

RX SHIFT

SAMPLE

1-To-0

DETECTOR

RX

START

Read SBUF

Internal

Data Bus

SBUF

RB8

CLOCK PAROUT

BIT

DETECTOR

RXD

SIN

D8

Receive Shift Register

Figure 16-4: Serial Port Mode 3

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Preliminary W79E4051/W79E2051 Data Sheet

SM0

SM1

MODE

TYPE

BAUD CLOCK

FRAME

SIZE

START

BIT

STOP

BIT

9TH BIT

FUNCTION

0

1

0

1

0

1

0

1

2

3

SYNCH.

4 OR 12 TCLKS

TIMER 1

8 BITS

NO

NONE

0, 1

ASYNCH.

10 BITS

1 BIT

ASYNCH. 32 OR 64 TCLKS 11 BITS

ASYNCH. TIMER 1 11 BITS

0, 1

Table 16-1: Serial Port Mode Summary Table

16.5 Framing Error Detection

A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data

communication. Typically the frame error is due to noise and contention on the serial communication

line. The W79E4051/2051 series have the facility to detect such framing errors and set a flag which

can be checked by software.

The Frame Error FE bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051

family. However, in the W79E4051/2051 series it serves a dual function and is called SM0/FE. There

are actually two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as

SCON.7 is determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is

indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE.

The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while

reading or writing to FE. If FE is set, then any following frames received without any error will not clear

the FE flag. The clearing has to be done by software.

16.6 Multiprocessor Communications

Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the

W79E4051/2051 series, the RI flag is set only if the received byte corresponds to the Given or

Broadcast address. This hardware feature eliminates the software overhead required in checking

every received address, and greatly simplifies the software programmer task.

In the multiprocessor communication mode, the address bytes are distinguished from the data bytes

by transmitting the address with the 9th bit set high. When the master processor wants to transmit a

block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the

slave processors should have their SM2 bit set high when waiting for an address byte. This ensures

that they will be interrupted only by the reception of an address byte. The Automatic address

recognition feature ensures that only the addressed slave will be interrupted. The address comparison

is done in hardware not software.

The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0,

the slave will be interrupted on the reception of every single complete frame of data. The unaddressed

slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th bit is the stop

bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is received and

the received byte matches the Given or Broadcast address.

The Master processor can selectively communicate with groups of slaves by using the Given Address.

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Preliminary W79E4051/W79E2051 Data Sheet

All the slaves can be addressed together using the Broadcast Address. The addresses for each slave

are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the

SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in

SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in

SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives

the user flexibility to address multiple slaves without changing the slave address in SADDR.

The following example shows how the user can define the Given Address to address different slaves.

Slave 1:

SADDR1010 0100

SADEN 1111 1010

Given 1010 0x0x

Slave 2:

SADDR1010 0111

SADEN 1111 1001

Given 1010 0xx1

The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it

is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010

0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate

only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master

wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit

1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select

both slaves (1010 0001 and 1010 0101).

The master can communicate with all the slaves simultaneously with the Broadcast Address. This

address is formed from the logical OR of the SADDR and SADEN SFRs. The zeros in the result are

defined as don't cares. In most cases the Broadcast Address is FFh. In the previous case, the

Broadcast Address is (1111111x) for slave 1 and (11111111) for slave 2.

The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two

SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as xxxx

xxxx (i.e. all bits don't care). This effectively removes the multiprocessor communications feature,

since any selectivity is disabled.

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Preliminary W79E4051/W79E2051 Data Sheet

17 PULSE WIDTH MODULATED OUTPUTS (PWM)

The W79E4051/2051 contains one Pulse Width Modulated (PWM) channel which generate pulses of

programmable length and interval. The output for PWM0 is on P3.5. After chip reset the internal output

of the PWM channel is high. In this case before the pin will reflect the state of the internal PWM

output, a “1” must be written to the port bit that serves as a PWM output. A block diagram is shown in

Figure 17-1. The interval between successive outputs is controlled by a 10–bit down counter which

uses the internal microcontroller clock as its input. The PWM counter clock has the frequency as

F_CPWM= P_OSC/Prescaler. The two pre-scaler selectable bits FP[1:0] are located at PWMCON3[1:0].

When the counter reaches underflow it is reloaded with a user selectable value. This mechanism

allows the user to set the PWM frequency at any integer sub–multiple of the microcontroller clock

frequency. The repetition frequency of the PWM is given by: f_PWM= F_CPWM/ (PWMP+1) where PWMP

is contained in PWMPH and PWMPL SFR.

A compare value greater than the counter reloaded value is in the PWM output being permanently

low. In addition there are two special cases. A compare value of all zeroes, 000H, causes the output to

remain permanently high. A compare value of all ones, 3FFH, results in the PWM output remaining

permanently low. Again the compare value is loaded into a Compare register. The transfer from this

holding register to the actual Compare register is under program control.

The PWMP register fact that writes are not into the Counter register that controls the counter; rather

they are into a holding register. As described below the transfer of data from this holding register, into

the register which contains the actual reload value, is controlled by the user’s program.

The width of PWM output pulse is determined by the value in the appropriate Compare registers,

PWM0L and PWM0H. When the counter described above reaches underflow the PWM output is

forced high. It remains high until the compare value is reached at which point it goes low and keeps

low until the next underflow. The number of microcontroller clock pulses that the PWM0 output is high

is given by:

t_HI= (PWMP – PWM0+1)

Note :

1. A compare value of all zeroes, 000H, causes the PWM output to remain permanently high. A

compare value of all ones, 3FFH, results in the PWM output remain permanently low. A compare

value greater than the counter reloaded value will result in the PWM output being permanently

low.

2. When the PWMRUN is cleared, the PWM outputs take on the state prior to the bit being cleared.

In general, this state is not known. In order to place the PWM output in a known state when

PWMRUN is cleared;

.

Program Compare Registers to either the “always 1” or “always 0” (see note 1).

Set Load (and PWMRUN) bits to 1.

Wait for PWMF underflow flag or Load bit (=0).

Clear PWMRUN.

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Revision A06

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Preliminary W79E4051/W79E2051 Data Sheet

VDD

PWMP Register

SET

CLR

D

Q

PWM Period Interrupt

PWMF

load

PWMRUN

Fosc

Counter Register

10-bit Down Counter

S/W Clear

Posc

VDD

Fcpwm

Underflow

Prescaler

(1/1, 1/2, 1/4, 1/16)

PWM0I

X

Y

0

1

+

Clear

Counter

PWM0

(P3.5)

+

(FP1, FP0)

>

CLRPWM

-

PWM0OE

P3.5

Compare Register

PWM0 register

Figure 17-1: PWM block diagram

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Preliminary W79E4051/W79E2051 Data Sheet

18 ANALOG COMPARATORS

The W79E4051/2051 is provided an Analog Comparator shown in Figure 18-1. The comparator output

is wired to SFR bit P3.6. When the positive input of AIN0(P1.0) is greater than the negative input of

AIN1(P1.1), the comparator output is high. Otherwise the output is low.

The comparator may be configured to cause an interrupt under a variety of output value conditions by

setting bits CM[2:0] in ACSR(97H) register and bits CPCK[2:0] in ACCK(96H) register. The CF flag is

set whenever the comparator output is matched the setting condition by CM[2:0].

Setting bit CIPE(Comparator Idle Power-down Enable) in ACSR.5 to high makes the analog

comparator is active in power-down and idle mode, therefore the comparator interrupt can wake up

CPU from power down and idle mode.

Analog Comparator Circuit

Register bit

P3.6

(P1.0) AIN0

+

Debouncing

Control

CF

Interrupt

-

(P1.1) AIN1

Enable Comparator

CEN

CM[2:0]

CPCK[2:0]

Figure 18-1: Analog Comparator

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Preliminary W79E4051/W79E2051 Data Sheet

18.1 Comparator Interrupt with Debouncing

The comparator output is sampled at every State 4 (S4) of every machine cycle. The conditions on the

analog inputs maybe cause the comparator output toggle excessively, especially applying slow

moving analog inputs. Table 18-2: Comparator Interrupt Mode shows the 8 comparator interrupt

modes set by CM[2:0] in ACSR(97H). A built-in configurable debouncing timer provides 8 debouncing

timing controlled by CPCK[2:0] for widely applications. The debouncing timing is shown in Table 18-1.

If CPU is in normal/Idle mode F_DBis from Fosc; if CPU is in power-down mode F_DBis from internal RC

22M/11M Hz oscillator.

CPCK2 CPCK 1 CPCK 0 Debouncing Time

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(3/F_DB)*2~(4/F_DB)*2

(3/F_DB)*4~(4/F_DB)*4

(3/F_DB)*8~(4/F_DB)*8

(3/F_DB)*16~(4/F_DB)*16

(3/F_DB)*32~(4/F_DB)*32

(3/F_DB)*64~(4/F_DB)*64

(3/F_DB)*128~(4/F_DB)*128

(3/F_DB)*256~(4/F_DB)*256

Table 18-1: Comparator Debouncing Time

CM2

CM1

CM0 Comparator interrupt mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Negative (Low) level

Positive edge

Toggle with debounce

Positive edge with debounce

Negative edge

Toggle

Negative edge with debounce

Positive (High) level

Table 18-2: Comparator Interrupt Mode

Three debouncing modes are provided to filter out this noise. In debouncing mode when the

comparator output matches one of three debouncing mode condition, the debouncing timer resets and

starts up-counting. The end of debouncing triggers the hardware to check if the comparator output

matches the mode condition or not. If it is compliant with the mode condition the comparator flag CF is

set by hardware, otherwise CF keeps low. Refer to Figure 18-2.

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Preliminary W79E4051/W79E2051 Data Sheet

Comparator Output

Debouncing Timer

CF

Start

debouncing

End of

debouncing

Condition

matches

Figure 18-2: Example of Negative Edge Comparator Interrupt with Debouncing

18.2 Application circuit

It is recommended to add a decoupled capacitor as close as port pin for reducing the variation of

offset voltage as show in Figure 18-3.

(P1.0) AIN0

+

C

-

(P1.1) AIN1

C

Figure 18-3: Application Circuit of Comparator

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Revision A06

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Preliminary W79E4051/W79E2051 Data Sheet

19 TIME ACCESS PROCTECTION

The W79E4051/2051 series have a new feature, like the Watchdog Timer which is a crucial to proper

operation of the system. If left unprotected, errant code may write to the Watchdog control bits

resulting in incorrect operation and loss of control. In order to prevent this, the W79E4051/2051 series

have a protection scheme which controls the write access to critical bits. This protection scheme is

done using a timed access.

In this method, the bits which are to be protected have a timed write enable window. A write is

successful only if this window is active, otherwise the write will be discarded. This write enable window

is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window

automatically closes. The window is opened by writing AAh and immediately 55h to the Timed Access

(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed access

window is

TA

REG

MOV

0C7h

;Define new register TA, @0C7h

TA, #0AAh

TA, #055h

When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine

cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the

first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,

during which the user may write to the protected bits. Once the window closes the procedure must be

repeated to access the other protected bits.

Examples of Timed Assessing are shown below.

Example 1: Valid access

MOV

TA, #0AAh

;3 M/C Note: M/C = Machine Cycles

MOV

TA, #055h

;3 M/C

MOV

WDCON, #00h

Example 2: Valid access

MOV

TA, #0AAh

TA, #055h

;3 M/C

;1 M/C

;2 M/C

MOV

NOP

SETB

EWRST

Example 3: Valid access

MOV

ORL

TA, #0AAh

;3 M/C

;3M/C

TA, #055h

WDCON, #00000010B

Example 4: Invalid access

MOV

NOP

CLR

TA, #0AAh

;3 M/C

;1 M/C

;2 M/C

TA, #055h

EWT

Example 5: Invalid Access

MOV TA, #0AAh

;3 M/C

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Preliminary W79E4051/W79E2051 Data Sheet

NOP

MOV

SETB

;1 M/C

TA, #055h

EWT

;3 M/C

;2 M/C

In the first three examples, the writing to the protected bits is done before the 3 machine cycles

window closes. In Example 4, however, the writing to the protected bit occurs after the window has

closed, and so there is effectively no change in the status of the protected bit. In Example 5, the

second write to TA occurs 4 machine cycles after the first write, therefore the timed access window is

not opened at all, and the write to the protected bit fails.

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Preliminary W79E4051/W79E2051 Data Sheet

20 I/O PORT MODE SETTING

W79E4051/2051 has maximum one 8-bit(P1), one 7-bit(P3) and one 2-bit(P2) ports. Except P1.0 and

P1.1, all pins are quasi-bidrectional mode, which are common with standard 80C51, that the internal

weakly pull-ups are present as the port registers are set to logic one. P1.0 and P1.1, the alternate

function are analog comparator inputs, stays in PMOS-off open-drain mode after CPU reset. The P2.0

(XTAL2) can be configured as clock output by setting bit ENCLK to high when CPU clock source is

from on-chip RC or external Oscillator, and the frequency of clock output is divided by 4 on on-chip RC

clock or external Oscillator.

20.1 Quasi-Bidirectional Output Configuration

After chip was power on or reset, the all ports except P1.0 and P1.1 output are in this mode, and

output is common with the MCS-51. This mode can be used as both an input and output without the

need to reconfigure the port. P1.0~P1.1 stays in PMOS-off open-drain mode after CPU reset.

P1M1.Y

PORT INPUT/OUTPUT MODE

Open Drain

0

1

Quasi-bidirectional

Table 20-1: I/O port Configuration Table

When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features

are similar to an open drain output except that there are three pull-up transistors in the quasi-

bidirectional output that serve different purposes.

This mode has three pull-up resisters that are “strong” pull-up, “weak” pull-up and “very weak” pull-up.

The “strong” pull-up is used fast transition from logic “0” change to logic “1”, and it is fast latch and

transition. When port pins is occur from logic “0” to logic “1”, the strong pull-up will quickly turn on two

CPU clocks to pull high then turn off.

The “weak” pull-up is turned on when the input port pin is logic “1” level or itself is logic “1”, and it

provides the most source current for a quasi-bidirectional pin that output is “1” or port latch is logic “0”’.

The “very weak” pull-up is turned on when the port latch is logic “1”. If port latch is logic “0”, it will be

turned off. The very weak pull-up is support a very small current that will pull the pin high if it is left

floating. And the quasi-bidirectional port configuration is shown as below figure.

If port pin is low, it can drives large sink current up to about 20mA/10mA at V_DD=5V/2.7V.

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Preliminary W79E4051/W79E2051 Data Sheet

VDD

2 CPU

Clock Delay

Very

Weak

P

N

P

Strong

Weak

Port Pin

Port Latch

Data

Input Data

Figure 20-1: Quasi-Bidirectional Output

20.2 Open Drain Output Configuration

P1.0 and P1.1 are in open drain type after chip reset. To configure this mode is turned off all pull-ups.

If used similar as a logic output, the port must has an external pull-up resister. The open drain port

configuration is shown as below.

Port Pin

Port Latch

Data

N

Input Data

Figure 20-2: Open Drain Output

Publication Release Date: April 16, 2009

Revision A06

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Preliminary W79E4051/W79E2051 Data Sheet

21 OSCILLATOR

The W79E4051/2051 series provides three oscillator input option. These are configured at CONFIG

register (CONFIG0) that include On-Chip RC Oscillator Option, External Clock Input Option and

Crystal Oscillator Input Option. The Crystal Oscillator Input frequency may be supported from 4MHz to

24MHz, and without capacitor or resister.

Crystal Oscillator

Internal RC Oscillator

External Clock input

00H

01H

11H

16 bits Ripple

Counter

F

CPU

CPU Clock

FOSC1 FOSC0

Peripheral

Clock

Power Monitor Reset

Power Down

Figure 21-1: Oscillator

21.1 On-Chip RC Oscillator Option

The On-Chip RC Oscillator of W79E4051R and W79E2051R is trimmed by factory and is configurable

to 11.0592MHz/22.1184MHz ± 2% (through Configuration-bit FS1 bit) frequency to support clock

source. When FOSC1, FOSC0 = 01H, the On-Chip RC Oscillator is enabled. A clock output on P2.0

(XTAL2) may be enabled when On-Chip RC oscillator is used.

Note:

For the untrimmed parts of W79E2051 and W79E4051, the untrimmed frequency of internal RC

oscillator may have ± 25% deviation compared to the nominal frequency in 22.1184Mhz. It maybe has

an potential risk that CPU runs over specified speed if the untrimmed frequency is over 24MHz.

21.2 External Clock Input Option

The clock source pin (XTAL1) is from External Clock Input by FOSC1, FOSC0 = 11H, and frequency

range is form 4MHz up to 24MHz. A clock output on P2.0 (XTAL2) may be enabled when External

Clock Input is used.

The W79E4051/2051 series supports a clock output function when either the on-chip RC oscillator or

the external clock input options is selected. This allows external devices to synchronize to the

W79E4051/2051 serial. When enabled, via the ENCLK bit in the ACCK.7, the clock output appears on

the XTAL2/CLKOUT pin whenever the on-chip oscillator is running, including in Idle Mode. The

frequency of the clock output is 1/4 of the CPU clock rate. If the clock output is not needed in Idle

Mode, it may be turned off prior to entering Idle mode for saving additional power. The clock output

may also be enabled when the external clock input option is selected.

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Preliminary W79E4051/W79E2051 Data Sheet

22 POWER MONITORING FUNCTION

In order to prevent incorrect operation during power up and power drop, the W79E4051/2051 is

provided a power monitor function, Brownout Detect.

22.1 Brownout Detect and Reset

The W79E4051/2051 has an on-chip Brown-out Detection circuit for monitoring the VDD level during

operation by comparing it to a programmable brownout trigger level. There are 4 brownout trigger

levels available for wider voltage applications. The 4 nominal levels are 2.4V, 2.7V, 3.8V and 4.5V

(programmable through BOV.1-0 bits). When V_DDdrops to the selected brownout trigger level (V_BOR),

the brownout detection logics will either reset the CPU until the V_DDvoltage raises above V_BORor

requests a brownout interrupt at the moment that V_DDfalls and raises through V_BOR. The brownout

detection circuits also provides a low power brownout detection mode for power saving. When

LPBOV=1, the brownout detection repeatedly senses the voltage for 64/f_BRCthen turn off detector for

960/ f_BRCif V_DDvoltage still below brownout trigger level. f_BRC, the frequency of built-in RC oscillator, is

approximately 100K* V_DDHZ ±50%. The relative control bits are located in SFR AUXR1 @A2h. The

Brownout Detect block is shown in Figure 22-1.

BOS

BOV[1:0]

To Reset

0

1

Brownout

Detect

Circuit

BOD

LPBOV

BOI

BOF

To Brownout interrupt

Figure 22-1: Brown-out Detect Block

Publication Release Date: April 16, 2009

Revision A06

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Preliminary W79E4051/W79E2051 Data Sheet

V

DD

VBOR+

VBOR -

Nominal Brown-

out Voltage

Brown-out Status

BOS

T

BOR

8ms

BOI=0 to select

Brown-out Reset

Reset

Clear by Software

BOI=1 to select

Brown-out Interrupt

BOF

Set by Hardware

Hysterisis voltage is about 30mV~150mV for each BOD voltage level

TBOR :Brown-out Reset Delay Time with about 8mS

Figure 22-2: Brown-out Voltage Detection

Hysterisis range of brownout detect voltage is about 30mV to 150mV

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Preliminary W79E4051/W79E2051 Data Sheet

23 ICP (IN-CIRCUIT PROGRAM) FLASH MODE

The ICP(In-Circuit-Program) mode is another approach to access the Flash EPROM. There are only 3

pins needed to perform the ICP function. One is mode input, shared with RST pin, which must be kept

in Vdd voltage in the entire ICP working period. One is clock input, shared with P1.7, which accepts

serial clock from external device. Another is data I/O pin, shared with P1.6, that an external ICP

program tool shifts in/out data via P1.6 synchronized with clock(P1.7) to access the Flash EPROM of

W79E4051/2051. User may refer to http://www.manley.com.cn/english/index.asp for ICP Program

Tool.

Vcc

ICP Power

Switch

ICP Connector

VDD

Jumper^[1]

[2]

V

DD

PP

RST(Pin1)

P1.6

To application

ICP

Writer Tool

Data

Clock

Vss

P1.7

Vss

W79E2051

W79E4051

System Board

Note:

1. Circuitry separation is optionally needed between ICP and application during ICP operation.

2. Resistor is optional by application

Figure 23-1: ICP Writer Tool connector pin assign

Note: 1. When using ICP to upgrade code, the RST, P1.6 and P1.7 must be taken within design system board.

2. After program finished by ICP, to suggest system power must power off and remove ICP connector then power

on.

3. It is recommended that user performs erase function and programming configure bits continuously

without any interruption.

Publication Release Date: April 16, 2009

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Preliminary W79E4051/W79E2051 Data Sheet

24 CONFIG BITS

The W79E4051/2051 has two CONFIG bits (CONFIG0 located at FB00h, CONFIG1 located at FB01h)

that must be defined at power up and can not be set by the program after start of execution. Those

features are configured through the use of two flash EPROM bytes, and the flash EPROM can be

programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the

code can be protected. The protection of flash EPROM (CONFIG1) and those operations on it are

described below.

24.1 CONFIG0

Config0

WDTCK

CBOV1

CBOV0

0

-

BPFR

Fosc1

Fosc0

Figure 24-1: Config0 register bits

Bit

7

Name Function

WDTCK Clock source of Watchdog Timer select bit:

0: The internal 500KHz RC oscillator clock is for Watchdog Timer clock used.

1: The uC clock is for Watchdog Timer clock used.

Brownout voltage selection bits:

6~5 CBOV1

CBOV0

SFR bits (BOV1,BOV0) are initialized at reset with the inversed value of config0-bits

(CBOV1,CBOV0)

CBOV.1 CBOV.0 Brownout Voltage

1

0

1

0

1

0

Brownout voltage is 2.4V

Brownout voltage is 2.7V

Brownout voltage is 3.8V

Brownout voltage is 4.5V

2

BPFR Bypass Clock Filter.

0: Disable Clock Filter.

1: Enable Clock Filter.

1

0

Fosc1 CPU Oscillator Type Select bit 1.

Fosc0 CPU Oscillator Type Select bit 0.

Oscillator Configuration bits:

Fosc1

Fosc0

OSC source

0

1

4MHz ~ 24MHz crystal

Internal RC Oscillator (FS1 bit in CONFIG1.5 will determine

either 11MHz or 22MHZ)

XT1 and XT2 function as P2.1 and P2.0

1

0

1

Reserved

External Oscillator in XTAL1; XT2 is in Tri-state

- 82 -

Preliminary W79E4051/W79E2051 Data Sheet

24.2 CONFIG1

Config1

-

C7

C6

FS1

-

Figure 24-2: Config1 register bits

Bit

7

Name Function

C7

4K/2K Program Flash EPROM Lock bit

This bit is used to protect the customer’s program code. It may be set after the programmer

finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash

EPROM data and CONFIG Registers can not be accessed again.

6

5

C6

128 byte Data Flash EPROM Lock bit

This bit is used to protect the customer’s 128 bytes of data code. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0,

both the 128 bytes of Flash EPROM data and CONFIG Registers can not be accessed again.

FS1

Internal Oscillator 11MHz/22MHz selection bit

This bit is used to select 11MHz or 22MHz internal oscillator.

1: Internal oscillator is set to 22MHz

0: Internal oscillator is set to 11MHz

0~4

-

Reserved.

Lock bits C7 and C6:

Bit 7 Bit 6 Function Description

1

Both security of 4K/2KB program code and 128 Bytes data area are not locked. They

can be erased, programmed or read by Writer or ICP.

0

1

The 4K/2KB program code area is locked. It can not be read and written by Writer or

ICP. The 128 Bytes data area can be program one time or read.

1

0

Not supported.

Both security of 4K/2KB program code and 128 Bytes data area are locked. They can

not be read and written by Writer or ICP.

Publication Release Date: April 16, 2009

- 83 -

Revision A06

Preliminary W79E4051/W79E2051 Data Sheet

25 ELECTRICAL CHARACTERISTICS

25.1 Absolute Maximum Ratings

SYMBOL

DC Power Supply

Input Voltage

PARAMETER

CONDITION

MINIMUM

-0.3

MAXIMUM

+7.0

UNIT

V

V_DD

V_IN

V_DD−V_SS

V_SS-0.3

-40

V_DD+0.3

+85

V

Operating Temperature

Storage Temperature

Sink current

TA

°C

mA

V

Tst

-55

+150

95

ISK

V_RAM

-

RAM Keep Alive

Voltage

1.4

+7.0

Maximum Current into

V_DD

-

120

25

mA

Maximum Current out of

V_SS

Maximum Current suck

by a I/O pin

Maximum Current

sourced by a I/O pin

25

Maximum Current suck

by total I/O pins

80

Maximum Current

80

sourced by total I/O pins

Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability

- 84 -

Preliminary W79E4051/W79E2051 Data Sheet

25.2 DC ELECTRICAL CHARACTERISTICS

(VSS = 0V, TA =-40~85° C, unless otherwise specified; Typical value is test at TA=25° C)

SPECIFICATION

PARAMETER

Operating Voltage

SYM.

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DD

2.4

5.5

V

V_DD=2.4V ~ 5.5V @ 12MHz

V_DD=4.5V ~ 5.5V @ 24MHz

3.0

5.5

3.5

Program and erase Data Flash.

Operating Current

I_DD1

I_DD2

2

8

mA

No load, RST = V_DD, V_DD= 3.0V

@ 12MHz

12

No load, RST = V_DD, V_DD= 5.0V

@ 24MHz

Idle Current

I_IDLE1

I_IDLE2

1.6

6.5

0.5

2.5

7.5

10

mA

µA

No load, V_DD= 3.0V @ 12MHz

No load, V_DD= 5.0V @ 24MHz

Power Down Current

I_PWDN1

No load, V_DD= 5.0/3.0V

(Brownout detection is disabled)

INPUT / OUTPUT

Input Current P1, P2, P3

Input Current RST pin^[1]

I_IN1

I_IN2

-50

-55

-

+10

-30

V_DD= 5.5V, V_IN= 0V or V_IN=V_DD

V_DD= 5.5V, V_IN= 0.45V

µA

Input Leakage Current P1.0,

P1.1(Open Drain)

I_LK

-1

-

+1

V_DD= 5.5V, 0<V_IN<V_DD

µA

Logic 1 to 0 Transition Current

P1, P2, P3

-450

-93

0

-

-200

-56

1.0

V_DD= 5.5V, V_IN<2.0V

V_DD=2.4 Vin = 1.3v

[*3]

I_TL

Input Low Voltage P1, P2, P3

(TTL input)

V_DD= 4.5V

V_IL1

V_IH1

V_IL3

V

0

0.6

V_DD= 2.4V

V_DD= 5.5V

V_DD= 2.4V

Input High Voltage P1, P2, P3

(TTL input)

2.0

1.5

0

V

_DD+0.2

V_DD+0.2

0.8

Input Low Voltage XTAL1^[*2]

V_DD= 4.5V

0

0.4

V_DD= 3.0V

V_DD= 5.5V

V_DD= 3.0V

Input High Voltage XTAL1^[*2]

3.5

2.4

V_DD+0.2

V_IH3

V_ILS

V_IHS

V_HY

V

V_DD+0.2

Negative going threshold

(RST Schmitt input)

-0.5

-

0.3V_DD

Positive going threshold

(RST Schmitt input)

0.7V_DD

-

V_DD+0.5

Hysteresis voltage

(RST Schmitt input)

0.2V_DD

Source Current P1, P2, P3

(Quasi-bidirectional Mode)

-150

-18

-210

-27

-360

-40

V_DD= 4.5V, V_S= 2.4V

V_DD= 2.4V, V_S= 2.0V

µA

I_SR1

Publication Release Date: April 16, 2009

Revision A06

- 85 -

Preliminary W79E4051/W79E2051 Data Sheet

Sink Current P1, P2, P3

13

8

20

13

24

17

mA

V_DD= 4.5V, V_S= 0.45V

V_DD= 2.4V, V_S= 0.45V

I_SK1

(Quasi-bidirectional Mode)

Brownout voltage with

BOV[1:0]=00

V_BO2.4

V_BO2.7

V_BO3.8

V_BO4.5

2.25

2.55

3.65

4.30

2.4

2.7

3.8

4.5

2.55

2.75

3.90

4.65

V

Brownout voltage with

BOV[1:0]=01

Brownout voltage with

BOV[1:0]=10

Brownout voltage with

BOV[1:0]=11

Brownout detection current

No load, V_DD= 5.0/3.0V

I_BO1

160/135

210/170

µA

Average current at Brownout

detection active (LPBOV=0)

No load, V_DD= 5.0/3.0V

Average current at Brownout

detection active (LPBOV=1, 1/16

mode)

I_BO2

24/11

-

32/15

150

µA

Hysterisis range of BOD voltage

Power On Reset Voltage

V

_DD= 2.4V~5.5V,

(LPBOD,BOI) = (0,x) or (1,0)

_DD= 2.4V~5.5V,

35

mV

V_Bh

V

10

-

60

mV

V

(LPBOD,BOI)=(1,1)

1.45

2.0

2.10

With Hysterisis ~= 450mV

V_POR

Notes: *1. RST pin is a Schmitt trigger input.

*2. XTAL1 is a CMOS input.

*3. Pins of P1, P2 and P3 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin

approximates to 2V.

- 86 -

Preliminary W79E4051/W79E2051 Data Sheet

25.3 The COMPARATOR ELECTRICAL CHARACTERISTICS

(VDD−VSS = 3.0~5V±10%, TA = -40~85°C, Fosc = 24MHz, unless otherwise specified.)

PARAMETER

SYMBOL

SPECIFICATION

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Common mode range comparator

inputs

V_CR

0

V_DD-0.3

V

Common mode rejection ratio

Response time

CMRR

t_RS

-50

100

5

dB

ns

us

-

50

1

Comparator enable to output valid

time

t_EN

Input leakage current, comparator

Comparator offset voltage

I_IL

-10

0

10

20

uA

0< V_IN<V_DD

V_OFF

mV

With decoupled

capacitors on inputs

Publication Release Date: April 16, 2009

Revision A06

- 87 -

Preliminary W79E4051/W79E2051 Data Sheet

25.4 AC ELECTRICAL CHARACTERISTICS

t_CLCL

t_CLCH

t_CLCX

t_CHCL

t_CHCX

Note: Duty cycle is 50%.

25.5 EXTERNAL CLOCK CHARACTERISTICS

PARAMETER

SYMBOL

VARIABLE CLOCK

UNITS

MHz

MIN.

MAX.

Oscillator Frequency

1/t_CLCL

0

24

PARAMETER

SYMBOL

t_CHCX

MIN.

18.8

-

TYP.

MAX.

UNITS

nS

NOTES

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

-

t_CLCX

-

nS

t_CLCH

10

nS

t_CHCL

-

nS

- 88 -

Preliminary W79E4051/W79E2051 Data Sheet

25.6 RC OSC AND AC CHARACTERISTICS

(VDD−VSS = 2.4~5V, TA = -40~85°C.)

Parameter

Specification (reference)

Test Conditions

Min.

-25

Typ.

Max.

25

Unit

%

V_DD=2.4V~5.5V, TA = -40°C ~85°C

W79E2051/W79E4051

Frequency accuracy of On-

chip RC oscillator

(Without calibration)

V_DD=5.0V, TA = 25°C

W79E2051R/W79E4051R

On-chip RC oscillator with

calibration^1,2

-2

-5

-7

-9

2

5

7

%

V_DD=2.7V~5.5V, TA = 0~85°C

V_DD=2.7V~5.5V, TA = -20~85°C

V_DD=2.7V~5.5V, TA = -40~85°C

(Fosc = 22.1184MHz with

factory calibration)

%

Wakeup time

Note:

256

clk

1. These values are for design guidance only and are not tested.

2. RC frequency deviation vs. V_DDand Temperature is shown below

6

3

T=85C

T=50C

T=25C

T=0C

0

-3

-6

-9

-12

T=-20C

T=-40C

2.2

2.7

3.2

3.7

4.2

4.7

5.2

Supply Voltage (V)

Publication Release Date: April 16, 2009

Revision A06

- 89 -

Preliminary W79E4051/W79E2051 Data Sheet

26 TYPICAL APPLICATION CIRCUITS

C1

XTAL1

XTAL2

R

C2

W79E4051/

2051

The table below shows the reference values for crystal applications.

CRYSTAL

C1

C2

R

4MHz ~ 24 MHz

without

- 90 -

Preliminary W79E4051/W79E2051 Data Sheet

27 PACKAGE DIMENSIONS

27.1 20-pin SOP

11

c

20

E

H

E

L

1

10

O

D

0.25

A

Y

SEATING PLANE

e

GAUGE P

A1

b

Control demensions are in milmeters .

DIMENSION IN MM DIMENSION IN INCH

SYMBOL

MIN.

2.35

0.10

0.33

0.23

MAX.

2.65

MIN.

0.093

MAX.

0.104

0.012

0.020

A

A1

b

0.004

0.013

0.30

0.51

c

0.32

0.009

0.291

0.496

0.013

0.299

7.40

E

D

7.60

13.00

0.512

12.60

e

0.050 BSC

1.27 BSC

10.65

0.10

1.27

8

H

Y

10.00

0.394

0.419

0.004

0.050

8

E

0.40

0

0.016

0

L

θ

Figure 27-1: 20L SOP-300mil

Publication Release Date: April 16, 2009

Revision A06

- 91 -

Preliminary W79E4051/W79E2051 Data Sheet

27.2 20-pin DIP

D

20

11

1

E

1

10

E

S

c

1

2

A

Base Plane

Seating Plane

L

B

e₁

e_A

α

B ₁

Dimension in inch

Dimension in mm

Symbol

Nom

Min

Max Min

0.175

Max

4.45

A

0.010

0.125

0.25

1

A

0.130 0.135

3.18

0.41

1.47

0.20

3.30

0.46

1.52

0.25

20.06

7.62

6.35

2.54

3.30

3.43

0.56

1.63

0.36

26.42

7.87

6.48

2.79

2

A

0.016 0.018

0.022

0.064

B

0.060

0.058

0.008

1

B

0.010 0.014

1.026 1.040

c

D

E

0.310

0.255

0.110

0.290

0.245

0.300

0.250

7.37

6.22

2.29

1

E

e

1

0.090 0.100

3.05

0

0.140

15

0.120

0

0.130

3.56

15

L

α

A

e

9.53

1.91

0.335

0.375

0.075

8.51

0.355

9.02

S

Figure 27-2: 20L DIP-300mil

- 92 -

Preliminary W79E4051/W79E2051 Data Sheet

27.3 20-pin SSOP

D

11

20

DTEAIL A

E

H

E

1

10

b

A

A2

SEATING PLANE

q

L

L1

Y

e

b

A1

DETAIL A

DIMENSION IN MM

DIMENSION IN INCH

SYMBOL

MIN.

NOM

MAX.

MIN.

NOM

MAX.

0.079

2.00

A

A1

A2

b

c

D

0.05

1.65 1.75 1.85

0.002

0.065

0.069

0.073

0.015

0.010

0.22

0.09

6.90

5.00

0.38 0.009

0.25 0.004

7.20 7.50

5.30 5.60

7.80 8.20

0.65

0.272 0.283 0.295

0.197 0.209 0.220

0.291 0.307 0.323

E

H

E

7.40

0.0256

e

L

L1

0.95

0.037

0.55 0.75

1.25

0.021 0.030

0.050

0.004

8

Y

q

0.10

8

0

Figure 27-3: 20-Pin SSOP

Publication Release Date: April 16, 2009

Revision A06

- 93 -

Preliminary W79E4051/W79E2051 Data Sheet

28 REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A01

July 9, 2008

-

Initial Issued

78

86

1. Add a notice for the untrimmed internal RC OSC.

2. Modify the test condition of “Hysterisis range of BOD

voltage” in DC spec.

A02

A03

August 4, 2008

August 29, 2008

85

86

3. Modify the Max value of power down current.

1. Revised Maximum Current suck by total I/O pins from

75mA to 80mA.

91

2. Modify “24.6 RC OSC AND AC CHARACTERISTICS”

25

88

83

1. Revise the description of SFR bit LPBOV

2. Correct I_BO23215 with 32/15.

3. Add Chapter 23 ICP

December 22,

2008

A04

A05

A06

February 25,

2009

1. Add DC spec of Data Flash program/erase voltage

5, 84

5,6,7

1. Add SSOP20 parts of W79E4051ARG/RARG and

W79E2051ARG/RARG.

April 16, 2009

94

2. Add SSOP-20 package dimension diagram.

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any

malfunction or failure of which may cause loss of human life, bodily injury or severe property

damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic

energy control instruments, airplane or spaceship instruments, the control or operation of

dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all

types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay

claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the

damages and liabilities thus incurred by Nuvoton.

- 94 -


型号：	W79E4051AKG
厂家：	NUVOTON
描述：	8-BIT MICROCONTROLLER
文件：	总94页 (文件大小：2079K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W79E4051AKG [NUVOTON]

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