WAU8812 [NUVOTON]
Mono Audio Codec with Speaker Driver;
| 型号： | WAU8812 |
| 厂家： | 
NUVOTON |
| 描述： | Mono Audio Codec with Speaker Driver |
| 文件： | 总15页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mono Audio Codec with Speaker Driver
emPowerAudio™
1. GENERAL DESCRIPTION
The WAU8812 is a cost effective and low power wideband MONO audio CODEC. It is designed for voice telephony
related applications. Functions include Automatic Level Control (ALC) with noise gate, PGA, standard audio interface
I2S, PCM with time slot assignment, and on-chip PLL. The device provides one differential microphone input and one
single ended auxiliary input (multi purpose). There are few variable gain control stages in the audio path. It also
includes MONO line output and integrated BTL speaker driver.
The analog inputs have PGA on the front end, allowing dynamic range optimization with a wide range of input
sources. The microphone amplifiers have a programmable gain from -12dB to +35.25dB to handle both amplified
microphones. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features voice band
digital filtering. Voice-band data is accepted by the audio interface (I2S). The DAC converter path includes filtering
and mixing, programmable-gain amplifiers (PGA), and soft muting. The digital interfaces, 2-Wire or SPI, have
independent supply voltage to allow integration into multiple supply systems. The WAU8812 operates at supply
voltages from 2.5V to 3.6V, although the digital core can operate at voltage as low as 1.71V to save power.
2. FEATURES
24-bit signal processing linear Audio CODEC
Low Power, Low Voltage
Audio DAC: 93dB SNR and -84dB THD
Audio ADC: 91dB SNR and -79dB THD
Support variable sample rates for 8 - 48KHz
Integrated BTL Speaker Driver 0.8W into 8Ω / 5V
Integrated Headset Driver 40mW into 16Ω / 3.3V
Analog Supply: 2.5V to 3.6V
Digital Supply: 1.71V to 1.95V
Nominal Operating Voltage: 3.3V
Additional features
Programmable ALC
ADC Notch Filter
Programmable High Pass Filter
Digital A/D-D/A Passthrough
AEC-Q100 & TS16949 qualification
Industrial temperature: range: –40°C to +85°C
Analog I/O
Integrated programmable Microphone Amplifier
Integrated Line Input and Line Output
Integrated Audio Switches
Earphone / Speaker / Line Output selection
Microphone / Line Inputs selection
Low Noise bias supplied for microphone
Digital Playback Limiter
Applications
VoIP Telephones
Conference speaker-phone
IP PBX
Mobile Telephone Hands-free Kits
Residential & Consumer Intercoms
General Purpose low power audio CODEC
On-chip PLL
Interfaces
I2S digital interface
PCM output with time slot assignment
SPI & 2-Wire serial control Interface (I2C style;
Read/Write capable)
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 1 of 15
October 2008
3. PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREF
MIC -
AUX
VDDSPK
3
MIC +
MICBIAS
NC
VDDSPK
SPKOUT -
VSSSPK
VSSSPK
SPKOUT +
MOUT
4
5
6
VDDA
VSSA
VSSA
VDDC
VDDB
VSSD
ADCOUT
DACIN
FS
WAU8812
MONO AUDIO
CODEC
7
8
SSOP 28-Pin
9
MODE
10
11
12
13
14
SDIO
SCLK
CSb/GPIO
MCLK
BCLK
Figure 1: 28-Pin SSOP Package
Figure 2: 32-Pin QFN Package
Page 2 of 15
emPowerAudio™
Preliminary Datasheet Revision 0.85
October 2008
4. PIN DESCRIPTION
Pin Name
VREF
28-Pin
32-Pin
Functionality
A/D
Pin Type
1
2
3
4
5
6
7
8
29
30
31
32
1
Decoupling internal analog mid supply reference
Microphone Negative Input
Microphone Positive Input
Microphone Bias
A
A
A
A
O
I
MIC-
MIC+
MICBIAS
NC
I
O
No Connect
VDDA
VSSA
VSSA
2
Analog Supply
A
A
A
I
3
Analog Ground
O
O
4
Analog Ground
Logic supply voltage. This pin should not be hooked
up to an external supply
-
5
D
O
VDDL
VDDC
VDDB
9
6
Digital Supply Core
Digital Supply Buffer
Digital Ground
D
D
D
D
D
D
D
D
D
D
D
D
D
D
I
I
10
11
-
7
VSSD
8
O
O
O
I
VSSD
9
Digital Ground
ADCOUT
DACIN
FS
12
13
14
15
16
17
18
19
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Digital Audio Data Output
Digital Audio Data Input
Frame Sync
I/O
I/O
I
BCLK
Bit Clock
MCLK
Master Clock
CSb/GPIO
SCLK
SPI Chip Select or General Purposes 1 I/O
SPI or 2-Wire Serial Clock
SPI Data In or 2-Wire I/O
SPI Data Output
I/O
I
SDIO
O
O
I
SO
MODE
NC
20
-
Interface Select (2-Wire or SPI)
No Connect
MOUT
SPKOUT+
VSSSPK
VSSSPK
SPKOUT-
VDDSPK
VDDSPK
AUX
21
22
23
24
25
26
27
28
MONO Output
A
A
A
A
A
A
A
A
O
O
O
O
O
I
Speaker Positive Output
Speaker Ground
Speaker Ground
Speaker Negative Output
Speaker Supply
Speaker Supply
I
Auxiliary Input
I
Table 1: Pin Description for SSOP and QFN Packages
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 3 of 15
October 2008
5. BLOCK DIAGRAM
Figure 3: WAU82 General lock iagram
Page 4 of 15
emPowerAudio™
Preliminary Datasheet Revision 0.85
October 2008
6. REGISTER DESCRIPTION
Register
Address
Register Bits
D4
Default
DEC
0
HEX
0x0
D8
D7
D6
D5
D3
D2
D1
D0
RESET (SOFTWARE)
POWER MANAGEMENT
1
2
3
0x01
0x02
0x03
DCBUFEN
0
0
AUXEN
0
PLLEN MICBIASEN
ABIASEN
0
IOBUFEN
PGAEN
REFIMP
0x000
0x000
0x000
0
0
0
BSTEN
0
0
ADCEN
DACEN
MOUTEN NSPKEN PSPKEN
BIASGEN
MOUTMXEN SPKMXEN
AUDIO CONTROL
AIFMT[1:0]
4
5
0x04
0x05
0x06
0x07
0x08
0x0A
0x0B
0x0E
0x0F
BCLKP
FSP
0
WLEN[1:0]
DACPHS
ADCPHS
0
0x050
0x000
0x140
0x000
0x000
0x000
0x0FF
0x100
0x0FF
0
0
CMB8
DACCM[1:0]
ADCCM[1:0]
ADDAP
CLKIOEN
SCLKEN
6
CLKM
MCLKSEL[2:0]
BCLKSEL[2:0]
0
7
SPIEN
0
0
0
0
0
0
0
SMPLR[2:0]
AUTOMT
0
8
0
GPIOPLL[1:0]
DEEMP[1:0]
GPIOPL
DACOS
GPIOSEL[2:0]
0
10
11
14
15
0
DACMT
DACPL
ADCPL
0
HPFEN
0
DACGAIN
ADCOS
ADCGAIN
DIGITAL TO ANALOG (DAC) LIMITER
DACLIMDCY[3:0]
DACLIMTHL[2:0]
NOTCH FILTER
NFCA0[13:7]
HPFAM
HPF[2:0]
0
24
25
0x18
0x19
DACLIMEN
DACLIMATK[3:0]
DACLIMBST[3:0]
0x032
0x000
0
27
28
29
30
0x1B
0x1C
0x1D
0x1E
NFCU
NFCU
NFCU
NFCU
NFCEN
0x000
0x000
0x000
0x000
0
0
0
NFCA0[6:0]
NFCA1[13:7]
NFCA1[6:0]
ALC CONTROL
32
33
34
35
0x20
0x21
0x22
0x23
ALCEN
ALCZC
ALCM
0
0
0
0
ALCMXGAIN[2:0]
ALCMNGAIN[2:0]
0x038
0x00B
0x032
0x000
ALCHT[3:0]
ALCDCY[3:0]
ALCSL[3:0]
ALCATK[3:0]
0
0
0
ALCNEN
ALCNTH[2:0]
PLL CONTROL
36
37
38
39
0x24
0x25
0x26
0x27
0
0
0
0
0
0
0
PLLMCLK
PLLN[3:0]
0x008
0x00C
0x093
0x0E9
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
INPUT, OUTPUT & MIXER CONTROL
40
44
45
47
49
50
54
56
58
0x28
0x2C
0x2D
0x2F
0x31
0x32
0x36
0x38
0x3A
0
0
0
0
0
0
0
0
0
MOUTATT
SPKATT MICBIASM
0x000
0x003
0x010
0x100
0x002
0x001
0x039
0x001
0x000
MICBIASV
AUXM
AUXPGA NMICPGA PMICPGA
0
PGAZC
PGAMT
PGAGAIN[5:0]
PGABST
0
PMICBSTGAIN
0
MOUT3V
0
AUXBSTGAIN
0
0
0
0
0
0
0
SPK3V
0
TSEN
AOUTIMP
DACSPK
0
0
SPKZC
0
AUXSPK
BYPSPK
0
0
SPKMT
MOUTMT
SPKGAIN[5:0]
0
0
0
AUXMOUT BYPMOUT DACMOUT
LPSPKA
LPIPBST LPADC
LPSPKD
LPDAC
TRIMREG
0
IBADJ
0
PCM TIME SLOT CONTROL
59
60
62
63
0x3B
0x3C
0x3E
0x3F
TSLOT[8:0]
0x000
0x000
0x000
0x01A
PCMTSEN
TRI
0
PCM8BIT PUDOEN
PUDPE
PUDPS
REV[7:0]
0
0
0
1
TSLOT[9:8]
0
0
0
0
0
1
1
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 5 of 15
October 2008
7. ABSOLUTE MAXIMUM RATINGS
CONDITION
VDDB, VDDC, VDDA supply voltages
VDDSPK supply voltage (MOUT3V=0, SPK3V=0)
VDDSPK supply voltage (MOUT3V=1, SPK3V=1)
Core Digital Input Voltage range
MIN
-0.3
MAX
+3.63
Units
V
-0.3
+5.50
V
-0.3
+3.63
V
VSSD – 0.3
VSSD – 0.3
VSSA – 0.3
-40
VDDC + 0.30
VDDB + 0.30
VDDA + 0.30
+85
V
Buffer Digital Input Voltage range
Analog Input Voltage range
V
V
Industrial operating temperature
0C
0C
Storage temperature range
-65
+150
CAUTION: Do not operate at or near the maximum ratings listed for extended period of time. Exposure to such
conditions may adversely influence product reliability and result in failures not covered by warranty. These devices
are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
8. OPERATING CONDITIONS
Typical
Value
Condition
Symbol
Min Value
Max Value
Units
Digital supply range (Core)
VDDC
VDDB
1.71
1.71
2.50
2.50
2.50
3.60
3.60
3.60
3.60
5.50
V
V
V
V
V
Digital supply range (Buffer)
Analogue supplies range
VDDA
Speaker supply (MOUT3V=0, SPK3V=0)
Speaker supply (MOUT3V=1, SPK3V=1)
VDDSPK
VDDSPK
VSSD, VSSA,
VSSSPK
Ground
0
V
1. VDDA must be ≥ VDDC.
2. VDDB must be ≥ VDDC.
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 6 of 15
October 2008
9. ELECTRICAL CHARACTERISTICS
VDDC = 1.8V, VDDA = VDDB = SPK3V = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue to Digital Converter (ADC)
PGABST = 0dB
1.0
0
VRMS
dBV
dB
Full scale input signal 1
VINFS
PGAGAIN = 0dB
Signal to Noise Ratio 2
Total Harmonic Distortion 3
SNR
THD
Gain = 0dB, A-weighted
Input = -1dBFS, Gain = 0dB
87
91
-79
-65
dB
Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kꢀ / 50pF load)
1.5x
MOUT3V=0
MOUT3V=1
(VREF
)
Full Scale output signal 1
VRMS
VREF
A-weighted (ADC/DAC
oversampling rate of 128)
Signal to Noise Ratio 2
SNR
THD
90
93
dB
dB
Total Harmonic Distortion 3
RL = 10 kꢀ; -1.5dBfs
-84
-70
Auxiliary Analogue Input (AUX)
1
0
VRMS
dBV
Full-scale Input Signal Level1
VINFS
Gain = 0dB
AUXM=0
Input Resistance
Input Capacitance
RAUX
CAUX
20
kꢀ
10
pF
Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier
(PGA)
PGABST = 0dB
1
0
VRMS
dBV
Full-scale Input Signal Level 1
VINFS
PGAGAIN = 0dB
35.2
5
Programmable input PGA gain
Programmable Gain Step Size
-12
dB
dB
Guaranteed monotonic
Boost disabled = 0
0.75
0
Programmable Boost PGA gain
Mute Attenuation
dB
dB
µV
Boost enabled = 1
20
100
0 to 20kHz,
PGA equivalent output noise
110
Gain set to 35.25dB
PGA Gain = 35.25dB
kꢀ
kꢀ
kꢀ
1.6
47
75
Auxiliary Input resistance
RAUX
PGA Gain = 0dB
PGA Gain = -12dB
Positive Microphone Input
resistance
kꢀ
RMIC+
CMIC
PMICPGA = 1
94
10
Input Capacitance
pF
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 7 of 15
October 2008
VDDC = 1.8V, VDDA = VDDB = SPK3V = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
Speaker Output PGA
Programmable Gain
SYMBOL
TEST CONDITIONS
MIN
-57
TYP
MAX
6
UNIT
dB
dB
Programmable Gain Step
Size
Guaranteed monotonic
1
BTL Speaker Output (SPKOUT+, SPKOUT- with 8ꢀ bridge tied load)
SPKBOOST = 0
VCCSPK / 3.3
Full scale output 7
SPKBOOST = 1
VRMS
(VCCSPK / 3.3) * 1.5
Output power is very closely correlated with THD; see
below
Output Power
PO
SPK3V=3.3V, RL = 8ꢀ
SPK3V=5V, RL = 8ꢀ
90
90
dB
dB
Signal to Noise Ratio
SNR
PO =180mW, RL = 8ꢀ,
SPK3V=3.3V
-85
-53
-85
-82
dB
dB
dB
dB
PO =400mW, RL = 8ꢀ,
SPK3V=3.3V
Total Harmonic Distortion
(3-stage Output Amplifier)
THD
PO =360mW, RL = 8ꢀ,
SPK3V=5V
PO =800mW, RL = 8ꢀ,
SPK3V=5V
Power Supply Rejection
Ratio (50Hz - 22kHz)
VDDSPK = 5V (non-
boost)
80
80
dB
dB
PSRR
VDDSPK = 3V (boost)
Headphone’ output (SPKOUTP, SPKOUTN with resistive load to ground)
Full scale output 7
VREF
90
VRMS
dB
Signal to Noise Ratio
A-weighted
SNR
THD
Po=20mW, RL = 16ꢀ,
VDDSPK = 3.3V
-84
-85
dB
dB
Total Harmonic Distortion
Po=20mW, RL = 32ꢀ,
VDDSPK = 3.3V
Microphone Bias
Bias Voltage
(MBIASV = 0)
(MBIASV = 1)
0.9*
VDDA
V
VMICBIAS
IMICBIAS
VN
0.65*
VDDA
V
Bias Current Source
Output Noise Voltage
3
mA
MICBIASM = 0 (1kHz to
20kHz)
14
nV/√Hz
MICBIASM = 1 (1kHz to
20kHz)
4
nV/√Hz
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 8 of 15
October 2008
VDDC = 1.8V, VDDA = VDDB = SPK3V = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Automatic Level Control (ALC)/Limiter – ADC only
Target Record Level
-28.5
-12
-6
dB
dB
Programmable Gain
35.25
Programmable Gain Step
Size
0.75
dB
ms
Guaranteed Monotonic
Gain Hold Time 4, 6
tHOLD
tDCY
0 / 2.67 / …/ 43691 (time
doubles with each step)
MCLK=12.288MHz
ALC Mode
3.3 / 6.6 / 13.1 / … / 3360
(time doubles with each step)
ALCM=0
ms
ms
MCLK=12.288MHz
Limiter Mode
ALCM=1
Gain Ramp-Up (Decay)
Time 5, 6
0.73 / 1.45 / 2.91 / … / 744
(time doubles with each step)
MCLK=12.288MHz
ALC Mode
0.83 / 1.66 / 3.33 / … / 852
(time doubles with each step)
ALCM=0
ms
ms
MCLK=12.288MHz
Limiter Mode
ALCM=1
Gain Ramp-Down (Attack)
Time 5, 6
tATK
0.18 / 0.36 / 0.73 / … / 186
(time doubles with each step)
MCLK=12.288MHz
Digital Input / Output
0.7 ×
VDDC
0.3 ×
Input HIGH Level
VIH
VIL
V
V
V
V
Input LOW Level
Output HIGH Level
Output LOW Level
VDDC
0.9 ×
VDDC
VOH
VOL
IOL = 1mA
0.1 x
VDDC
IOH = -1mA
3.25
Notes
1. Full Scale is relative to VDDA (FS = VDDA/3.3.) Input level to RIP and LIP is limited to a maximum of -3dB so
that THD+N performance will not be reduced.
2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the
output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
3. THD+N (dB) - THD+N are a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It
does not apply to ramping down the gain when the signal is too loud, which happens without a delay.
5. Ramp-up and Ramp-Down times are defined as the time it takes to change the PGA gain by 6dB of its gain
range.
6. All hold, ramp-up and ramp-down times scale proportionally with MCLK
7. The maximum output voltage can be limited by the speaker power supply. If MOUT3V or SPK3V is, set then
VDDSPK should be 1.5xVDDA to prevent clipping taking place in the output stage (when PGA gains are set to
0dB).
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 9 of 15
October 2008
10. DIGITAL FILTER CHARACTERISTICS
TEST
CONDITIONS
PARAMETER
MIN
0
TYP
MAX
UNIT
ADC Filter
+/- 0.025dB
-6dB
0.454*fs
+/-0.025
Passband
0.5*fs
Passband Ripple
dB
dB
Stopband
Stopband
Group Delay
0.546*fs
-60
f > 0.546*fs
21/fs
ADC High Pass Filter
-3dB
3.7
High Pass Filter
Corner Frequency
-0.5dB
-0.1dB
10.4
21.6
Hz
DAC Filter
+/- 0.035dB
-6dB
0
0.454*fs
+/-0.035
Passband
0.5*fs
29/fs
Passband Ripple
dB
dB
Stopband
Stopband
Group Delay
0.546*fs
-55
f > 0.546*fs
Table 57 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
3. Note that this delay applies only to the filters and does not include
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 10 of 15
October 2008
Figure 5: ADC Filter Frequency Response
Figure 4: DAC Filter Frequency Response
Figure 6: DAC Filter Ripple
Figure 7: ADC Filter Ripple
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 11 of 15
October 2008
11. TYPICAL APPLICATION
Figure 8: Application Diagram 28-Pin SSOP
Figure 9: Application Diagram For 32-Pin QFN
Page 12 of 15
emPowerAudio™
Preliminary Datasheet Revision 0.85
October 2008
12. PACKAGE SPECIFICATION
12.1. 28 Pin SSOP
D
28
15
DTEAIL A
H
E
E
1
14
A
A2
b
SEATING PLANE
SEATING PLANE
θ
L
Y
L1
e
b
A1
DETAIL A
DIMENSION IN MM
DIMENSION IN INCH
SYMBOL
MIN. NOM MAX. MIN.
NOM MAX.
0.079
2.00
A
A1
A2
b
0.05
1.65 1.75 1.85
0.002
0.065
0.069
0.073
0.015
0.010
0.22
0.09
0.38 0.009
0.25 0.004
c
10.20
5.30 5.60
7.80 8.20
0.65
10.05
5.00
0.395 0.401 0.407
0.197 0.209 0.220
10.35
D
E
HE
7.40
0.291 0.307 0.323
0.0256
e
L
L1
0.95
0.037
0.55 0.75
1.25
0.021 0.030
0.050
0.004
8
Y
θ
0.10
8
0
0
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 13 of 15
October 2008
12.2. 32-Pin QFN
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 14 of 15
October 2008
13. ORDERING INFORMATION
Nuvoton Part Number Description
WAU8812_ _
Package Material:
Pb-free Package
G
=
Package Type:
R
Y
=
=
28-Pin SSOP Package
32-Pin QFN Package
emPowerAudio™
Preliminary Datasheet Revision 0.85
Page 15 of 15
October 2008
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