4030B [NXP]

Quadruple exclusive-OR gate; 四倍异或门


型号：	4030B
厂家：	NXP
描述：	Quadruple exclusive-OR gate 四倍异或门
文件：	总3页 (文件大小：32K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC

• The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

HEF4030B

gates

Quadruple exclusive-OR gate

January 1995

Product speciﬁcation

File under Integrated Circuits, IC04

Philips Semiconductors

Product speciﬁcation

HEF4030B

gates

Quadruple exclusive-OR gate

DESCRIPTION

The HEF4030B provides the positive quadruple

exclusive-OR function. The outputs are fully buffered for

highest noise immunity and pattern insensitivity of output

impedance.

Fig.2 Pinning diagram.

HEF4030BP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4030BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4030BT(D): 14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.1 Functional diagram.

Fig.2 Logic diagram (one gate).

TRUTH TABLE

I₁

FAMILY DATA, I_DDLIMITS category GATES

See Family Specifications

I₂

O₁

Notes

1. H = HIGH state (the more positive voltage)

L = LOW state (the less positive voltage)

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4030B

gates

Quadruple exclusive-OR gate

AC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C; C_L= 50 pF; input transition times ≤ 20 ns

V_DD

TYPICAL EXTRAPOLATION

FORMULA

SYMBOL

TYP.

MAX.

Propagation delays

I_n→ O_n

175

57 ns + (0,55 ns/pF) C_L

24 ns + (0,23 ns/pF) C_L

22 ns + (0,16 ns/pF) C_L

47 ns + (0,55 ns/pF) C_L

19 ns + (0,23 ns/pF) C_L

17 ns + (0,16 ns/pF) C_L

10 ns + (1,0 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

10 ns + (1,0 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

HIGH to LOW

t_PHL

t_PLH

t_THL

t_TLH

150

LOW to HIGH

Output transition times

HIGH to LOW

120

LOW to HIGH

V_DD

TYPICAL FORMULA FOR P (µW)

Dynamic power

dissipation per

package (P)

1 100 f_i+ ∑(f_oCL) × V_DD

where

4 900 f_i+ ∑(f_oCL) × V_DD

f_i= input freq. (MHz)

14 400 f_i+ ∑(f_oCL) × V_DD

f_o= output freq. (MHz)

C_L= load capacitance (pF)

∑(f_oC_L) = sum of outputs

V_DD= supply voltage (V)

January 1995

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