74ABT16821ADGG_技术文档

INTEGRATED CIRCUITS

74ABT16821A

74ABTH16821A

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Sep 28

IC23 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

FEATURES

DESCRIPTION

The 74ABT16821A high-performance BiCMOS device combines

low static and dynamic power dissipation with high speed and high

output drive.

• 20-bit positive-edge triggered register

• Multiple V and GND pins minimize switching noise

CC

• Live insertion/extraction permitted

• Power-up reset

The 74ABT16821A has two 10-bit, edge triggered registers, with

each register coupled to a 3-State output buffer. The two sections of

each register are controlled independently by the clock (nCP) and

Output Enable (nOE) control gates.

• Power-up 3-State

Each register is fully edge triggered. The state of each D input, one

set-up time before the Low-to-High clock transition, is transferred to

the corresponding flip-flop’s Q output.

• 74ABTH16821A incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused

inputs

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors.

• Output capability: +64mA/-32mA

• Latch-up protection exceeds 500mA per JEDEC Std 17

The active Low Output Enable (nOE) controls all ten 3-State buffers

independent of the register operation. When nOE is Low, the data in

the register appears at the outputs. When nOE is High, the outputs

are in high impedance “off” state, which means they will neither drive

nor load the bus.

• ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

Two options are available, 74ABT16821A which does not have the

bus-hold feature and 74ABTH16821A which incorporates the

bus-hold feature.

QUICK REFERENCE DATA

CONDITIONS

= 25°C; GND = 0V

SYMBOL

PARAMETER

TYPICAL

UNIT

T

amb

t

Propagation delay

nCP to nQx

2.4

2.0

PLH

PHL

C = 50pF; V = 5V

ns

L

CC

C

Input capacitance

Output capacitance

V = 0V or V

CC

3

7

pF

IN

I

C

V

= 0V or V ; 3-State

O CC

OUT

CCZ

I

Outputs disabled; V = 5.5V

500

10

µA

mA

CC

Quiescent supply current

I

Outputs LOW; V = 5.5V

CC

CCL

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

SOT371-1

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

–40°C to +85°C

74ABT16821A DL

74ABT16821A DGG

74ABTH16821A DL

74ABTH16821A DGG

BT16821A DL

BT16821A DGG

BH16821A DL

BH16821A DGG

SOT364-1

SOT371-1

SOT364-1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

55, 54, 52, 51, 49, 48, 47, 45, 44, 43,

42, 41, 40, 38, 37, 36, 34, 33, 31, 30

1D0 - 1D9

2D0 - 2D9

Data inputs

2, 3, 5, 6, 8, 9, 10, 12, 13, 14,

15, 16, 17, 19, 20, 21, 23, 24, 26, 27

1Q0 - 1Q9

2Q0 - 2Q9

Data outputs

1, 28

56, 29

1OE, 2OE

1CP, 2CP

GND

Output enable inputs (active-Low)

Clock pulse inputs (active rising edge)

Ground (0V)

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

V

CC

Positive supply voltage

2

1998 Feb 27

853-1796 19026

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

PIN CONFIGURATION

LOGIC SYMBOL (IEEE/IEC)

1

1OE

1CP

2OE

2CP

EN2

C1

EN4

C3

1OE

1Q0

1Q1

GND

1Q2

1Q3

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1CP

1D0

1D1

GND

1D2

1D3

56

28

29

3

4

5

55

54

52

51

49

48

47

45

44

2

1D

2

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

6

3

5

V

7

V

CC

1Q4

1Q5

1Q6

GND

1Q7

1Q8

1Q9

2Q0

2Q1

2Q2

GND

2Q3

2Q4

2Q5

8

1D4

1D5

1D6

GND

1D7

1D8

1D9

2D0

2D1

2D2

GND

2D3

2D4

2D5

6

9

8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

9

10

12

13

43

42

41

40

38

37

36

34

33

31

30

14

15

16

17

19

20

21

23

24

26

27

1D9

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2D9

1Q9

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

2Q9

4

3D

V

CC

2Q6

2Q7

GND

2Q8

2Q9

2OE

2D6

2D7

GND

2D8

2D9

2CP

SH00003

FUNCTION TABLE

INPUTS

OUTPUTS

nQ0 - nQ9

SH00001

INTERNAL

REGISTER

OPERATING

MODE

nOE nCP nDx

L

↑

l

h

L

H

L

H

Load and read

register

LOGIC SYMBOL

56

54

52

51

49

48

47

45

44

43

L

↑

X

NC

Hold

H

↑

X

Dn

NC

Dn

Z

Disable

outputs

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9

1CP

1OE

H = High voltage level

56

1

h

=

High voltage level one set-up time prior to the Low-to-High

clock transition

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9

L

l

=

Low voltage level

Low voltage level one set-up time prior to the Low-to-High

clock transition

2

3

5

6

8

9

10

34

12

33

13

31

14

30

NC= No change

X

Z

↑

=

Don’t care

42

41

40

38

37

36

High impedance “off” state

Low to High clock transition

Not a Low-to-High clock transition

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9

↑

29

28

2CP

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9

15

16

17

19

20

21

23

24

26

27

SH00002

3

1998 Feb 27

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

LOGIC DIAGRAM

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

nD8

nD9

D

CP Q

nCP

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

nQ8

nQ9

SH00004

1, 2

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

CONDITIONS

RATING

UNIT

V

CC

I

IK

DC supply voltage

–0.5 to +7.0

–18

DC input diode current

V < 0

I

mA

V

3

V

I

DC input voltage

–1.2 to +7.0

–50

I

DC output diode current

V

O

< 0

mA

V

OK

3

V

OUT

DC output voltage

Output in Off or High state

Output in Low state

–0.5 to +5.5

128

I

DC output current

mA

OUT

Output in High state

–64

T

stg

Storage temperature range

–65 to 150

°C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNIT

MIN

4.5

0

MAX

V

DC supply voltage

5.5

V

CC

V

Input voltage

V

CC

I

V

High-level input voltage

Low-level Input voltage

High-level output current

Low-level output current

Input transition rise or fall rate

2.0

V

IH

V

0.8

–32

64

V

IL

I

mA

ns/V

°C

OH

I

OL

∆t/∆v

0

10

T

amb

Operating free-air temperature range

–40

+85

4

1998 Feb 27

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

DC ELECTRICAL CHARACTERISTICS

LIMITS

T

= -40°C

to +85°C

amb

SYMBOL

PARAMETER

TEST CONDITIONS

T

amb

= +25°C

UNIT

Min

Typ

–0.9

2.9

Max

Min

Max

V

Input clamp voltage

V

= 4.5V; I = -18mA

–1.2

V

IK

CC

IK

= 4.5V; I = -3mA; V = V or V

2.5

3.0

2.0

2.5

3.0

2.0

OH

I

IL

IH

V

OH

High-level output voltage

= 5.0V; I = -3mA; V = V or V

3.4

V

OH

I

IL

= 4.5V; I = -32mA; V = V or V

IH

2.4

V

OH

I

IL

V

OL

Low-level output voltage

= 4.5V; I = 64mA; V = V or V

IH

0.36

0.13

0.55

±1.0

±1

V

OL

I

IL

3

V

RST

Power-up output voltage

= 5.5V; I = 1mA; V = GND or V

V

O

I

CC

I

Input leakage current

= 5.5V; V = V or GND

±0.01 ±1.0

µA

I

CC

= 5.5V; V = V or GND

Control pins

Data pins

±0.01

0.01

–1

±1

1

I

CC

Input leakage current

74ABTH16821A

I

= 5.5V; V = V

1

I

= 5.5V; V = 0

–3

–5

I

= 4.5V; V = 0.8V

35

I

5

Bus Hold current inputs

74ABTH16821A

I

µA

V

CC

V

CC

V

CC

= 4.5V; V = 2.0V

–75

HOLD

I

= 5.5V; V = 0 to 5.5V

±800

I

Power-off leakage current

Power-up/down 3-State

= 0.0V; V or V ≤ 4.5V

±5.0

±100

±50

±100

±50

µA

OFF

O

I

V

CC

V

OE

= 2.1V; V = 0.5V; V = GND or V

;

O

I

CC

I

PU/PD

4

output current

= Don’t care

I

3-State output High current

3-State output Low current

V

= 5.5V; V = 2.7V; V = V or V

1.0

10

µA

OZH

CC

O

I

IL

IH

I

V

= 5.5V; V = 0.5V; V = V or V

–1.0

–10

OZL

O

I

IL

Output High leakage

current

I

V

CC

= 5.5V; V = 5.5V; V = GND or V

5.0

50

µA

CEX

O

I

1

I

Output current

V

= 5.5V; V = 2.5V

–50

–90

0.5

10

–180

1

–50

–180

1

mA

O

CC

O

I

= 5.5V; Outputs High, V = GND or V

CCH

I

CC

I

Quiescent supply current

Additional supply current

= 5.5V; Outputs Low, V = GND or V

19

1

19

1

CCL

I

CC

= 5.5V; Outputs 3-State; V = GND or V

0.5

CCZ

I

CC

V

CC

V

CC

= 5.5V; one input at 3.4V, other inputs at

or GND

∆I

0.25

1.5

mA

CC

2

per input pin

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V a transition

CC

time of up to 100µsec is permitted.

5. This is the bus hold overdrive current required to force the input to the opposite logic state.

5

1998 Feb 27

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

AC CHARACTERISTICS

GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω

R

F

L

LIMITS

MAX

T

= -40 to

+85 C

= +5.0V ±0.5V

amb

o

T

V

= +25 C

amb

CC

o

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0V

V

CC

MIN

TYP

MIN

MAX

f

Maximum clock frequency

1

160

250

160

MHz

ns

MAX

t

Propagation delay

nCP to nQx

1.3

1.1

2.4

2.0

3.3

2.6

1.3

1.1

3.7

3.0

PLH

PHL

t

Output enable time

to High and Low level

3

4

1.4

1.2

2.5

2.3

3.3

3.0

1.4

1.2

4.1

3.7

PZH

PZL

ns

t

Output disable time

from High and Low level

3

4

1.6

1.3

3.2

2.3

4.1

3.1

1.6

1.3

4.8

3.3

PHZ

PLZ

AC SETUP REQUIREMENTS

GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω

R

F

L

LIMITS

o

T

V

= +25 C

= +5.0V

T

V

= -40 to +85 C

amb

CC

amb

CC

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0V ±0.5V

MIN

TYP

MIN

MAX

t (H)

t (L)

s

Setup time, High or Low

nDx to nCP

1.8

1.2

–0.9

1.8

s

2

1

ns

t (H)

Hold time, High or Low

nDx to nCP

1.0

0.8

–1.0

1.0

h

t (L)

h

t (H)

nCP pulse width

High or Low

2.5

0.8

1.0

2.5

w

t (L)

w

AC WAVEFORMS

3.0V or V

whichever

is less

CC

nOE

1/f

MAX

3.0V or V

CC

V

M

whichever

is less

0V

nCP

nQx

V

t

V

M

t

PHZ

PZH

t

w

(H)

0V

t

(L)

w

V

OH

PLH

PH

L

Y

V

M

OH

nQx

0V

V

M

V

OL

SH00007

SH00005

Waveform 3. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock frequency

3.0V or V

CC

nOE

nQx

whichever

is less

3.0V or V

whichever

is less

CC

V

M

t

0V

V

M

nDx

CP

M

t

PZL

PLZ

0V

t (H) t (H)

s

t (L) t (L)

s h

3.0V or V

h

CC

3.0V or V

CC

whichever

is less

V

M

V

X

0V

V

OL

M

0V

SH00008

Waveform 4. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

SH00006

Waveform 2. Data Setup and Hold Times

6

1998 Feb 27

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

TEST CIRCUIT AND WAVEFORM

t

W

V

AMP (V)

90%

CC

90%

7.0V

NEGATIVE

PULSE

V

M

10%

M

10%

R

L

0V

V

OUT

IN

PULSE

GENERATOR

D.U.T.

t

(t

)

t

(t

)

R

THL

F

TLH

)

(t

)

F

R

L

C

TLH

R

THL

T

L

AMP (V)

90%

M

90%

POSITIVE

PULSE

V

M

Test Circuit for 3-State Outputs

10%

t

W

0V

SWITCH POSITION

V

= 1.5V

M

TEST

SWITCH

Input Pulse Definition

t

closed

PLZ

PZL

t

closed

open

All other

INPUT PULSE REQUIREMENTS

DEFINITIONS

R = Load resistor; see AC CHARACTERISTICS for value.

L

FAMILY

Amplitude

3.0V

Rep. Rate

1MHz

t

F

W

R

C = Load capacitance includes jig and probe capacitance;

L

see AC CHARACTERISTICS for value.

74ABT/H16

500ns 2.5ns 2.5ns

R = Termination resistance should be equal to Z

T

of

OUT

pulse generators.

SA00018

7

1998 Feb 27

Philips Semiconductors

Preliminary specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm

SOT371-1

8

1998 Feb 27

Philips Semiconductors

Preliminary specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm

SOT364-1

9

1998 Feb 27

Philips Semiconductors

Product specification

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

74ABT16821A

74ABTH16821A

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1998

Sunnyvale, California 94088–3409

Telephone 800-234-7381

print code

Date of release: 05-96

9397-750-03501

Document order number:

Philips

Semiconductors

10

yyyy mmm dd


型号：	74ABT16821ADGG
厂家：	NXP
描述：	20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State 20位总线接口D型触发器;正边沿触发三态触发器
文件：	总10页 (文件大小：84K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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