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74ABT16821ADL,118 [NXP]

74ABT16821A - 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state SSOP 56-Pin;
74ABT16821ADL,118
型号： 74ABT16821ADL,118
厂家： NXP    NXP
描述：

74ABT16821A - 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state SSOP 56-Pin
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74ABT16821A  
20-bit bus-interface D-type flip-flop; positive-edge trigger;  
3-state  
Rev. 03 — 16 March 2010  
Product data sheet  
1. General description  
The 74ABT16821A high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT16821A has two 10-bit, edge-triggered registers, with each register coupled to  
a 3-state output buffer. The two sections of each register are controlled independently by  
the clock (nCP) and output enable (nOE) control gates.  
Each register is fully edge triggered. The state of each D input, one set-up time before the  
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.  
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS  
memories, or MOS microprocessors.  
The active-LOW output enable (nOE) controls all ten 3-state buffers independent of the  
register operation. When nOE is LOW, the data in the register appears at the outputs.  
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will  
neither drive nor load the bus.  
2. Features and benefits  
„ 20-bit positive-edge triggered register  
„ Multiple VCC and GND pins minimize switching noise  
„ Live insertion and extraction permitted  
„ Output capability: +64 mA and −32 mA  
„ Power-up 3-state  
„ Power-up reset  
„ Latch-up protection exceeds 500 mA per JESD78B class II level A  
„ ESD protection:  
‹ HBM JESD22-A114F exceeds 2000 V  
‹ MM JESD22-A115-A exceeds 200 V  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature  
range  
Name  
Description  
Version  
74ABT16821ADL  
−40 °C to +85 °C SSOP56  
plastic shrink small outline package; 56 leads;  
body width 7.5 mm  
SOT371-1  
SOT364-1  
74ABT16821ADGG  
−40 °C to +85 °C TSSOP56  
plastic thin shrink small outline package; 56 leads;  
body width 6.1 mm  
4. Functional diagram  
1
1OE  
1CP  
EN2  
56  
C1  
EN4  
C3  
28  
29  
2OE  
2CP  
2
3
5
6
8
9
10  
12  
13  
14  
15  
16  
17  
19  
20  
21  
23  
24  
26  
27  
55  
54  
52  
51  
49  
48  
47  
45  
44  
43  
42  
41  
40  
38  
37  
36  
34  
33  
31  
30  
1D  
2
1D0  
1D1  
1D2  
1D3  
1D4  
1D5  
1D6  
1D7  
1D8  
1D9  
2D0  
2D1  
2D2  
2D3  
2D4  
2D5  
2D6  
2D7  
2D8  
2D9  
1Q0  
1Q1  
1Q2  
1Q3  
1Q4  
1Q5  
1Q6  
1Q7  
1Q8  
1Q9  
2Q0  
2Q1  
2Q2  
2Q3  
2Q4  
2Q5  
2Q6  
2Q7  
2Q8  
2Q9  
4
3D  
001aae855  
Fig 1. IEC logic symbol  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
2 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
55 54 52 51 49 48 47 45 44 43  
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9  
56  
1
1CP  
1OE  
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9  
2
3
5
6
8
9
10 12 13 14  
42 41 40 38 37 36 34 33 31 30  
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9  
29  
28  
2CP  
2OE  
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9  
15 16 17 19 20 21 23 24 26 27  
001aae856  
Fig 2. Logic symbol  
nD0  
nD1  
nD2  
nD3  
nD4  
nD5  
nD6  
nD7  
nD8  
nD9  
D
D
D
D
D
D
D
D
D
D
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP Q  
nCP  
nOE  
nQ0  
nQ1  
nQ2  
nQ3  
nQ4  
nQ5  
nQ6  
nQ7  
nQ8  
nQ9  
001aae857  
Fig 3. Logic diagram  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
3 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
5. Pinning information  
5.1 Pinning  
74ABT16821A  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE  
1CP  
1D0  
1D1  
GND  
1D2  
1D3  
2
1Q0  
1Q1  
GND  
1Q2  
1Q3  
3
4
5
6
7
V
CC  
V
CC  
8
1Q4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
1Q9  
2Q0  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
2Q5  
1D4  
1D5  
1D6  
GND  
1D7  
1D8  
1D9  
2D0  
2D1  
2D2  
GND  
2D3  
2D4  
2D5  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
V
V
CC  
CC  
2Q6  
2Q7  
GND  
2Q8  
2Q9  
2OE  
2D6  
2D7  
GND  
2D8  
2D9  
2CP  
001aae854  
Fig 4. Pin configuration  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
4 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
5.2 Pin description  
Table 2.  
Pin description  
Symbol  
Pin  
Description  
1OE, 2OE  
1Q0 to 1Q9  
GND  
1, 28  
output enable input (active LOW)  
2, 3, 5, 6, 8, 9, 10, 12, 13, 14  
4, 11, 18, 25, 32, 39, 46, 53  
7, 22, 35, 50  
data output  
ground (0 V)  
supply voltage  
VCC  
2Q0 to 2Q9  
2CP, 1CP  
2D0 to 2D9  
1D0 to1D9  
15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output  
29, 56  
clock pulse input (active rising edge)  
42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input  
55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input  
6. Functional description  
Table 3.  
Function table[1]  
Input  
Output  
Internal register Operating mode  
nOE  
L
nCP  
↑
nDx  
l
nQ0 to nQ9  
L
L
load + read register  
load + read register  
hold  
L
↑
h
H
NC  
Z
H
L
H or L  
L or H  
↑
X
NC  
NC  
Dn  
H
X
disable output  
disable output  
H
Dn  
Z
[1] H = HIGH voltage level;  
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;  
L = LOW voltage level;  
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;  
↑ = LOW-to-HIGH clock transition;  
NC = no change;  
X = don’t care;  
Z = high-impedance OFF-state.  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
5 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
−0.5  
−1.2  
−0.5  
−18  
−50  
-
Max  
+7.0  
+7.0  
+5.5  
-
Unit  
V
supply voltage  
[1]  
[1]  
input voltage  
V
VO  
output voltage  
output in OFF-state or HIGH-state  
VI < 0 V  
V
IIK  
input clamping current  
output clamping current  
output current  
mA  
mA  
mA  
mA  
°C  
°C  
IOK  
VO < 0 V  
-
IO  
output in LOW-state  
output in HIGH-state  
128  
-
−64  
-
[2]  
Tj  
junction temperature  
storage temperature  
150  
+150  
Tstg  
−65  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.  
8. Recommended operating conditions  
Table 5.  
Operating conditions  
Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
4.5  
0
Typ  
Max  
5.5  
VCC  
-
Unit  
V
supply voltage  
-
-
-
-
-
-
-
-
input voltage  
V
VIH  
HIGH-level input voltage  
LOW-level Input voltage  
HIGH-level output current  
LOW-level output current  
input transition rise and fall rate  
ambient temperature  
2.0  
-
V
VIL  
0.8  
-
V
IOH  
−32  
-
mA  
mA  
ns/V  
°C  
IOL  
64  
Δt/ΔV  
Tamb  
0
10  
in free air  
−40  
+85  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
6 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
9. Static characteristics  
Table 6.  
Static characteristics  
Symbol Parameter  
Conditions  
25 °C  
−40 °C to +85 °C Unit  
Min Typ Max  
Min  
Max  
VIK  
input clamping voltage VCC = 4.5 V; IIK = −18 mA  
−1.2 −0.9  
-
−1.2  
-
V
VOH  
HIGH-level output  
voltage  
VI = VIL or VIH  
VCC = 4.5 V; IOH = −3 mA  
VCC = 5.0 V; IOH = −3 mA  
VCC = 4.5 V; IOH = −32 mA  
2.5  
3.0  
2.0  
-
2.9  
3.4  
2.4  
-
-
-
2.5  
3.0  
2.0  
-
-
V
V
V
V
-
-
VOL  
LOW-level output  
voltage  
VCC = 4.5 V; IOL = 64 mA;  
VI = VIL or VIH  
0.36 0.55  
0.55  
[1]  
[2]  
VOL(pu)  
power-up LOW-level  
output voltage  
VCC = 5.5 V; IO = 1 mA;  
VI = GND or VCC  
-
0.13 0.55  
-
0.55  
V
II  
input leakage current VCC = 5.5 V; VI = VCC or GND  
-
-
±0.01 ±1.0  
±5.0 ±100  
-
-
±1.0 μA  
±100 μA  
IOFF  
power-off leakage  
current  
VCC = 0 V; VI or VO ≤ 4.5 V  
IO(pu/pd)  
IOZ  
power-up/power-down VCC = 2.1 V; VO = 0.5 V;  
output current  
-
±5.0 ±50  
-
±50  
μA  
VI = GND or VCC; nOE don’t care  
OFF-state output  
current  
VCC = 5.5 V; VI = VIL or VIH  
output HIGH-state at VO = 2.7 V  
output LOW-state at VO = 0.5 V  
-
-
-
1.0  
10  
-
-
-
10  
−10  
50  
μA  
μA  
μA  
−1.0 −10  
ILO  
output leakage current HIGH-state; VO = 5.5 V;  
VCC = 5.5 V; VI = GND or VCC  
5.0  
50  
[3]  
IO  
output current  
supply current  
VCC = 5.5 V; VO = 2.5 V  
VCC = 5.5 V; VI = GND or VCC  
outputs HIGH-state  
−180 −90  
−50  
−180  
−50  
mA  
ICC  
-
-
-
-
0.5  
10  
1.0  
19  
-
-
-
-
1.0  
19  
mA  
mA  
mA  
mA  
outputs LOW-state  
outputs 3-state  
0.5  
1.0  
1.5  
1.0  
1.5  
[4]  
ΔICC  
additional supply  
current  
per input pin; VCC = 5.5 V; one input  
at 3.4 V and other inputs at VCC or  
GND  
0.25  
CI  
input capacitance  
output capacitance  
VI = 0 V or VCC  
-
-
3
7
-
-
-
-
-
-
CO  
outputs disabled; VO = 0 V or VCC  
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.  
[2] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %  
a transition time of up to 100 μs is permitted.  
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
[4] This is the increase in supply current for each input at 3.4 V.  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
7 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
GND = 0 V; for test circuit, see Figure 8.  
Symbol Parameter Conditions  
25 °C; VCC = 5.0 V −40 °C to +85 °C; Unit  
VCC = 5.0 V ± 0.5 V  
Min Typ Max  
Min  
Max  
fmax  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
maximum  
frequency  
see Figure 5  
160 250  
-
160  
-
MHz  
ns  
LOW to HIGH  
propagation delay  
nCP to nQx, see Figure 5  
nCP to nQx, see Figure 5  
1.3  
1.1  
1.4  
1.2  
1.6  
1.3  
1.8  
2.4  
2.0  
2.5  
2.3  
3.2  
2.3  
1.2  
3.3  
2.6  
3.3  
3.0  
4.1  
3.1  
1.3  
1.1  
1.4  
1.2  
1.6  
1.3  
3.7  
3.0  
4.1  
3.7  
4.8  
3.3  
HIGH to LOW  
propagation delay  
ns  
OFF-state to HIGH nOE to nQx; see Figure 6  
propagation delay  
ns  
OFF-state to LOW nOE to nQx; see Figure 6  
propagation delay  
ns  
HIGH to OFF-state nOE to nQx; see Figure 6  
propagation delay  
ns  
LOW to OFF-state nOE to nQx; see Figure 6  
propagation delay  
ns  
tsu(H)  
tsu(L)  
th(H)  
th(L)  
tWH  
set-up time HIGH  
set-up time LOW  
hold time HIGH  
hold time LOW  
nDx to nCP; see Figure 7  
nDx to nCP; see Figure 7  
nDx to nCP; see Figure 7  
nDx to nCP; see Figure 7  
nCP; see Figure 5  
-
-
-
-
-
-
1.8  
+1.8  
1.0  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
+1.8 −0.9  
1.0 0.8  
+1.0 −1.0  
+1.0  
2.5  
pulse width HIGH  
pulse width LOW  
2.5  
2.5  
0.8  
1.0  
tWL  
nCP; see Figure 5  
2.5  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
8 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
11. Waveforms  
1 / f  
max  
V
I
nCP  
nQx  
V
V
V
M
M
M
0 V  
t
t
WL  
WH  
t
PLH  
t
PHL  
V
OH  
V
V
M
M
V
OL  
001aae858  
VM = 1.5 V  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig 5. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency  
V
I
nOE input  
V
M
GND  
3.5 V  
t
t
PZL  
PLZ  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
+ 0.3 V  
OL  
V
V
OL  
t
t
PZH  
PHZ  
V
OH  
− 0.3 V  
OH  
output  
V
HIGH-to-OFF  
OFF-to-HIGH  
M
GND  
outputs  
enabled  
outputs  
enabled  
outputs  
disabled  
001aal294  
VM = 1.5 V  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig 6. 3-state output enable time to HIGH-level and output disable time from HIGH- level  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
9 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
V
I
V
V
V
V
M
nDx  
CP  
M
M
M
0 V  
t
t
t
t
h(L)  
su(H)  
h(H)  
su(L)  
V
I
V
V
M
M
0 V  
001aae860  
The shaded areas indicate when the input is permitted to change for predictable output performance.  
VM = 1.5 V  
Fig 7. Set-up and hold times data input (nDx) to clock (CP)  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
EXT  
V
M
V
M
V
CC  
10 %  
10 %  
0 V  
R
L
L
V
V
O
t
t
I
f
r
G
DUT  
t
r
t
f
V
I
R
C
R
T
L
90 %  
90 %  
positive  
pulse  
V
V
M
M
mna616  
10 %  
10 %  
0 V  
t
W
001aai298  
a. Input pulse definition  
b. Test circuit  
Test data is given in Table 8.  
Definitions test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig 8. Load circuitry for switching times  
Table 8.  
Input  
VI  
Test data  
Load  
CL  
VEXT  
fI  
tW  
tr, tf  
RL  
tPHL, tPLH  
open  
tPZH, tPHZ  
tPZL, tPLZ  
7.0 V  
3.0 V  
1 MHz  
500 ns  
≤ 2.5 ns  
50 pF  
500 Ω  
open  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
10 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
12. Package outline  
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm  
SOT371-1  
D
E
A
X
c
y
H
v
M
A
E
Z
29  
56  
Q
p
A
2
A
A
(A )  
3
1
θ
pin 1 index  
L
L
28  
1
detail X  
w M  
b
p
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.  
8o  
0o  
0.4  
0.2  
2.35  
2.20  
0.3  
0.2  
0.22 18.55  
0.13 18.30  
7.6  
7.4  
10.4  
10.1  
1.0  
0.6  
1.2  
1.0  
0.85  
0.40  
mm  
2.8  
0.25  
0.635  
1.4  
0.25  
0.18  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT371-1  
MO-118  
Fig 9. Package outline SOT371-1 (SSOP56)  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
11 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm  
SOT364-1  
E
D
A
X
c
H
v
M
A
y
E
Z
56  
29  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
detail X  
1
28  
w
M
b
e
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions).  
A
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.  
8o  
0o  
0.15  
0.05  
1.05  
0.85  
0.28  
0.17  
0.2  
0.1  
14.1  
13.9  
6.2  
6.0  
8.3  
7.9  
0.8  
0.4  
0.50  
0.35  
0.5  
0.1  
mm  
1.2  
0.5  
1
0.25  
0.25  
0.08  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT364-1  
MO-153  
Fig 10. Package outline SOT364-1 (TSSOP56)  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
12 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
13. Abbreviations  
Table 9.  
Acronym  
BiCMOS  
DUT  
Abbreviations  
Description  
Bipolar Complementary Metal-Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
HBM  
Human Body Model  
MM  
Machine Model  
14. Revision history  
Table 10. Revision history  
Document ID  
74ABT16821A_3  
Modifications:  
Release date  
20100316  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74ABT_H16821A_2  
• The format of this data sheet has been redesigned to comply with the new identity  
guidelines of NXP Semiconductors.  
• Legal texts have been adapted to the new company name where appropriate.  
• Type number 74ABTH16821ADGG removed from Section 3 “Ordering information”.  
74ABT_H16821A_2  
74ABT_H16821A  
20021213  
Product specification  
-
74ABT_H16821A  
19980227  
Product specification  
-
-
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
13 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
suitable for use in medical, military, aircraft, space or life support equipment,  
15.2 Definitions  
nor in applications where failure or malfunction of an NXP Semiconductors  
product can reasonably be expected to result in personal injury, death or  
severe property or environmental damage. NXP Semiconductors accepts no  
liability for inclusion and/or use of NXP Semiconductors products in such  
equipment or applications and therefore such inclusion and/or use is at the  
customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on a weakness or default in the  
customer application/use or the application/use of customer’s third party  
customer(s) (hereinafter both referred to as “Application”). It is customer’s  
sole responsibility to check whether the NXP Semiconductors product is  
suitable and fit for the Application planned. Customer has to do all necessary  
testing for the Application in order to avoid a default of the Application and the  
product. NXP Semiconductors does not accept any liability in this respect.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use in automotive applications — This NXP  
Semiconductors product has been qualified for use in automotive  
applications. The product is not designed, authorized or warranted to be  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
14 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74ABT16821A_3  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 03 — 16 March 2010  
15 of 16  
74ABT16821A  
NXP Semiconductors  
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
6
Functional description . . . . . . . . . . . . . . . . . . . 5  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Recommended operating conditions. . . . . . . . 6  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 15  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2010.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 16 March 2010  
Document identifier: 74ABT16821A_3  

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