74ABT16823ADGG [NXP]
18-bit bus interface D-type flip-flop with reset and enable 3-State; 18位总线接口D型双稳态多谐振荡器具有复位和使能三态
| 型号： | 74ABT16823ADGG |
| 厂家： | 
NXP |
| 描述： | 18-bit bus interface D-type flip-flop with reset and enable 3-State |
| 文件： | 总12页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16823A
74ABTH16823A
18-bit bus interface D-type flip-flop
with reset and enable (3-State)
Product specification
1998 Feb 27
Supersedes data of 1995 Sep 28
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
FEATURES
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
• Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
• Live insertion/extraction permitted
• Power-up 3-State
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
• 74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.
• Power-up Reset
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
nCP to nQx
2.3
1.9
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
C
Input capacitance
Output capacitance
V = 0V or V
CC
4
6
pF
pF
IN
I
C
V = 0V or V ; 3-State
O CC
OUT
CCZ
I
Outputs disabled; V = 5.5V
500
9
µA
mA
CC
Quiescent supply current
I
Outputs low; V = 5.5V
CCL
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
BT16823A DL
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT16823A DL
74ABT16823A DGG
74ABTH16823A DL
74ABTH16823A DGG
BT16823A DGG
BH16823A DL
SOT364-1
SOT371-1
BH16823A DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
2, 27
SYMBOL
FUNCTION
1OE, 2OE
Output enable input (active-Low)
Data inputs
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
55, 30
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
Clock pulse input (active rising edge)
Clock enable input (active-Low)
Master reset input (active-Low)
Ground (0V)
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
V
CC
Positive supply voltage
2
1998 Feb 27
853-1791 19025
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1MR
1OE
1Q0
GND
1Q1
1Q2
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CP
1CE
1D0
GND
1D1
1D2
2
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
EN1
R2
1
55
56
27
28
30
29
3
G3
4
3C4
5
EN5
R6
6
V
7
V
G7
CC
CC
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
8
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
7C8
9
54
52
51
49
48
47
45
44
43
42
3
4D
1, 2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
25
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
41
40
38
37
36
34
33
31
8D
5, 6
V
V
CC
CC
2Q6
2Q7
GND
2Q8
2OE
2MR
2D6
2D7
GND
2D8
2CE
2CP
SH00015
SH00014
3
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
CP
Q
CP
Q
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nD
R
nD
R
nD
R
nD
nD
R
nD
R
nD
R
nD
R
nD
R
R
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
SH00016
n = 1 or 2
FUNCTION TABLE
INPUTS
nCE
OUTPUTS
nQ0 – nQ8
OPERATING MODE
nOE
nMR
nCP
nDx
L
L
L
L
H
L
H
H
H
X
X
L
X
↑
X
h
l
L
H
Clear
Load and read data
L
↑
L
H
X
↑
X
X
NC
Z
Hold
X
High impedance
H = High voltage level
h
L
l
=
=
=
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
↑
4
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
IK
I
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
I
DC output current
mA
OUT
output in High state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
0
MAX
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
5
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
= 4.5V; I = –32mA; V = V or V
2.4
OH
I
IL
IH
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
V
CC
V
CC
= 5.5V; I = 1mA; V = GND or V
0.13
±0.01
±0.01
V
OL
I
CC
3
voltage
I
Input leakage curent
= 5.5V; V = V or GND
±1
±1
±1
±1
µA
µA
I
I
CC
Control
pins
= 5.5V; V = V or GND
I
CC
Input leakage current
74ABTH16823A
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5V; V = V
0.01
–2
1
1
µA
µA
I
CC
Data pins
= 5.5V; V = 0
–3
–5
I
= 4.5V; V = 0.8V
35
35
I
5
Bus Hold current inputs
74ABTH16823A
I
= 4.5V; V = 2.0V
–75
–75
µA
HOLD
I
= 5.5V; V = 0 to 5.5V
±800
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V ≤ 4.5V
±5.0
±5.0
±100
±50
±100
±50
µA
µA
OFF
O
I
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
,
O
I
CC
CC
I
PU/PD
4
output current
= Don’t care
I
3-State output High current
3-State output Low current
V
= 5.5V; V = 2.7V; V = V or V
1.0
10
10
µA
µA
OZH
CC
CC
O
I
IL
IH
IH
I
V
= 5.5V; V = 0.5V; V = V or V
–1.0
–10
–10
OZL
O
I
IL
Output High leakage
current
I
V
CC
V
CC
= 5.5V; V = 5.5V; V = GND or V
50
–80
0.5
9.0
0.5
50
–180
1
50
–180
1
µA
mA
mA
mA
mA
CEX
O
I
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–50
O
V
CC
V
CC
= 5.5V; Outputs High, V = GND or
I
I
I
CCH
I
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V = GND or V
19
1
19
1
CCL
I
CC
V
CC
= 5.5V; Outputs 3–State;
CCZ
V = GND or V
I
CC
Additional supply current
per input pin
V
= 5.5V; one input at 3.4V,
CC
∆I
CC
0.2
1
1
mA
2
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
6
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
MAX
T
= –40°C
to +85°C
= +5.0V ±0.5V
amb
T
V
= +25°C
= +5.0V
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
V
CC
MIN
TYP
MIN
MAX
f
Maximum clock frequency
1
1
140
190
140
MHz
ns
MAX
t
t
Propagation delay
nCP to nQx
1.4
1.2
2.3
1.9
3.2
2.6
1.4
1.2
3.7
2.9
PLH
PHL
Propagation delay
nMR to nQx
t
2
2.0
3.3
4.3
2.0
5.0
ns
ns
ns
PHL
t
t
Output enable time
to High and Low level
4
5
1.3
1.2
2.4
2.1
3.2
2.9
1.3
1.2
3.9
3.4
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
1.7
1.6
2.9
2.3
4.0
3.2
1.7
1.6
4.7
3.4
PHZ
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
T
V
= +25°C
= +5.0V
T
V
= –40 to +85°C
= +5.0V ±0.5V
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
MIN
TYP
MIN
t (H)
t (L)
s
Setup time, High or Low
nDx to nCP
2.0
1.5
1.3
0.9
2.0
1.5
s
3
3
1
3
ns
ns
ns
ns
t (H)
Hold time, High or Low
nDx to nCP
1.5
1.5
–0.9
–1.2
1.5
1.5
h
t (L)
h
t (H)
nCP pulse width
High or Low
3.3
3.3
1.7
1.7
3.3
3.3
w
t (L)
w
t (H)
Setup time, High or Low
nCE to nCP
1.5
2.0
0.9
0.9
1.5
2.0
s
t (L)
s
t (H)
t (L)
h
Hold time, High or Low
nCE to nCP
1.5
1.5
–0.8
–0.9
1.5
1.5
h
3
2
2
ns
ns
ns
t (L)
w
nMR pulse width, Low
3.0
2.5
1.7
1.0
3.0
2.5
Recovery time
nMR to nCP
t
rec
7
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
3.0V or V
whichever
is less
CC
1/f
MAX
nOE
3.0V or V
whichever
is less
CC
V
V
M
M
t
nCP
nQx
0V
V
t
V
M
M
t
PHZ
0V
t
(H)
PZH
w
t
PLH
t
(L)
w
V
V
OH
–0.3V
PHL
V
OH
OH
V
M
V
V
nQx
M
M
0V
0V
SH00020
SH00017
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
3.0V or V
CC
whichever
is less
3.0V or V
whichever
is less
CC
V
V
M
M
nOE
nQx
V
V
M
nMR
M
0V
3.0V or V
0V
3.0V or V
whichever
is less
t
t
PLZ
PZL
t
CC
REC
t
(L)
w
whichever
is less
CC
V
V
M
nCP
nQx
M
V
V
+0.3V
OL
OL
0V
t
PHL
V
OH
SH00021
V
M
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
0V
SH00018
Waveform 2. Master Reset Pulse WIdth, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
3.0V or V
CC
whichever
is less
nDx,
nCE
V
V
V
V
V
M
M
M
M
0V
3.0V or V
t (H)
t
(H)
t (L)
t (L)
h
CC
s
h
s
whichever
is less
nCP
V
M
M
0V
SH00019
Waveform 3. Data Setup and Hold Times
8
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
TEST CIRCUIT AND WAVEFORM
V
CC
t
W
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
R
L
M
M
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
SWITCH POSITION
TEST SWITCH
V = 1.5V
M
Input Pulse Definition
t
t
closed
closed
open
PLZ
PZL
All other
DEFINITIONS:
R
C
=
=
Load resistor; see AC CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
L
L
INPUT PULSE REQUIREMENTS
FAMILY
Rep. Rate
t
w
t
R
t
Amplitude
F
R
T
=
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns
2.5ns
74ABT16
3.0V
1MHz
500ns
SH00022
9
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
10
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
11
1998 Feb 27
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset
and enable (3-State)
74ABT16823A
74ABTH16823A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
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Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03502
Document order number:
Philips
Semiconductors
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