74ABT834 [NXP]
Octal inverting transceiver with parity generator/checker 3-State; 八路反相收发器奇偶校验发生器/检验三态
| 型号： | 74ABT834 |
| 厂家： | 
NXP |
| 描述： | Octal inverting transceiver with parity generator/checker 3-State |
| 文件： | 总7页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
power dissipation with high speed and high
output drive.
sent to the input of a storage register. If a
Low–to–High transition happens at the clock
input (CP), the error data is stored in the
register and the Open–collector error flag
(ERROR) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
FEATURES
• Low static and dynamic power dissipation
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for bus–oriented applications.
with high speed and high output drive
• Open–collector ERROR output
• Output capability: +64mA/–32mA
When Output Enable A (OEA) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB) controls the B
outputs in the same way.
• Latch–up protection exceeds 500mA per
If both OEA and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL
STD 883C Method 3015.6 and 200 V per
Machine Model
The parity generator creates an odd parity
output (PARITY) when OEB is Low. When
OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
• Power up/down 3–State
DESCRIPTION
The 74ABT834 high–performance BiCMOS
device combines low static and dynamic
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
3.4
UNIT
ns
T
amb
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
C = 50pF; V = 5V
L
CC
t
t
Propagation delay
An to PARITY
PLH
PHL
C = 50pF; V = 5V
7.4
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
4
7
pF
pF
µA
IN
I
C
V = 0V or V
I CC
OUT
CCZ
I
Outputs disabled; V =5.5V
50
CC
ORDERING INFORMATION
CONDITIONS
= 25°C; GND = 0V
PACKAGES
ORDER CODE
T
amb
24–pin plastic DIP (300mil)
24–pin plastic SOL (300mil)
–40°C to +85°C
–40°C to +85°C
74ABT834N
74ABT834D
PIN CONFIGURATION
LOGIC SYMBOL
OEA
A0
1
2
3
4
5
24
23
22
21
20
V
CC
B0
B1
B2
B3
2
3
4
5
6
7
8
9
A1
A2
A0 A1 A2 A3 A4 A5 A6 A7
OEB
A3
14
1
6
7
8
9
19 B4
18 B5
A4
A5
15
10
PARITY
OEA
CLEAR
CP
11
13
ERROR
A6
A7
17
16
15
14
B6
B0 B1 B2 B3 B4 B5 B6 B7
B7
ERROR 10
CLEAR 11
GND 12
PARITY
OEB
23 22 21 20 19 18 17 16
13 CP
TOP VIEW
1
June 9, 1992
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
2, 3, 4, 5,
6, 7, 8, 9
A0 – A7
A port 3–State inputs/outputs
23, 22, 21, 20,
19, 18, 17, 16
B0 – B7
B port 3–State inputs/outputs
OEA
OEB
1
Enables the A outputs when Low
Enables the B outputs when Low
Parity output
14
15
10
11
13
12
24
PARITY
ERROR
CLEAR
CP
Error output
Clears the error flag register when Low
Clock input
GND
Ground (0V)
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
An
OUTPUTS
Bn
Bn + Parity
Σ of Lows
MODE
OEB
OEA
An
PARITY
Σ of Highs
A data to B bus and generate odd parity
output
Odd
Even
NA
(output)
NA
(input)
H
L
L
H
An
NA
(output)
Odd
Even
NA
(input)
NA
(input)
1
B data to A bus and check for parity error
H
H
L
L
H
L
Bn
Z
2
A bus and B bus disabled
X
X
Z
Z
A data to B bus and generate inverted
parity output
Odd
Even
NA
(output)
NA
(input)
L
H
An
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
CP
Internal node
Point ”P”
Output
Bn + Parity
Σ of Lows
Pre–state
ERRORn–1
ERROR
OUTPUT
MODE
CLEAR
H
H
H
↑
↑
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Sample
Hold
H
L
↑
X
X
X
X
X
X
NC
H
Clear
X
H
L
X
NA
NC
Z
↑
↑
=
=
=
=
=
=
=
=
High voltage level steady state
Low voltage level steady state
Don’t care
Not applicable
No change
High impedance ”off” state
Low–to–High clock transition
Not a Low–to–High clock transition
2
June 9, 1992
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
LOGIC DIAGRAM
8
8
A0 – A7
B0 – B7
8
OEB
OEA
PARITY
8
8
MUX
B
9–bit
Odd
Parity
Tree
}
}
9
”P”
A
Sel A/B
D
R
ERROR
CP
CLEAR
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to abso-
lute–maximum–rated conditions for extended periods may affect device reliability.
2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction tempera-
tures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3
June 9, 1992
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
5.5
V
DC supply voltage
Input voltage
V
V
CC
V
V
CC
I
V
High–level input voltage
Input voltage
2.0
V
IH
V
0.8
5.5
–32
64
V
IL
V
High–level output voltage, ERROR
High–level output current
V
OH
OH
I
mA
mA
ns/V
°C
I
OL
Low–level output current
∆t/∆v
Input transition rise or fall rate
Operating free–air temperature range
0
5
T
amb
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
= 4.5V; I = –18mA
–0.9
–1.2
–1.2
V
IK
CC
IK
High–level output current
ERROR ONLY
I
= 5.5V; V = 5.5V; V = V or V
IH
20
20
µA
OH
CC
OH
I
IL
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
3.5
4.0
2.5
3.0
2.0
V
V
V
V
OH
I
IL
IH
V
High–level output voltage
= 5.0V; I = –3mA; V = V or V
OH I IL
OH
IH
= 4.5V; I = –32mA; V = V or V
IH
2.6
OH
I
IL
V
Low–level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
OL
OL
I
IL
I
I
Input leakage Control pins
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5
±1.0
±1.0
µA
µA
CC
I
current
Data pins
= 5.5V; V = GND or 5.5V
±100
±100
CC
I
I
+ I
+ I
3–State output High current
3–State output Low current
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
IH
5.0
–5.0
–80
50
50
–50
–180
250
30
50
–50
–180
250
30
µA
µA
IH
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
I
= 5.5V; V = 0.5V; V = V or V
O I IL IH
IL
OZL
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–50
mA
µA
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
20
mA
CCL
I
CC
= 5.5V; Outputs 3–State;
I
50
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
CC
0.3
mA
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
4
June 9, 1992
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0V
= +5.0V ±10%
Min
Typ
Min
Max
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
2
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to PARITY
PLH
PHL
1, 2
1, 2
5
t
t
Propagation delay
OEA to PARITY
PLH
PHL
Propagation delay
CLEAR to ERROR
t
PLH
Propagation delay
CP to ERROR
t
1
PHL
PZH
t
Output enable time
OEA to An or OEB to Bn, PARITY
3, 4
3, 4
t
PZL
t
Output disable time
OEA to An or OEB to Bn, PARITY
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
o
o
T
V
= +25 C
= +5.0V
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0V ±10%
Min
Typ
Min
Max
t (H)
t (L)
s
Setup time, High or Low
Bn or PARITY to CP
s
6
6
6
5
5
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Bn or PARITY to CP
h
t (L)
h
t (H)
Pulse width, High or Low
CP
w
t (L)
w
Pulse width, Low
CLEAR
t (L)
w
Recovery time
CLEAR to CP
t
rec
5
June 9, 1992
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
INPUT
INPUT
V
V
V
V
M
M
t
M
M
t
t
t
PHL
PLH
PLH
PHL
V
V
OUTPUT
V
V
OUTPUT
M
M
M
M
Waveform 1. Propagation Delay For Inverting Output
Waveform 2. Propagation Delay For Non–Inverting
Output
V
V
OEA, OEB
V
OEA, OEB
V
M
M
M
t
M
t
t
t
PHZ
PZH
PZL
PLZ
V
–0.3V
0V
OH
V
V
M
OUTPUT
OUTPUT
M
V
+0.3V
0V
OL
Waveform 3. 3–State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 4. 3–State Output Enable Time to Low Level
and Output Disable Time from Low Level
V
V
CLEAR
M
M
t
(L)
t
REC
w
V
V
V
V
Bn, PARITY
M
M
t
M
M
V
CP
M
t
(H)
t
(L)
t
t
(H)
t (L)
h
s
s
h
(H)
(L)
t
w
w
PLH
CP
ERROR
V
V
M
V
V
M
M
M
Waveform 6. Data Setup and Hold Times and
Clock Pulse Width
Waveform 5. CLEAR Pulse Width, CLEAR to ERROR
Delay and CLEAR to Clock Recovery Time
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
6
June 9, 1992
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18
16
14
12
t
PLH
10
8
6
4
t
PHL
2
0
0
100
200
300
400
500
600
Load resistor (Ω)
NOTE:
When using Open–Collector parts, the value of the pull–up resistor greatly affects the value of the t
. For example, changing the
PLH
specified pull–up resistor value from 500Ω to 100Ω will improve the t
over 300% with only a slight change in the t
. However,
PHL
PLH
if the value of the pull–up resistor is changed, the user must make certain that the total I current through the resistor and the total
OL
I ’s of the receivers does not exceed the I maximum specification.
IL
OL
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
CC
90%
90%
V
X
V
V
M
NEGATIVE
PULSE
M
10%
10%
90%
R
R
X
L
0V
(t
V
V
OUT
IN
PULSE
D.U.T
t
t
(t
(t
)
t
TLH
)
GENERATOR
THL
F
R
)
t
(t )
R
T
C
TLH
R
THL F
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3–State Outputs
10%
10%
t
W
0V
SWITCH POSITION
LOAD VALUES
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
OUTPUT
ERROR 100Ω
All other 500Ω 7.0V
R
V
X
X
Input Pulse Definition
t
t
PLZ
PZL
V
CC
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
74ABT
500ns 2.5ns 2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
7
June 9, 1992
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