74ABT841D,623 [NXP]
74ABT841 - 10-bit bus interface latch; 3-state SOP 24-Pin;
| 型号： | 74ABT841D,623 |
| 厂家： | 
NXP |
| 描述： | 74ABT841 - 10-bit bus interface latch; 3-state SOP 24-Pin 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ABT841
10-bit bus interface latch; 3-state
Rev. 4 — 7 November 2011
Product data sheet
1. General description
The 74ABT841 high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT841 bus interface register is designed to provide extra data width for wider
data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-state outputs. The flip-flops appear
transparent to the data when latch enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW
transition, the data that meets the set-up and hold time is latched.
Data appears on the bus when the output enable (OE) is LOW. When OE is HIGH the
output is in the high-impedance state.
2. Features and benefits
High speed parallel latches
Extra data width for wide address/data paths or buses carrying parity
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Broadside pinout
Output capability: +64 mA and 32 mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74ABT841D
74ABT841DB
74ABT841PW
40 C to +85 C SO24
40 C to +85 C SSOP24
40 C to +85 C TSSOP24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
SOT340-1
SOT355-1
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
4. Functional diagram
1
EN
13
C1
2
3
4
5
6
7
8
9
10 11
2
3
23
22
21
20
19
18
17
16
15
14
1D
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
4
13
1
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
5
6
7
23 22 21 20 19 18 17 16 15 14
8
001aae911
9
10
11
001aae912
Fig 1. Logic symbol
Fig 2. IEC logic symbol
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
13
1
LE
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
001aae913
Fig 3. Logic diagram
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
2 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
5. Pinning information
5.1 Pinning
74ABT841
1
2
24
23
22
21
20
19
18
17
16
15
14
13
OE
D0
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
LE
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
11
12
D8
D9
GND
001aae910
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
output enable input (active LOW)
data input
D0 to D9
GND
2, 3, 4, 5, 6, 7, 8, 9,10, 11
12
13
ground (0 V)
LE
latch enable input (active falling edge)
data output
Q0 to Q9
VCC
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
24
positive supply voltage
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
3 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
6. Functional description
Table 3.
Function table[1]
Input
Output
Operating mode
transparent
latched
OE
L
LE
H
H
nD
L
Q0 to Q9
L
L
H
l
H
L
L
L
h
H
Z
H
L
X
X
X
high-impedance
hold
L
NC
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
= HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
1.2
0.5
18
50
-
Max
+7.0
+7.0
+5.5
-
Unit
V
supply voltage
[1]
[1]
input voltage
V
VO
output voltage
output in OFF-state or HIGH-state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
mA
mA
mA
C
C
IOK
IO
VO < 0 V
-
output in LOW-state
128
150
+150
[2]
Tj
junction temperature
storage temperature
-
Tstg
65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
4 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
4.5
0
Typ
Max
5.5
VCC
-
Unit
V
supply voltage
-
-
-
-
-
-
-
-
VI
input voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
2.0
-
V
VIL
0.8
-
V
IOH
32
-
mA
mA
ns/V
C
IOL
64
5
t/V
Tamb
0
in free air
40
+85
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
Conditions
25 C
Typ Max
40 C to +85 C Unit
Min
1.2 0.9
Min
Max
VIK
input clamping voltage
VCC = 4.5 V; IIK = 18 mA
VI = VIL or VIH
-
1.2
-
V
VOH
HIGH-level output
voltage
VCC = 4.5 V; IOH = 3 mA
VCC = 5.0 V; IOH = 3 mA
VCC = 4.5 V; IOH = 32 mA
2.5
3.0
2.0
-
3.5
4.0
2.6
-
-
-
2.5
3.0
2.0
-
-
V
V
V
V
-
-
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
0.42 0.55
0.55
[1]
[2]
[3]
VOL(pu) power-up LOW-level
output voltage
VCC = 5.5 V; IO = 1 mA;
VI = GND or VCC
-
0.13 0.55
-
0.55
V
II
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
control pins
-
-
-
0.01 1.0
-
-
-
1.0 A
100 A
100 A
data pins
5
100
IOFF
power-off leakage
current
VCC = 0 V; VI or VO 4.5 V
5.0 100
IO(pu/pd) power-up/power-down
output current
VCC = 2.0 V; VO = 0.5 V;
VI = GND or VCC; OEn HIGH
-
5.0 50
-
50
A
IOZ
OFF-state output current VCC = 5.5 V; VI = VIL or VIH
VO = 2.7 V
VO = 0.5 V
-
-
-
5.0
5.0 50
5.0 50
50
-
-
-
50
50
50
A
A
A
ILO
IO
output leakage current
output current
HIGH-state; VO = 5.5 V;
VCC = 5.5 V; VI = GND or VCC
VCC = 5.5 V; VO = 2.5 V
180 100 50
180
50
mA
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
5 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
Table 6.
Static characteristics …continued
Symbol Parameter
Conditions
25 C
40 C to +85 C Unit
Min
Typ Max
Min
Max
ICC
supply current
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
outputs LOW-state
-
-
-
-
0.5
25
250
38
-
-
-
-
250
38
A
mA
A
mA
outputs disabled
0.5
0.5
250
1.5
250
1.5
[4]
ICC
additional supply current per input pin; VCC = 5.5 V; one
input at 3.4 V; other inputs at VCC
or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
-
-
4
7
-
-
-
-
-
-
pF
pF
CO
outputs disabled; VO = 0 V or VCC
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V 10 %, a
transition time of up to 100 s is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter Conditions
25 C; VCC = 5.0 V 40 C to +70 C; Unit
VCC = 5.0 V 0.5 V
Min Typ Max
Min
2.1
2.1
2.0
2.8
1.0
Max
6.2
6.5
6.2
6.7
5.3
tPLH
LOW to HIGH
propagation delay
Dn to Qn; see Figure 5
LE to Qn; see Figure 6
Dn to Qn; see Figure 5
LE to Qn; see Figure 6
2.1
2.1
2.0
2.8
1.0
4.1
4.1
4.0
4.6
3.0
5.5
5.9
5.5
6.2
4.5
ns
ns
ns
ns
ns
tPHL
HIGH to LOW
propagation delay
tPZH
tPZL
tPHZ
tPLZ
OFF-state to HIGH OE to Qn; see Figure 7
propagation delay
OFF-state to LOW OE to Qn; see Figure 7
propagation delay
2.2
2.7
2.8
4.1
4.7
4.6
5.6
6.2
6.1
2.2
2.7
2.8
6.3
7.1
6.5
ns
ns
ns
HIGH to OFF-state OE to Qn; see Figure 7
propagation delay
LOW to OFF-state OE to Qn; see Figure 7
propagation delay
tsu(H)
tsu(L)
th(H)
th(L)
tWH
set-up time HIGH
set-up time LOW
hold time HIGH
hold time LOW
Dn to LE; see Figure 8
Dn to LE; see Figure 8
Dn to LE; see Figure 8
Dn to LE; see Figure 8
LE; see Figure 6
2.5
1.5
1.5
1.0
0
-
-
-
-
-
-
2.5
1.5
1.5
1.0
3.3
3.3
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
0.2
+1.0 0.8
pulse width HIGH
pulse width LOW
3.3
3.3
1.9
1.9
tWL
LE; see Figure 6
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
6 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
11. Waveforms
V
I
V
V
M
Dn
Qn
M
GND
t
t
PHL
PLH
V
OH
V
V
M
M
V
OL
001aae916
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay for data to output
V
I
LE
Qn
V
V
V
M
M
M
GND
t
t
WL
WH
t
t
PLH
PHL
V
OH
V
V
M
M
V
OL
001aae914
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay, latch enable input to output and enable pulse width
V
I
OE input
V
M
GND
3.5 V
t
t
PZL
PLZ
output
LOW-to-OFF
OFF-to-LOW
V
M
V
+ 0.3 V
OL
V
V
OL
t
t
PZH
PHZ
V
OH
− 0.3 V
OH
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aal299
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. 3-state output (Qn) enable and disable times
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
7 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
V
I
Dn
V
V
M
V
V
M
M
M
GND
t
t
t
t
h(L)
su(H)
h(H)
su(L)
V
I
V
V
M
LE
M
GND
001aae918
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8. Data set-up and hold times
t
W
V
I
90 %
90 %
negative
pulse
V
EXT
V
V
M
M
V
10 %
10 %
CC
0 V
R
L
V
V
O
t
t
r
I
f
G
DUT
t
t
f
r
V
I
R
T
C
L
R
L
90 %
90 %
positive
pulse
V
M
V
M
mna616
10 %
10 %
0 V
t
W
001aai298
a. Input pulse definition
b. Test circuit
Test data and VEXT levels are given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 9. Test circuit for measuring switching times
Table 8.
Input
VI
Test data
Load
CL
VEXT
fI
tW
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
tPZL, tPLZ
7.0 V
3.0 V
1 MHz
500 ns
2.5 ns
50 pF
500
open
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
8 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 10. Package outline SOT137-1 (SO24)
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
9 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
Fig 11. Package outline SOT340-1 (SSOP24)
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
10 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 12. Package outline SOT355-1 (TSSOP24)
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
11 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
13. Abbreviations
Table 9.
Acronym
BiCMOS
DUT
Abbreviations
Description
Bipolar Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10. Revision history
Document ID
74ABT841 v.4
Modifications:
74ABT841 v.3
74ABT841 v.2
74ABT841
Release date
20111107
Data sheet status
Change notice
Supersedes
Product data sheet
-
74ABT841 v.3
• Legal pages updated.
20100325
20100302
19950906
Product data sheet
-
-
-
74ABT841 v.2
Product data sheet
74ABT841
-
Product specification
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
12 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
13 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT841
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
14 of 15
74ABT841
NXP Semiconductors
10-bit bus interface latch; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 November 2011
Document identifier: 74ABT841
相关型号：
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