74ABT841DB [NXP]
10-bit bus interface latch 3-State; 10位总线接口锁存三态
| 型号： | 74ABT841DB |
| 厂家： | 
NXP |
| 描述： | 10-bit bus interface latch 3-State |
| 文件： | 总6页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
FEATURES
• High speed parallel latches
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
• Extra data width for wide address/data paths or buses carrying
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
parity
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Slim DIP 300 mil package
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
• Broadside pinout
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up reset
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
PLH
PHL
C = 50pF; V = 5V
4.1
4
ns
pF
pF
nA
L
CC
C
Input capacitance
V = 0V or V
I CC
IN
Outputs disabled;
= 0V or V
C
Output capacitance
Total supply current
7
OUT
CCZ
V
O
CC
I
Outputs disabled; V = 5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT841 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT841 N
74ABT841 D
74ABT841 DB
74ABT841 PW
24-Pin plastic SO
74ABT841 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT841 DB
74ABT841PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
V
CC
Output enable input
(active-Low)
1
OE
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D0-D9
Q0-Q9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Data outputs
TOP VIEW
Latch enable input (active
falling edge)
13
LE
12
24
GND
Ground (0V)
V
CC
Positive supply voltage
D8 10
D9 11
15
14
13
Q8
Q9
LE
GND 12
SA00247
1
1995 Sep 06
853-1628 15703
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
LOGIC SYMBOL
FUNCTION TABLE
OPERATING
MODE
INPUTS
OUTPUTS
Q0 – Q9
OE
LE
Dn
L
L
H
H
L
H
L
H
Transparent
Latched
2
3
4
5
6
7
8
9
10 11
L
L
↓
↓
l
h
L
H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
H
L
X
L
X
X
Z
High impedance
Hold
13
1
LE
NC
OE
H
h
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low LE
transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low LE
transition
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
L
l
=
=
↓
=
High-to-Low LE transition
NC= No change
X
Z
=
=
Don’t care
High impedance “off” state
SA00244
LOGIC SYMBOL (IEEE/IEC)
1
EN
13
C1
2
23
22
21
20
19
18
17
16
15
14
1D
3
4
5
6
7
8
9
10
11
SA00245
2
1995 Sep 06
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
D9
11
2
3
4
5
6
7
8
9
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
D
Q
Q
Q
Q
Q
Q
Q
Q
L
Q
L
Q
13
1
LE
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SA00246
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
3
1995 Sep 06
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
3.5
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
4.0
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.6
OH
I
IL
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
Input leakage Control pins
V
CC
V
CC
V
CC
= 5.5V; V = GND or 5.5V
±0.01
±5
±1.0
±100
±100
±1.0
±100
±100
µA
µA
µA
I
I
current
Data pins
= 5.5V; V = GND or 5.5V
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±5.0
OFF
O
I
Power-up/down 3–state
output current
V
CC
V
OE
= 2.0V; V = 0.5V; V = GND or V
;
O
I
CC
I
±5.0
±50
±50
µA
PU/PD
4
= V
CC
I
+ I
+ I
3-State output High current
3-State output Low current
Output high leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
IH
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
OZL
IH
I
= 5.5V; V = 5.5V; V = GND or V
O I
CEX
CC
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
0.5
–180
250
38
–50
–180
250
38
O
I
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
25
CCL
I
CC
= 5.5V; Outputs 3–State;
0.5
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per One input at 3.4V, other inputs at V or
CC
∆I
CC
mA
2
input pin
GND; V = 5.5V
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
t
t
Propagation delay
Dn to Qn
2.1
2.0
4.1
4.0
5.5
5.5
2.1
2.0
6.2
6.2
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
LE to Qn
2.1
2.8
4.1
4.6
5.9
6.2
2.1
2.8
6.5
6.7
PLH
PHL
t
t
Output enable time
to High and Low level
4
5
1.0
2.2
3.0
4.1
4.5
5.6
1.0
2.2
5.3
6.3
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
2.7
2.8
4.7
4.6
6.2
6.1
2.7
2.8
7.1
6.5
PHZ
PLZ
4
1995 Sep 06
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to LE
2.5
1.5
1.0
0.0
2.5
1.5
s
3
3
1
ns
ns
ns
t (H)
Hold time, High or Low
Dn to LE
1.5
1.0
0.2
–0.8
1.5
1.0
h
t (L)
h
t (H)
LE pulse width
High or Low
w
3.3
1.9
3.3
t (L)
w
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
LE
Qn
V
V
V
M
V
V
M
M
OE
Qn
M
M
t
(H)
w
t
t
PHZ
PZH
t
t
PLH
PHL
V
–0.3V
OH
V
M
V
V
M
M
0V
SA00248
SA00066
Waveform 1. Propagation Delay, Latch Enable Input to Output,
and Enable Pulse Width
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
V
V
M
Dn
M
t
V
V
M
t
M
t
t
PZL
PLZ
PLH
PHL
V
Qn
M
V
V
M
Qn
M
V
+0.3V
0V
OL
SA00067
SA00064
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Waveform 2. Propagation Delay for Data to Outputs
V
V
M
V
V
M
Dn
LE
M
M
M
t (H)
s
t (H)
h
t (L)
s
t (L)
h
V
V
M
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00249
Waveform 3. Data Setup and Hold Times
5
1995 Sep 06
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t )
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
6
1995 Sep 06
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