74ABTL3205BB-T [NXP]
IC ABT SERIES, 10-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52, Bus Driver/Transceiver;
| 型号： | 74ABTL3205BB-T |
| 厂家： | 
NXP |
| 描述： | IC ABT SERIES, 10-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52, Bus Driver/Transceiver |
| 文件： | 总14页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABTL3205
10-bit BTL transceiver with registers
Product specification
1995 Jun 16
Philips
Semiconductors
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FEATURES
• 10-bit BTL transceiver
DESCRIPTION
This transceiver is a 10 bit bidirectional transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus.
• Drives heavily loaded backplanes with equivalent load
impedances down to 10 ohms
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good margins by limiting
the switching threshold to a narrow region centered at 1.55V.
• High drive 100mA BTL open collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading (<6pF) by placing an internal series
diode on the drivers. BTL also provides incident wave switching, a
necessity for high performance backplanes.
power consumption
• Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
To support live insertion, OEB is held Low during power on/off cycles
to insure glitch free B port drivers. Proper bias for B port drivers
during live insertion is provided by the BIAS V pin when at a 5V level
bounce
• Tight output skew (0.5nsec typical)
• Glitch-free power up/down operation
while V is Low. The BIAS V pin is a low current input which will
CC
reverse bias the BTL driver series Schottky diode, and also bias the
B port output pins to a voltage between 1.62V and 2.1V. This bias
function is in accordance with IEEE BTL standard 1194.1. If live
insertion is not a requirement, the BIAS V pin should be tied to a
• Low I current
CC
• Supports live insertion
• High density packaging
V
CC
pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
package. The LOGIC V and BUS V pins are also isolated
CC
CC
internally to minimize noise and may be externally decoupled
separately or simply tied together.
This transceiver function is intended to operate in a half-duplex
mode. Low current in standby mode is obtained by powering down
unused circuitry. Likewise, transmit circuitry is powered down when
in receive mode and receive circuitry is powered down while in
transmit mode.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
t
t
Propagation delay
An to Bn
3.3
3.7
PLH
ns
PHL
t
t
Propagation delay
Bn to An
3.6
3.5
PLH
ns
PHL
C
Output capacitance (B0 - B8) only)
Output current (B0 - B8) only)
6
100
1
pF
OB
I
OL
mA
Standby
An to Bn
Bn to An
7
I
Supply current
mA
CC
18
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
52-PIN PQFP
–40°C to +85°C
74ABTL3205 BB
74ABTL3205 BB
SOT379-1
2
1995 Jun 16
853-1802 15352
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
BUS GND
B0
1
2
TTL Gnd
A0
B1
A1
3
BUS GND
B2
TTL GND
A2
4
5
B3
6
A3
TTL GND
AClk2
TTL GND
A4
BUS GND
BClk2
7
8
BUS GND
B4
9
10
11
12
13
B5
A5
BUS GND
B6
TTL GND
A6
14 15 16 17 18 19 20 21 22 23 24 25 26
SA00138
PIN DESCRIPTION
SYMBOL
FUNCTION
ASSERTION
I/O
LOGIC
TTL
OEA1
OEA2
OEB
IEA
Output enable data receiver group 1
Output enable data receiver group 2
Output enable data transmitter
Low
Low
Low
Low
Input
Input
Input
Input
Input
TTL
TTL
Output enable clock and framepulse receiver
TTL
M/S
Master/Slave select:
TTL
L:
H:
Master, enable clock transmitter
Slave, disable clock transmitter
Mode
Input
Input
TTL
TTL
Low:
High:
Data through mode
Registered data mode
Power Up
Power up mode, held low during power up to
disable clock and data transmitters
Low
Recmode
Tranmode
AClk1
Enables receiver
Enables transmitter
Clock or data path
High
High
Input
Input
I/O
TTL
TTL
TTL
TTL
AClkln
I/O
IEA = H → Input for busclock
IEA = L → Output for busclock
A0..A3
AClk2
AFPIn
APAR
A4..A7
BClk1
B0..B3
BClk2
B4..B7
data group 1
I/O
I/O
TTL
TTL
TTL
TTL
TTL
BTL
BTL
BTL
BTL
Clock or data path
Alternate data path
Alternate data path
data group 2
Output
Input
I/O
Clock or data path
data group 1
I/O
I/O
Clock or data path
data group 2
I/O
I/O
3
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC DIAGRAM
ACLKin
I/O
ACLK1
I/O
BCLK1
I/O
ACLK2
I/O
AFP
OUT
APAR
BCLK2
I/O
IN
D
C
Q
B0-B3
I/O
A0-A3
I/O
D
C
Q
B4-B7
I/O
A4-A7
IEA
I/O
D
C
Q
IN
Definition for the MUX:
OEB
M/S
IN
IN
OEA1
IN
OEA2
Low
High
IN
IN
RECMODE
MODE
IN
TRANMODE
POWERUP
IN
IN
SA00139
4
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FUNCTION TABLE
INPUTS
OEA1 OEA2 OEB
MODE
ACLK ACLK ACLK BCLK BCLK
REC
TRAN POWER
An Bn
APAR IEA M/S MODE
in
1
X
X
X
X
2
X
X
X
X
1
X
X
X
X
2
X
X
X
X
MODE MODE
UP
I
O
O
O
O
°
H
H
H
H
H
H
H
H
L
L
L
L
X
X
X
X
H
H
X
X
X
X
X
X
H
H
L
L
L
L
L
H
H
H
H
H
An to Bn
(REGISTERED)
h
L
H
°
H
X
X
H
AN to Bn
(THROUGH)
L
H
B0-B3
to
O
O
O
O
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
X
X
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
L
L
L
L
L
L
L
L
A0-A3
(THROUGH)
B4-B7
to
A4-A7
X
X
H
(THROUGH)
ACLK1
to
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
°
L
H
X
X
O
O
X
X
X
X
X
X
X
X
X
X
L
O
O
X
X
L
X
X
O
O
X
X
L
H
H
X
X
L
X
X
H
H
X
X
L
X
X
H
H
X
X
X
X
L
X
X
X
X
X
X
X
X
I
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
L
X
X
X
X
H
H
H
H
X
X
H
H
L
H
H
H
H
L
H
H
H
H
X
X
X
X
H
H
X
X
H
H
BCLK1
ACLK2
to
BCLK2
L
H
X
X
O
O
X
X
X
X
X
X
L
L
BCLK1
to
ACLK1
X
X
X
X
H
H
X
X
H
H
X
X
X
X
H
H
X
X
H
H
H
X
X
X
X
X
X
L
L
L
BCLK2
to
ACLK2
X
X
X
X
X
X
H
H
L
H
X
X
L
L
L
APAR
to
BCLK2
X
X
X
X
H
H
H
H
L
°
L
h
BCLK2
to
AFPIn
X
X
O
O
X
X
L
X
X
O
O
H
X
X
L
L
BCLK1
to
ACLKin
L
H
H
H
L
L
L
OUTPUTS
ACLK1 ACLK2 BCLK1 BCLK2
MODE
ACLK
in
AF
Pin
An
Bn
Input
Input
Input
Input
H*
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
An to Bn
(REGISTERED)
H*
L
AN to Bn
(THROUGH)
B0-B3
to
H
L
Input
Input
Input
Input
Input
Input
Input
Input
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A0-A3
(THROUGH)
B4-B7
to
A4-A7
H
L
(THROUGH)
ACLK1
to
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Input
Input
X
X
X
H*
L
X
X
X
X
X
X
X
X
X
X
X
X
H*
L
NOTES:
H = High voltage level
BCLK1
ACLK2
to
BCLK2
X
Input
Input
X
X
H*
L
L
h
=
=
Low voltage level
X
X
X
High voltage level one set-up time prior to
Low to High ACLKin transition
Low voltage level one set-up time prior to
Low to High ACLKin transition
Low to High transition
BCLK1
to
ACLK1
X
H
Input
Input
X
X
X
L
X
X
l
=
BCLK2
to
ACLK2
X
X
H
Input
Input
H*
L
X
X
L
X
°
=
=
APAR
to
BCLK2
Input
Input
X
X
X
X
Z
High impedance (off) state
X
X
X
H* = Goes to level of pull-up voltage
Don’t care
O = Output
BCLK2
to
AFPIn
X
X
X
Input
Input
X
X
=
X
X
X
X
BCLK1
to
ACLKin
H
X
X
Input
Input
X
X
L
X
X
X
5
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC SYMBOL (IEEE/IEC)
Recmode
Transmode
Powerup
OEA1
EN1
OEA2
EN2
OEB
EN3
IEA
EN4
M/S
&
EN8
EN5
EN6
MODE
6C7
AClk1
BClk1
B0
1
4
5
3
AClkIn
A0
A1
1
7D
B1
B2
1
1
1
7D
7D
7D
3
3
A2
A3
B3
3
5
AClk2
AFP
BClk2
2
4
APAR
A4
7D
7D
8
3
B4
B5
B6
B7
2
2
2
2
A5
A6
A7
7D
7D
7D
3
3
3
SA00140
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted, these limits are over the operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
V
CC
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–1.2 to +7.0
–1.2 to +5.5
–18 to +5
TTL Signals
BTL Signals
V
V
IN
V
I
IN
mA
/v
V
OUT
Voltage applied to output in High output state
–0.5 to +V
48
CC
A0 - A8
B0 - B8
mA
mA
°C
°C
I
Current applied to output in Low output state
OUT
200
T
amb
Operating free-air temperature range
Storage temperature
–40 to +85
T
STG
–65 to +150
6
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
2
MIN
TYP
V
V
= MAX, V = MAX,
CC
IH
IL
I
I
High level output current
BTL
BTL
0.5
10
100
100
3.4
µA
µA
V
OH
= MIN, V = 1.9V
OH
V
V
= 0.0V, V = MAX,
IL
CC
IH
Power-off output current
OFF
= MIN, V = 1.9V
OH
4
V
V
= MIN, V = MAX,
IL
CC
IH
2.5
2.85
= MIN, I = –3mA
OH
V
OH
High-level output voltage
TTL
4
V
V
= MIN to MAX,
CC
IL
= MAX, V = MIN,
V
CC
– 1.1
V
IH
I
= –10µA
OH
V
V
= MIN, V = MAX,
IL
CC
IH
TTL
BTL
0.35
1.0
0.5
V
V
V
= MIN, I = 24mA
OL
V
V
= MIN, V = MAX,
IL
CC
IH
V
V
Low-level output voltage
Input clamp voltage
0.75
0.5
1.10
OL
= MIN, I = 100mA
OL
V
V
= MIN, V = MAX,
IL
CC
IH
0.7
= MIN, I = 4mA
OL
TTL
BTL
V
V
V
= MIN, I = I
IK
0.8
0.8
–1.2
–1.2
V
V
CC
CC
CC
I
IK
= MIN, I = –18mA
I
Input current at maximum
input voltage
= MAX,
I
I
TTL
TTL
0.1
±50
µΑ
µΑ
V = 0.5V or 5.5V
I
V
CC
= MAX, V = 2.7V,
I
0.1
0.1
20
Bn = AIn = 0V
I
IH
High-level input current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 1.9V
100
µΑ
mA
µΑ
µΑ
µΑ
µΑ
I
BTL
5
= MAX, V = 3.5V
100
–60
I
TTL
BTL
TTL
TTL
= MAX, V = 0.5V
0.1
0.1
0.1
20
–20
–100
50
I
I
IL
Low-level input current
= MAX, V = 0.75V
I
I
I
Off-state output current
Off-state output current
Short-circuit output
= MAX, V = 2.7V
O
OZH
= MAX, V = 0.5V
–50
OZL
O
I
TTL
V
CC
= MAX, V = 0.0V
130
1
–150
3
mA
mA
mA
mA
mA
mA
OS
O
3
current
Recmode Low
Tranmode Low
V
V
= MAX
= MAX
CC
Recmode Low
Tranmode High Mode = Low
CC
7
12
21
25
43
Recmode Low = MAX
Tranmode High Mode = High
V
CC
13
18
29
I
Supply current (total)
CC
Recmode High
Tranmode Low
V
V
= MAX
= MAX
CC
Recmode High
Tranmode High
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Due to test equipment limitations, actual test conditions are V = 1.8V and V = 1.3V for the B side.
IH
IL
5. For B port input voltage between 3 and 5 volts I will be greater than 100µA, but the parts will continue to function normally.
IH
TTL signals CLKin, CLK-1/CLK-OUT, CLK-2/FP-OUT, /FP-IN, /PARITY t,A0..A7, OEB, MASTER/SLAVE, MODE, OEA1, OEA2
BTL signals CLK1BTL, CLK2BTL, B0..B7
7
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LIVE INSERTION SPECIFICATIONS
LIMITS
NOM
SYMBOL
PARAMETER
UNIT
MAX
MIN
V
Bias pin DC current
V
V
= 0 to 5.25V, Bn = 0 to 2.0 V
= 0 to 4.75 V, Bn = 0 to 2.0V,
4.5
5.5
1
V
BIASV
CC
CC
mA
Bias V = 4.5 to 5.5V
I
Bias pin DC current
BIASV
V
CC
= 4.5 to 5.5V, Bn = 0 to 2.0 V,
10
µA
Bias V = 4.5 to 5.5V
Ǹ
Bus voltage during prebias
B0 – B8 = 0V, Bias V = 5.0V
1.62
2.1
V
Bn
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
= +25°C
T
T
amb
= –40°C to +85°C
amb
V
TEST
CONDITION
SYMBOL
PARAMETER
= 5V
V
= 5V ± 10%
UNIT
CC
CC
C = 50pF, C = 500Ω
C = 50pF, C = 500Ω
L
L
L L
MIN
TYP
MAX
MIN
MAX
t
2.0
1.8
3.6
3.5
6.5
6.1
2.0
1.8
Propagation delay
Bn to An
7.3
6.7
PLH
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 1, 2
Waveform 4, 5
ns
ns
ns
ns
ns
ns
ns
t
PHL
t
t
2.0
1.8
3.8
3.6
6.5
6.1
2.0
1.8
7.3
6.7
Propagation delay,
BCLK1 to ACLK1
PLH
PHL
t
t
2.0
1.8
3.7
3.7
6.5
6.1
2.0
1.8
7.3
6.7
Propagation delay
BCLK1 to ACLKin
PLH
PHL
t
t
2.0
1.8
3.7
3.9
6.5
6.1
2.0
1.8
7.3
6.7
Propagation delay
BCLK2 to ACLK2
PLH
PHL
t
t
2.0
1.8
3.8
3.9
6.5
6.1
2.0
1.8
7.3
6.7
Propagation delay
BCLK2 to AFP
PLH
PHL
t
2.0
1.8
3.8
2.5
6.5
6.1
2.0
1.8
7.3
6.7
Output Enable time
OEA1, OEA2, IEA to An
PZH
t
PLZ
t
1.6
2.0
2.5
3.3
5.6
7.8
1.4
1.8
5.7
8.2
Output Disable time
OEA1, OEA2, IEA to An
PHZ
t
PLZ
t
t
3.0
1.7
7.0
4.0
TLH
Output transition time, An Port
10% to 90%, 90% to 10%
Test Circuit and
Waveforms
ns
ns
THL
2
Pulse skew
t
(p)
Waveform 3
2.0
SK
|t
– t
|
PHL
PLH MAX
NOTES:
1. |t actual – t actual| for any data input to output path compared to any other data input to output path where N and M are either LH or
PN
PM
HL. Skew times are valid only under same test conditions (temperature, V , loading, etc.).
CC
2. t (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
SK
duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
8
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
AC ELECTRICAL CHARACTERISTICS
B PORT LIMITS
= +25°C
T
T
amb
= –40°C to +85°C
amb
V
TEST
CONDITION
SYMBOL
PARAMETER
= 5V
V
= 5V ± 10%
UNIT
CC
CC
C
= 30pF, R = 18.5Ω
C = 30pF, R = 18.5Ω
D
U
L U
MIN
TYP
MAX
MIN
MAX
t
1.0
1.0
3.3
2.7
4.7
4.5
1.0
1.0
Propagation delay
An to Bn
PLH
Waveform 2
Waveform 1, 2
Waveform 1, 2
Waveform 2
5.7
ns
ns
ns
ns
ns
ns
t
PHL
t
t
2.0
2.0
4.6
4.5
5.9
5.9
2.0
2.0
6.3
6.3
Propagation delay,
ACLKin to Bn
PLH
PHL
t
t
2.0
2.0
4.6
4.5
7.3
7.3
2.0
2.0
7.6
7.6
Propagation delay
ACLKin to BCLK2
PLH
PHL
t
t
1.0
1.0
3.2
2.9
4.7
4.5
1.0
1.0
5.1
4.7
Propagation delay
ACLK1 to BCLK1
PLH
PHL
t
t
1.0
1.0
3.1
3.1
5.7
5.5
1.0
1.0
6.0
5.6
Propagation delay
ACLK2 to BCLK2
PLH
Waveform 2
PHL
t
t
1.0
1.0
3.8
3.4
6.8
6.4
1.0
1.0
7.6
6.9
Enable/disable time
OEB to Bn or BCLK2
PLH
Waveform 1, 2
PHL
t
t
1.0
0.6
2.5
2.0
1.0
0.6
3.0
2.5
TLH
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
ns
ns
THL
Pulse skew2
t
(p)
Waveform 3
2.0
SK
|t
– t
|
PHL
PLH MAX
NOTES:
1. |t actual – t actual| for any data input to output path compared to any other data input to output path where N and M are either LH or
PN
PM
HL. Skew times are valid only under same test conditions (temperature, V , loading, etc.).
CC
2. t (p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
SK
duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C
T
= –40°C to +85°C
amb
V
amb
V
= 5V
= 5V ± 10%
CC
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF (A side)
R = 500Ω (A side)
L
/
/
C
R
= 30pF (B side)
= 18.5Ω (B side)
L
D
U
MIN
TYP
MIN
MAX
t (H)
t (L)
s
1.9
1.3
2.0
1.5
Setup time
An to ACLKin
s
Waveform 6
Waveform 6
ns
ns
t (H)
1.8
2.0
2.3
2.0
Hold time
An to ACLKin
h
t (L)
h
9
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
AC WAVEFORMS
V
M
= 1.55V for Bn, V = 1.5V for all others
M
V
V
OEA
An
V
V
M
M
M
t
M
t
OEAn
t
PZH
PHZ
t
PLH
PHL
V
–0.3V
0V
OH
V
M
V
V
M
M
An
SA00144
SA00141
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 1. Propagation Delay for Data or
Output Enable to Output
OEA
An
V
V
M
M
V
V
M
t
M
t
An, Bn
Bn, An
t
t
PLZ
PZL
PHL
PLH
V
M
V
+0.3V
OL
V
V
M
M
SA00145
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
SA00142
Waveform 2. Propagation Delay for Data to Output
An
or
Bn
V
V
M
V
V
M
M
M
An, Bn
V
M
t (H)
S
t (H)
h
t (L)
h
t (L)
S
t
(0)
SK
V
V
M
ACLKin
M
An, Bn
V
M
SA00349
SA00143
Waveform 6. Data Setup and Hold Times
Waveform 3. Output Skews
10
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
TEST CIRCUIT AND WAVEFORMS
V
CC
BIAS V
7.0V
R
R
L
L
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
W
AMP (V)
90%
90%
R
T
C
L
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
LOW V
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
Test Circuit for 3-State Outputs on A Port
SWITCH POSITION
)
(t )
F
TLH
R
THL
AMP (V)
90%
M
POSITIVE
PULSE
TEST
, t
SWITCH
closed
open
V
V
M
t
PLZ PZL
10%
10%
t
W
LOW V
All other
V
M
= 1.55V for Bn or Bn, V = 1.5V for all others
M
V
CC
2.0V (for R = 9Ω)
Input Pulse Definition
U
2.1V (for R = 16.5Ω)
U
BIAS V
INPUT PULSE REQUIREMENTS
ABTL
R
U
D
V
V
OUT
IN
Amplitude
Low V
Rep. Rate
t
t
t
THL
W
TLH
PULSE
GENERATOR
D.U.T.
A Port
B Port
3.0V
0.0V
1MHz
500ns 2.5ns 2.5ns
500ns 2.5ns 2.5ns
R
T
C
2.0V
1.0V
1MHz
Test Circuit for Outputs on B Port
DEFINITIONS
R =
L
Load resistor; see AC CHARACTERISTICS for value.
C =
L
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R =
T
Terminationresistance should be equal to Z
generators.
of pulse
OUT
C
R
=
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
D
U
Pull up resistor;
see AC CHARACTERISTICS for value.
SA00146
11
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
12
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
NOTES
13
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 01-00
Document order number:
9397 750 06827
Philips
Semiconductors
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