74AHC164 [NXP]
8-bit serial-in/parallel-out shift register; 8位串行输入/并行输出移位寄存器
| 型号： | 74AHC164 |
| 厂家： | 
NXP |
| 描述： | 8-bit serial-in/parallel-out shift register |
| 文件： | 总20页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift
register
Product specification
2000 Aug 15
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
FEATURES
DESCRIPTION
• ESD protection:
The 74AHC/AHCT164 shift registers are high-speed
silicon-gate CMOS devices and are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
The 74AHC/AHCT164 input signals are 8-bit serial
through one of two inputs (Dsa or Dsb); either input can be
used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an
unused input must be tied HIGH.
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and from −40 to +125 °C.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q0, which
is a logical AND of the two data inputs (Dsa, Dsb) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
CL = 15 pF; VCC = 5 V
UNIT
AHC AHCT
tPHL/tPLH
CP to Qn
4.5
3.4
3.5
3
ns
MR to Qn
4.0
3
ns
CI
input capacitance
maximum clock frequency
power dissipation capacitance
VI = VCC or GND
pF
fmax
CPD
CL = 15 pF; VCC = 5 V
175
48
175
51
MHz
pF
CL = 50 pF; f = 1 MHz; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
2000 Aug 15
2
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
Q0 Q1-Q7
OPERATING MODES
MR
CP
Dsa
Dsb
reset (clear)
shift
L
X
↑
↑
↑
↑
X
l
X
l
L
L
L
L
H
L-L
H
H
H
H
q0-q6
q0-q6
q0-q6
q0-q6
l
h
l
h
h
h
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑ = LOW-to-HIGH transition;
X = don’t care;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
RANGE
74AHC164D
−40 to +125 °C
14
14
14
14
SO
plastic
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT108-1
SOT402-1
74AHC164PW
74AHCT164D
74AHCT164PW
TSSOP
SO
TSSOP
2000 Aug 15
3
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
PINNING
PIN
SYMBOL
DESCRIPTION
1, 2
Dsa, Dsb
Q0 to Q7
GND
CP
data input
outputs
3, 4, 5, 6, 10, 11, 12, 13
7
ground (0 V)
8
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
DC supply voltage
9
MR
14
VCC
3
4
handbook, halfpage
handbook, halfpage
Q
1
0
D
D
1
2
3
4
5
6
7
14
13
12
11
10
9
V
CC
sa
D
D
sa
Q
Q
Q
1
2
3
Q
Q
Q
Q
sb
7
6
5
4
5
sb
2
8
Q
0
1
2
3
6
Q
164
10
11
12
13
Q
Q
Q
Q
4
5
6
7
CP
Q
Q
MR
CP
9
MR
GND
8
MNA596
MNA597
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2000 Aug 15
4
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
handbook, halfpage
SRG8
8
C1/
9
R
handbook, halfpage
1
2
D
1
sa
3
&
1D
2
8
D
4
5
sb
8-BIT SERIAL-IN/PARALLEL-OUT
SHIFT REGISTER
CP
MR
9
6
10
11
12
13
Q
3
Q
4
Q
5
Q
6
Q
Q
Q
Q
6 7
0
1
2
3
4
5
10 11 12 13
MNA598
MNA599
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
D
D
sa
D
Q
D
Q
D
Q
D
Q
D
CP
FF5
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
sb
FF1
FF2
FF3
FF4
FF6
FF7
FF8
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
CP
MR
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
MNA600
Fig.5 Logic diagram.
5
2000 Aug 15
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
RECOMMENDED OPERATING CONDITIONS
74AHC
74AHCT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC
VI
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
input voltage
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient temperature see DC and AC
−40
−40
+25
+25
−40
+25
+25
°C
characteristics per
device
+125 −40
+125 °C
tr, tf
input rise and fall ratios (∆t/∆V) VCC = 3.3 ±0.3 V
VCC = 5 ±0.5 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
ns/V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5 +7.0
−0.5 +7.0
V
input voltage
V
IIK
DC input diode current
VI < −0.5 V; note 1
−
−
−20
±20
mA
mA
IOK
DC output clamping diode
current
−0.5 > VO > VCC + 0.5 V; note 1
IO
DC output sink current
DC VCC or GND current
storage temperature
−0.5 < VO < VCC + 0.5 V
−
±25
±75
mA
mA
ICC
Tstg
PD
−
−65
−
+150 °C
500 mW
power dissipation per package for temperature range: −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly by 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly by 5.5 mW/K.
2000 Aug 15
6
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
DC CHARACTERISTICS
74AHC family
With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
OTHER
VCC (V)
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
V
V
V
V
V
V
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
voltage
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
1.9
2.9
4.4
2.40
IO = −50 µA
−
−
−
−
−
−
VI = VIH or VIL;
−
−
−
IO = −4.0 mA
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
3.70
−
V
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL;
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
−
−
−
−
0.1
0.1
0.1
0.55
V
V
V
V
voltage
IO = 50 µA
VI = VIH or VIL;
IO = 4.0 mA
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
−
−
−
−
−
−
−
3
0.36
0.1
−
−
0.44
1.0
±2.5
40
−
−
−
−
−
0.55
2.0
V
II
input leakage
current
VI = VCC or GND 5.5
µA
IOZ
ICC
CI
3-state output
VI = VIH or VIL; 5.5
OFF-state current VO = VCC or GND
±0.25 −
±10.0 µA
quiescent supply VI = VCC or GND; 5.5
4.0
10
−
−
80
10
µA
current
IO = 0
input capacitance
−
10
pF
2000 Aug 15
7
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
74AHCT family
With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
−
0.8
−
−
0.8
−
V
VOH
HIGH-level output VI = VIH or VIL;
voltage
4.5
4.5
4.5
4.5
5.5
5.5
4.4 4.5
4.4
3.8
−
4.4
3.70
−
V
IO = −50 µA
VI = VIH or VIL;
IO = −8.0 mA
3.94
−
0
−
−
−
−
−
−
V
VOL
LOW-level output VI = VIH or VIL;
voltage
−
−
−
−
0.1
0.36
0.1
0.1
0.44
1.0
±2.5
0.1
0.55
2.0
V
IO = 50 µA
VI = VIH or VIL;
IO = 8.0 mA
−
−
V
II
input leakage
current
VI = VIH or VIL
−
−
µA
IOZ
3-state output
VI = VIH or VIL;
±0.25 −
−
±10.0 µA
OFF-state current VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
−
4.0
−
−
40
−
−
80
µA
∆ICC
additional
VI = VCC − 2.1 V 4.5 to 5.5 −
1.35
1.5
1.5
mA
quiescent supply
current per input
pin
other inputs at
VCC or GND;
IO = 0
CI
input capacitance
−
−
3
10
−
10
−
10
pF
2000 Aug 15
8
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
AC CHARACTERISTICS
Type 74AHC164
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
V
CC = 3.0 to 3.6 V; typical values at VCC = 3.3 V
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 9 15 pF −
6.5 12.8 1.0
5.3 12.8 1.0
15.0 1.0
15.0 1.0
16.0 ns
16.0 ns
tPHL
propagation delay
MR to Qn
see Figs 7 and 9
see Figs 6 and 9
−
fmax
maximum clock pulse
frequency
80
125
−
65
−
50
−
MHz
t
PHL/tPLH propagation delay
see Figs 6 and 9 50 pF −
9.3 16.3 1.0
7.6 16.3 1.0
18.5 1.0
18.5 1.0
20.5 ns
20.5 ns
CP to Qn
tPHL
tW
propagation delay
MR to Qn
see Figs 7 and 9
−
clock pulse width HIGH see Figs 6 and 9
or LOW
5.0
5.0
5.0
1.5
−
−
−
−
−
−
−
−
5.0
5.0
6.0
1.5
−
−
−
−
5.0
5.0
6.0
1.5
−
−
−
−
ns
ns
ns
ns
master reset pulse
width LOW
see Figs 7 and 9
see Figs 8 and 9
see Figs 8 and 9
tsu
th
set-up time
Dsa, Dsb to CP
hold time
Dsa, Dsb to CP
trem
fmax
removal time MR to CP see Figs 7 and 9
2.5
50
−
−
−
2.5
45
−
−
2.5
35
−
−
ns
maximum clock pulse
frequency
see Figs 6 and 9
75
MHz
2000 Aug 15
9
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 9 15 pF −
4.5 9.0
4.0 8.6
1.0
1.0
105
10.5 1.0
10.0 1.0
11.5 ns
11.0 ns
tPHL
propagation delay
MR to Qn
see Figs 7 and 9
−
fmax
maximum clock pulse
frequency
see Figs 6 and 9
125 175
−
−
85
−
MHz
t
PHL/tPLH propagation delay
see Figs 6 and 9 50 pF −
6.4 11.0 1.0
5.8 10.6 1.0
12.5 1.0
12.0 1.0
14.0 ns
13.5 ns
CP to Qn
tPHL
tW
propagation delay
MR to Qn
see Figs 7 and 9
−
clock pulse width HIGH see Figs 6 and 9
or LOW
5.0
5.0
4.5
2.0
−
−
−
−
−
−
−
−
5.0
5.0
4.5
2.0
−
−
−
−
5.0
5.0
4.5
2.0
−
−
−
−
ns
ns
ns
ns
master reset pulse
width LOW
see Figs 7 and 9
see Figs 8 and 9
see Figs 8 and 9
tsu
th
set-up time
Dsa, Dsb to CP
hold time
Dsa, Dsb to CP
trem
fmax
removal time MR to CP see Figs 7 and 9
2.5
85
−
−
−
2.5
75
−
−
2.5
65
−
−
ns
maximum clock pulse
frequency
see Figs 6 and 9
115
MHz
2000 Aug 15
10
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
Type 74AHCT164
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
T
amb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
V
CC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 9
15 pF −
3.4 9.0
3.5 8.6
1.0
1.0
105
10.5 1.0
10.0 1.0
11.5 ns
11.0 ns
tPHL
propagation delay
MR to Qn
see Figs 7 and 9
−
fmax
maximum clock pulse see Figs 6 and 9
frequency
125 175
−
−
85
−
MHz
t
PHL/tPLH propagation delay
see Figs 6 and 9
see Figs 7 and 9
see Figs 6 and 9
see Figs 7 and 9
see Figs 8 and 9
see Figs 8 and 9
see Figs 7 and 9
50 pF −
4.9 11.0 1.0
5.0 10.6 1.0
12.5 1.0
12.0 1.0
14.0 ns
13.5 ns
CP to Qn
tPHL
tW
propagation delay
MR to Qn
−
clock pulse width
HIGH or LOW
5.0
−
−
−
−
−
−
−
5.0
5.0
4.5
2.0
2.5
75
−
−
−
−
−
−
5.0
5.0
4.5
2.0
2.5
65
−
−
−
−
−
−
ns
master reset pulse
width LOW
5.0
4.5
2.0
2.5
85
−
ns
tsu
set-up time
Dsa, Dsb to CP
−
ns
th
hold time
Dsa, Dsb to CP
−
ns
trem
fmax
removal time
MR to CP
−
ns
maximum clock pulse see Figs 6 and 9
frequency
115
MHz
2000 Aug 15
11
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
AC WAVEFORMS
1/f max
V
i
(1)
CP input
V
M
t
GND
t
t
PLH
W
PHL
V
OH
(2)
Q
output
V
n
M
MNA601
V
OL
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
AHC
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
AHCT
Fig.6 The clock (CP) to output (Qn) propagation delays, the shift clock pulse width (tW) and maximum shift clock
frequency (fmax).
V
i
(1)
V
MR input
GND
M
t
W
t
rem
V
i
(1)
V
CP input
M
GND
t
PHL
V
OH
(2)
V
Q
output
M
n
MNA603
V
OL
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
Fig.7 The master reset (MR) pulse width, the master reset to output (Qn), propagation delays and the master
reset clock (CP) removal time (trem).
2000 Aug 15
12
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
V
i
(1)
CP input
V
M
GND
t
t
su
su
t
t
h
h
V
i
(1)
D
input
V
M
n
GND
V
OH
(2)
Q
output
V
n
M
V
OL
MNA602
(1)
(2)
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
AHC
GND to VCC 50% VCC 50% VCC
GND to 3.0 V 1.5 V 50% VCC
The shaded areas indicate when the input is permitted to change for
predictable output performance.
AHCT
Fig.8 The data set-up (tsu) and hold (th) times for the (Dn) input.
S1
V
CC
open
V
CC
GND
1000 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
R
L
T
MNA219
TEST
S1
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
open
VCC
Definitions for test circuit.
CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
GND
Fig.9 Load circuit for switching times.
13
2000 Aug 15
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.050
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT108-1
076E06
MS-012
2000 Aug 15
14
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-04-04
99-12-27
SOT402-1
MO-153
2000 Aug 15
15
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Aug 15
16
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
REFLOW(1)
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
not suitable
suitable
suitable
suitable
suitable
suitable
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Aug 15
17
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Aug 15
18
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
NOTES
2000 Aug 15
19
Philips Semiconductors – a worldwide company
Argentina: see South America
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Slovenia: see Italy
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Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
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ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
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TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
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MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
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Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
70
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/01/pp20
Date of release: 2000 Aug 15
Document order number: 9397 750 07332
相关型号：
74AHC164D14
Serial In Parallel Out, AHC/VHC/H/U/V Series, 8-Bit, Right Direction, True Output, CMOS, PDIP14, GREEN, PLASTIC, DIP-14
DIODES
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