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74AHC1GU04GV-Q100 [NXP]

AHC/VHC/H/U/V SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SC-74A, SOT-753, 5 PIN;
74AHC1GU04GV-Q100
型号： 74AHC1GU04GV-Q100
厂家： NXP    NXP
描述：

AHC/VHC/H/U/V SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SC-74A, SOT-753, 5 PIN

输入元件 光电二极管
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74AHC1GU04-Q100  
Inverter  
Rev. 1 — 21 November 2012  
Product data sheet  
1. General description  
The 74AHC1GU04-Q100 is a high-speed Si-gate CMOS device. It provides an inverting  
single stage function.  
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Symmetrical output impedance  
High noise immunity  
Low power dissipation  
Balanced propagation delays  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74AHC1GU04GW-Q100 40 C to +125 C  
TSSOP5  
plastic thin shrink small outline package;  
5 leads; body width 1.25 mm  
SOT353-1  
74AHC1GU04GV-Q100 40 C to +125 C  
SC-74A  
plastic surface-mounted package; 5 leads  
SOT753  
4. Marking  
Table 2.  
Marking codes  
Type number  
Marking  
AD  
74AHC1GU04GW-Q100  
74AHC1GU04GV-Q100  
AU4  
 
 
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
5. Functional diagram  
A
Y
1
4
2
2
4
A
Y
mna043  
mna044  
mna045  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
Fig 3. Logic diagram  
6. Pinning information  
6.1 Pinning  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢁꢉꢊꢅꢈꢈ  
ꢊ
ꢋ
ꢌ
ꢍ
ꢀꢁꢂꢁ  
ꢅ
ꢃ
ꢉ
ꢄꢄ  
ꢎ
ꢆꢇꢈ  
ꢀꢀꢀꢁꢂꢂꢃꢃꢄꢅ  
Fig 4. Pin configuration  
6.2 Pin description  
Table 3.  
Symbol  
n.c.  
Pin description  
Pin  
Description  
not connected  
data input  
1
2
3
4
5
A
GND  
Y
ground (0 V)  
data output  
VCC  
supply voltage  
7. Functional description  
Table 4.  
Function table  
H = HIGH voltage level; L = LOW voltage level  
Input  
Output  
A
L
Y
H
L
H
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
2 of 13  
 
 
 
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
20  
0.5  
-
Max  
+7.0  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0.5 V  
mA  
V
[1]  
VI  
+7.0  
20  
25  
75  
IOK  
output clamping current  
output current  
VO < 0.5 V or VO > VCC + 0.5 V  
0.5 V < VO < VCC + 0.5 V  
mA  
mA  
mA  
mA  
C  
IO  
-
ICC  
supply current  
-
IGND  
Tstg  
Ptot  
ground current  
75  
65  
-
-
storage temperature  
total power dissipation  
+150  
250  
[2]  
Tamb = 40 C to +125 C  
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] For both TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.  
9. Recommended operating conditions  
Table 6.  
Recommended operating conditions  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter Conditions  
Min  
2.0  
0
Typ  
Max  
Unit  
VCC  
VI  
supply voltage  
5.0  
5.5  
V
input voltage  
-
5.5  
V
VO  
output voltage  
0
-
VCC  
+125  
100  
20  
V
Tamb  
t/V  
ambient temperature  
input transition rise and fall rate VCC = 3.3 V 0.3 V  
VCC = 5.0 V 0.5 V  
40  
-
+25  
C  
ns/V  
ns/V  
-
-
-
10. Static characteristics  
Table 7.  
Static characteristics  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
25 C  
40 C to +85 C 40 C to +125 C Unit  
Min Max Min Max  
1.7 1.7  
Min Typ Max  
VIH  
HIGH-level  
VCC = 2.0 V  
VCC = 3.0 V  
VCC = 5.5 V  
VCC = 2.0 V  
VCC = 3.0 V  
VCC = 5.5 V  
1.7  
2.4  
4.4  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
input voltage  
-
2.4  
2.4  
-
4.4  
4.4  
VIL  
LOW-level  
0.3  
0.6  
1.1  
-
-
-
0.3  
0.6  
1.1  
-
-
-
0.3  
0.6  
1.1  
input voltage  
-
-
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
3 of 13  
 
 
 
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
Table 7.  
Static characteristics …continued  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
25 C  
40 C to +85 C 40 C to +125 C Unit  
Min Typ Max  
Min  
Max  
Min  
Max  
VOH  
HIGH-level  
VI = VIH or VIL  
output voltage  
IO = 50 A; VCC = 2.0 V 1.9  
IO = 50 A; VCC = 3.0 V 2.9  
IO = 50 A; VCC = 4.5 V 4.4  
IO = 4.0 mA; VCC = 3.0 V 2.58  
IO = 8.0 mA; VCC = 4.5 V 3.94  
VI = VIH or VIL  
2.0  
3.0  
4.5  
-
-
-
-
-
-
1.9  
-
-
-
-
-
1.9  
-
-
-
-
-
V
V
V
V
V
2.9  
4.4  
2.48  
3.8  
2.9  
4.4  
2.40  
3.70  
-
VOL  
LOW-level  
output voltage  
IO = 50 A; VCC = 2.0 V  
IO = 50 A; VCC = 3.0 V  
IO = 50 A; VCC = 4.5 V  
IO = 4.0 mA; VCC = 3.0 V  
IO = 8.0 mA; VCC = 4.5 V  
-
-
-
-
-
0
0
0
-
0.1  
-
-
-
-
-
-
0.1  
-
-
-
-
-
-
0.1  
V
0.1  
0.1  
0.1  
V
0.1  
0.1  
0.1  
V
0.36  
0.36  
0.1  
0.44  
0.44  
1.0  
0.55  
0.55  
2.0  
V
-
V
II  
input leakage VI = 5.5 V or GND;  
current VCC = 0 V to 5.5 V  
- -  
A  
ICC  
CI  
supply current VI = VCC or GND; IO = 0 A;  
VCC = 5.5 V  
- -  
1.0  
10  
-
-
10  
10  
-
-
40  
10  
A  
input  
- 1.5  
pF  
capacitance  
11. Dynamic characteristics  
Table 8.  
Dynamic characteristics  
GND = 0 V; tr = tf = 3.0 ns. For test circuit see Figure 6.  
Symbol Parameter  
Conditions  
25 C  
Min Typ Max  
40 C to +85 C 40 C to +125 C Unit  
Min Max Min Max  
[1]  
[2]  
tpd  
propagation  
delay  
A to Y; see Figure 5  
VCC = 3.0 V to 3.6 V  
CL = 15 pF  
-
-
3.4  
4.9  
7.1  
1.0  
8.5  
1.0  
10.0  
ns  
ns  
CL = 50 pF  
10.6 1.0  
12.0  
1.0  
13.5  
[3]  
[4]  
VCC = 4.5 V to 5.5 V  
CL = 15 pF  
-
-
-
2.6  
3.6  
14  
5.5  
7.0  
-
1.0  
1.0  
6.0  
8.0  
1.0  
1.0  
7.0  
9.0  
ns  
ns  
pF  
CL = 50 pF  
CPD  
power  
per buffer;  
-
-
-
-
dissipation  
capacitance  
VI = GND to VCC  
[1] tpd is the same as tPLH and tPHL  
.
[2] Typical values are measured at VCC = 3.3 V.  
[3] Typical values are measured at VCC = 5.0 V.  
[4] CPD is used to determine the dynamic power dissipation PD (W).  
PD = CPD VCC2 fi + (CL VCC2 fo) where:  
fi = input frequency in MHz;  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
4 of 13  
 
 
 
 
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts.  
12. Waveforms  
(1)  
V
A input  
M
V
CC  
V
V
O
I
t
t
PULSE  
GENERATOR  
PHL  
PLH  
DUT  
C
50 pF  
L
R
T
(1)  
Y output  
V
M
mna046  
mna034  
VM = 0.5 VCC; VI = GND to VCC  
.
Test data is given in Table 8.  
Definitions for test circuit:  
CL = Load capacitance including jig and probe  
capacitance.  
RT = Termination resistance should be equal to output  
impedance Zo of the pulse generator.  
Fig 5. The input (A) to output (Y) propagation delay  
times  
Fig 6. Load circuitry for switching times  
13. Typical transfer characteristics  
mna397  
mna398  
2.0  
O
1.0  
10  
3.0  
V
V
O
V
O
I
CC  
I
CC  
V
(V)  
1.6  
O
(mA)  
0.8  
(mA)  
(V)  
8
6
4
2
0
1.2  
0.8  
0.4  
0
0.6  
0.4  
0.2  
0
1.5  
I
(drain current)  
D
I
(drain current)  
D
0
0
1
2
3
0.4  
0.8  
1.2  
1.6  
2.0  
0
V (V)  
I
V (V)  
I
Fig 7. VCC = 2.0 V; IO = 0 A  
Fig 8. VCC = 3.0 V; IO = 0 A  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
5 of 13  
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
mna399  
6
50  
I
CC  
V
O
(mA)  
40  
V
O
R
bias  
= 560 kΩ  
(V)  
V
CC  
30  
20  
10  
0
3
0.47 μF  
100 μF  
input  
output  
V
I
A
I
I
(drain current)  
O
D
4
(f = 1 kHz)  
GND  
mna050  
0
0
2
6
V (V)  
I
Fig 9. VCC = 5.5 V; IO = 0 A  
Fig 10. Test set-up for measuring forward  
transconductance gfs = IO/VI at VO is  
constant  
mna400  
40  
g
fs  
(mA/V)  
30  
20  
10  
0
0
2
4
6
V
(V)  
CC  
Fig 11. Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 C  
14. Application information  
Some applications are:  
• Linear amplifier (see Figure 12)  
• In crystal oscillator design (see Figure 13)  
Remark: All values given are typical unless otherwise specified.  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
6 of 13  
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
R2  
R1  
V
CC  
R2  
1 μF  
R1  
U04  
U04  
C1  
C2  
Z
L
out  
mna052  
mna053  
Maximum Vo(p-p) = VCC 1.5 V centered at 0.5 VCC  
.
C1 = 47 pF (typical)  
C2 = 22 pF (typical)  
Gol  
---------------------------------------  
1 +  
Gv = –  
R1 = 1 Mto 10 M(typical)  
R1  
------  
1 + Gol  
R2 optimum value depends on the frequency and  
required stability against changes in VCC or average  
minimum ICC (ICC is typically 2 mA at VCC = 3 V and  
f = 1 MHz).  
R2  
G
ol = open loop gain  
Gv = voltage gain  
R1 3 k, R2 1 M  
ZL > 10 k; Gol = 20 (typical)  
Typical unity gain bandwidth product is 5 MHz.  
Fig 12. Used as a linear amplifier  
Fig 13. Crystal oscillator configuration  
Table 9.  
External components for resonator (f < 1 MHz)  
All values given are typical and must be used as an initial set-up.  
Frequency  
R1  
R2  
C1  
C2  
10 kHz to 15.9 kHz  
16 kHz to 24.9 kHz  
25 kHz to 54.9 kHz  
55 kHz to 129.9 kHz  
130 kHz to 199.9 kHz  
200 kHz to 349.9 kHz  
350 kHz to 600 kHz  
22 M  
22 M  
22 M  
22 M  
22 M  
22 M  
22 M  
220 k  
220 k  
100 k  
100 k  
47 k  
47 k  
47 k  
56 pF  
56 pF  
56 pF  
47 pF  
47 pF  
47 pF  
47 pF  
20 pF  
10 pF  
10 pF  
5 pF  
5 pF  
5 pF  
5 pF  
Table 10. Optimum value for R2  
Frequency  
R2  
Optimum for  
minimum required ICC  
3 kHz  
2.0 k  
8.0 k  
1.0 k  
4.7 k  
0.5 k  
2.0 k  
0.5 k  
1.0 k  
-
minimum influence due to change in VCC  
minimum required ICC  
6 kHz  
minimum influence by VCC  
minimum required ICC  
10 kHz  
14 kHz  
>14 kHz  
minimum influence by VCC  
minimum required ICC  
minimum influence by VCC  
replace R2 by C3 with a typical value of 35 pF  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
7 of 13  
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
15. Package outline  
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm  
SOT353-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )  
3
A
1
θ
L
L
p
1
3
e
w M  
b
p
detail X  
e
1
0
1.5  
3 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
E
max.  
0.1  
0
1.0  
0.8  
0.30  
0.15  
0.25  
0.08  
2.25  
1.85  
1.35  
1.15  
2.25  
2.0  
0.46  
0.21  
0.60  
0.15  
7°  
0°  
mm  
1.1  
0.65  
1.3  
0.15  
0.425  
0.3  
0.1  
0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-09-01  
03-02-19  
SOT353-1  
MO-203  
SC-88A  
Fig 14. Package outline SOT353-1 (TSSOP5)  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
8 of 13  
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
Plastic surface-mounted package; 5 leads  
SOT753  
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
1
2
3
p
detail X  
e
b
p
w
M B  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
02-04-16  
06-03-16  
SOT753  
SC-74A  
Fig 15. Package outline SOT753 (SC-74A)  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
9 of 13  
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
16. Abbreviations  
Table 11. Abbreviations  
Acronym  
CMOS  
CDM  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Charged Device Model  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
Military  
HBM  
MIL  
MM  
Machine Model  
17. Revision history  
Table 12. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
74AHC1GU04_Q100 v.1 20121121  
Product data sheet  
-
-
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
10 of 13  
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
18. Legal information  
18.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use in automotive applications — This NXP  
18.2 Definitions  
Semiconductors product has been qualified for use in automotive  
applications. Unless otherwise agreed in writing, the product is not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
18.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
11 of 13  
 
 
 
 
74AHC1GU04-Q100  
NXP Semiconductors  
Inverter  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
18.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
19. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74AHC1GU04_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 1 — 21 November 2012  
12 of 13  
 
 
NXP Semiconductors  
74AHC1GU04-Q100  
Inverter  
20. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 1  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2  
7
Functional description . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Recommended operating conditions. . . . . . . . 3  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 3  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 4  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Typical transfer characteristics . . . . . . . . . . . . 5  
Application information. . . . . . . . . . . . . . . . . . . 6  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
18.1  
18.2  
18.3  
18.4  
19  
20  
Contact information. . . . . . . . . . . . . . . . . . . . . 12  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2012.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 21 November 2012  
Document identifier: 74AHC1GU04_Q100  
 

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