74AHC74BQ [NXP]
Dual D-type flip-flop with set and reset; positive-edge trigger; 双D- FL型IP- FL运算与置位和复位;正边沿触发
| 型号： | 74AHC74BQ |
| 厂家： | 
NXP |
| 描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 文件： | 总18页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 05 — 9 June 2008
Product data sheet
1. General description
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Input levels:
N For 74AHC74: CMOS level
N For 74AHCT74: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC74
74AHC74D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74AHC74PW
74AHC74BQ
TSSOP14
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
74AHCT74
74AHCT74D
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74AHCT74PW −40 °C to +125 °C
74AHCT74BQ −40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
4. Functional diagram
4
10
1SD 2SD
SD
1Q
2Q
5
9
2
12
3
1D
2D
1CP
2CP
D
Q
Q
CP
11
FF
1Q
2Q
6
8
RD
1RD 2RD
1 13
mna418
Fig 1. Functional diagram
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
2 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
1SD
4
SD
1Q
1Q
1D
2
3
Q
Q
D
5
6
1CP
CP
FF
RD
4
S
5
6
1RD
2SD
3
2
1
1
C1
1D
R
10
SD
2Q
2Q
2D
9
8
12
11
D
Q
Q
10
11
12
13
S
9
8
2CP
CP
C1
FF
1D
R
RD
2RD
mna420
mna419
13
Fig 2. Logic symbol
Fig 3. IEC logic symbol
Q
C
C
C
C
C
C
D
Q
C
C
RD
SD
CP
mna421
C
C
Fig 4. Logic diagram (one flip-flop)
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
3 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1D
1CP
1SD
1Q
2RD
2D
1
2
3
4
5
6
7
14
13
12
11
10
9
1RD
1D
V
CC
2RD
2D
74
2CP
2SD
2Q
1CP
1SD
1Q
(1)
GND
74
2CP
2SD
2Q
1Q
1Q
001aac450
GND
8
2Q
Transparent top view
001aac449
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used
as supply pin or input.
Fig 5. Pin configuration SO14 and TSSOP14
Fig 6. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
Pin description
Pin
1
Description
asynchronous reset direct input (active LOW)
data input
2
1CP
1SD
1Q
3
clock input (LOW to HIGH, edge-triggered)
asynchronous set direct input (active LOW)
true flip-flop output
4
5
1Q
6
complement flip-flop output
ground (0 V)
GND
2Q
7
8
complement flip-flop output
true flip-flop output
2Q
9
2SD
2CP
2D
10
11
12
13
14
asynchronous set direct input (active LOW)
clock input (LOW to HIGH, edge-triggered)
data input
2RD
VCC
asynchronous reset direct input (active LOW)
supply voltage
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
4 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3.
Function table[1]
Control
Input
Output
nSD
L
nRD
H
nCP
X
nD
X
nQ
H
L
nQ
L
nQn+1
nQn+1
L
H
-
H
L
-
H
L
X
X
H
H
-
L
L
X
X
H
-
H
H
↑
L
L
H
H
L
H
H
↑
H
-
-
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW to HIGH transition;
Qn+1 = state after the next LOW to HIGH CP transition;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
IO
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
5 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
8. Recommended operating conditions
Table 5.
Operating conditions
Symbol Parameter
74AHC74
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
5.5
V
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
°C
ns/V
ns/V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT74
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
-
+25
-
°C
ns/V
VCC = 4.5 V to 5.5 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ
−40 °C to +85 °C −40 °C to +125 °C Unit
Max
Min
Max
Min
Max
74AHC74
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
output voltage
VI = VIH or VIL
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
1.9
2.9
4.4
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
IO = −4.0 mA; VCC = 3.0 V 2.58
IO = −8.0 mA; VCC = 4.5 V 3.94
VI = VIH or VIL
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.44
0.44
0.55
0.55
-
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
6 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ
Max
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
-
-
-
0.1
-
1.0
-
2.0
µA
µA
pF
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
2.0
10
-
-
20
10
-
-
40
10
V
input
VI = VCC or GND
3
capacitance
74AHCT74
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
2.0
-
-
20
-
-
40
µA
V
additional
per input pin;
1.35
1.5
1.5
mA
supply current VI = VCC − 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
CI
input
VI = VCC or GND
-
3
10
-
10
-
10
pF
capacitance
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
7 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
74AHC74
25 °C
Min Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
[2]
tpd
propagation nCP to nQ, nQ; see Figure 7
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.2 11.9
7.4 15.4
1.0
1.0
14.0
17.5
1.0
1.0
15.0
19.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.7
5.2
7.3
9.3
1.0
1.0
8.5
1.0
1.0
9.5
ns
ns
CL = 50 pF
10.5
12.0
nSD, nRD to nQ, nQ;
see Figure 8
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.4 12.3
7.7 15.8
1.0
1.0
14.5
18.0
1.0
1.0
15.5
20.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.7
5.3
7.7
9.7
1.0
1.0
9.0
1.0
1.0
10.0
12.5
ns
ns
CL = 50 pF
11.0
fmax
maximum
frequency
see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
80
50
125
75
-
-
45
70
-
-
45
70
-
-
MHz
MHz
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
130 170
-
-
110
75
-
-
110
75
-
-
MHz
MHz
CL = 50 pF
90
115
tW
pulse width CP HIGH or LOW;
nSD, nRD LOW;
see Figure 7 and 8
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
6.0
5.0
-
-
-
-
7.0
5.0
-
-
7.0
5.0
-
-
ns
ns
tsu
set-up time nD to nCP; see Figure 7
VCC = 3.0 V to 3.6 V
6.0
5.0
-
-
-
-
7.0
5.0
-
-
7.0
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
th
hold time
nD to nCP; see Figure 7
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nRD to nCP; see Figure 8
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.5
0.5
-
-
-
-
0.5
0.5
-
-
0.5
0.5
-
-
ns
ns
trec
recovery
time
5.0
3.0
-
-
-
-
5.0
3.0
-
-
5.0
3.0
-
-
ns
ns
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
8 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
[3]
[2]
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
-
12
-
-
-
-
-
pF
74AHCT74; VCC = 4.5 V to 5.5 V
tpd
propagation nCP to nQ, nQ; see Figure 7
delay
CL = 15 pF
CL = 50 pF
-
-
3.3
4.8
7.8
8.8
1.0
1.0
9.0
1.0
1.0
10.0
11.0
ns
ns
10.0
nSD, nRD to nQ, nQ;
see Figure 7
CL = 15 pF
CL = 50 pF
see Figure 7
CL = 15 pF
CL = 50 pF
-
-
3.7 10.4
5.3 11.4
1.0
1.0
12.0
13.0
1.0
1.0
13.0
14.5
ns
ns
fmax
maximum
frequency
100 160
-
-
-
80
65
-
-
-
80
65
-
-
-
MHz
MHz
ns
80
140
-
tW
pulse width CP HIGH or LOW;
nSD, nRD LOW;
5.0
5.0
5.0
see Figure 7 and 8
tsu
th
set-up time nD to nCP; see Figure 7
5.0
0
-
-
-
-
-
-
5.0
0
-
-
-
5.0
0
-
-
-
ns
ns
ns
hold time
nD to nCP; see Figure 7
nRD to nCP; see Figure 8
trec
recovery
time
3.5
3.5
3.5
[3]
CPD
power
fi = 1 MHz; VI = GND to VCC
-
16
-
-
-
-
-
pF
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
9 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
11. Waveforms
V
I
V
nD input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
V
nCP input
M
GND
t
W
t
t
PLH
PHL
V
OH
V
nQ output
nQ output
M
V
OL
V
OH
V
M
V
OL
mna422
t
t
PHL
PLH
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
10 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
V
I
V
M
nCP input
GND
t
rec
V
I
V
M
nSD input
nRD input
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
nQ output
nQ output
V
V
M
V
OL
V
OH
M
V
OL
t
t
PLH
mna423
PHL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 8. Set and reset pulse widths, recovery time and input to output propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
74AHC74
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
74AHCT74
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
11 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
For test data see Table 9.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9. Load circuitry for switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74AHC74
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
50 pF, 15 pF
50 pF, 15 pF
tPLH, tPHL
tPLH, tPHL
74AHCT74
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
12 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
13 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 11. Package outline SOT402-1 (TSSOP14)
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
14 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 12. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
15 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
ESD
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
14. Revision history
Table 11. Revision history
Document ID
Release date
20080609
Data sheet status
Change notice
Supersedes
74AHC_AHCT74_5
Modifications:
Product data sheet
-
74AHC_AHCT74_4
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT74_4
74AHC_AHCT74_3
74AHC_AHCT74_2
74AHC_AHCT74_1
20050207
20040429
19990923
19990805
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
74AHC_AHCT74_3
74AHC_AHCT74_2
74AHC_AHCT74_1
-
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
16 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
17 of 18
74AHC74; 74AHCT74
NXP Semiconductors
Dual D-type flip-flop with set and reset; positive-edge trigger
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 June 2008
Document identifier: 74AHC_AHCT74_5
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