74AHC86 [NXP]
Quad 2-input EXCLUSIVE-OR gate; 四2输入异或门
| 型号： | 74AHC86 |
| 厂家： | 
NXP |
| 描述： | Quad 2-input EXCLUSIVE-OR gate |
| 文件： | 总16页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Product specification
1999 Sep 17
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
FEATURES
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
AHC
3.4
AHCT
3.4
tPHL/tPLH propagation delay CL = 15 pF;
nA, nB to nY VCC = 5 V
ns
CI
input capacitance VI = VCC or GND
output capacitance VI = VCC or GND
3.0
4.0
10
3.0
4.0
12
pF
pF
pF
• Inputs accepts voltages higher than
VCC
CO
CPD
power dissipation
capacitance
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
• Specified from −40 to +85 °C and
−40 to +125 °C.
DESCRIPTION
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
The 74AHC/AHCT86 are high-speed
Si-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
FUNCTION TABLE
The 74AHC/AHCT86 provides the
2-input EXCLUSIVE-OR function.
See note 1.
INPUT
nA
OUTPUT
nY
nB
L
L
L
H
L
L
H
H
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
OUTSIDE NORTH
PACKAGES
NORTH AMERICA
AMERICA
PINS
PACKAGE
MATERIAL
CODE
74AHC86D
74AHC86D
14
14
14
14
SO
plastic
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT108-1
SOT402-1
74AHC86PW
74AHCT86D
74AHCT86PW
74AHC86PW DH
74AHCT86D
TSSOP
SO
74AHCT86PW DH
TSSOP
1999 Sep 17
2
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
PINNING
PIN
SYMBOL
1A to 4A
DESCRIPTION
1, 4, 9 and 12
data inputs
2, 5, 10 and 13
1B to 4B
1Y to 4Y
GND
data inputs
3, 6, 8 and 11
data outputs
ground (0 V)
DC supply voltage
7
14
VCC
handbook, halfpage
1
2
handbook, halfpage
1A
1B
1Y
2Y
3Y
3
6
8
1A
1B
1
2
3
4
5
6
7
V
CC
14
13
12
4B
4A
4Y
3B
3A
3Y
4
5
2A
2B
1Y
2A
11
86
9
3A
3B
2B
10
10
2Y
9
8
12
13
4A
4B
4Y 11
GND
MNA455
MNA456
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1
handbook, halfpage
= 1
= 1
= 1
= 1
3
6
2
4
5
handbook, halfpage
A
Y
9
8
10
B
MNA458
12
13
11
MNA457
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one gate).
1999 Sep 17
3
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
RECOMMENDED OPERATING CONDITIONS
74AHC
74AHCT
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. MIN. TYP. MAX.
VCC
VI
DC supply voltage
input voltage
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient
temperature
see DC and AC
characteristics per device
−40
−40
−
+25
+25
−
−40
+25
+25
−
°C
+125 −40
+125 °C
tr,tf (∆t/∆f) input rise and fall
times except for
VCC = 3.3 ±0.3 V
100
20
−
−
−
ns/V
VCC = 5 ±0.5 V
−
−
−
20
Schmitt trigger inputs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5
−0.5
−
+7.0
+7.0
−20
±20
±25
±75
V
input voltage
V
IIK
DC input diode current
DC output diode current
DC output source or sink current
DC VCC or GND current
storage temperature
VI < −0.5 V; note 1
mA
mA
mA
mA
IOK
IO
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−0.5 V < VO < VCC + 0.5 V
−
−
ICC
Tstg
PD
−
−65
−
+150 °C
500 mW
power dissipation per package
for temperature range: −40 to +125 °C;
note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 17
4
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
DC CHARACTERISTICS
Family 74AHC
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
OTHER
VCC (V)
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
voltage; all
outputs
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
1.9
2.9
4.4
2.40
IO = −50 µA
−
−
−
−
−
−
HIGH-level output VI = VIH or VIL;
−
−
−
voltage
IO = −4.0 mA
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
3.70
−
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL;
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
−
−
−
−
0.1
0.1
0.1
0.55
V
V
voltage; all
outputs
IO = 50 µA
LOW-level output VI = VIH or VIL;
voltage
IO = 4.0 mA
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
−
−
−
−
−
−
−
3
0.36
0.1
−
−
0.44
1.0
±2.5
20
−
−
−
−
−
0.55
2.0
II
input leakage
current
VI = VCC or GND 5.5
µA
IOZ
ICC
CI
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
5.5
±0.25 −
±10.0 µA
quiescent supply VI = VCC or GND; 5.5
2.0
10
−
−
40
10
µA
current
IO = 0
input capacitance
−
10
pF
1999 Sep 17
5
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
Family 74AHCT
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
OTHER VCC (V)
4.5 to 5.5 2.0
T
amb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
VIL
HIGH-level input
voltage
−
−
2.0
−
2.0
−
V
LOW-level input
voltage
4.5 to 5.5
4.5
−
−
0.8
−
−
0.8
−
−
0.8
−
V
VOH
HIGH-level output VI = VIH or VIL;
4.4 4.5
4.4
3.8
−
4.4
3.70
−
V
voltage; all outputs IO = −50 µA
HIGH-level output VI = VIH or VIL;
4.5
3.94
−
0
−
−
−
−
−
−
V
voltage
IO = −8.0 mA
VOL
LOW-level output
VI = VIH or VIL;
voltage; all outputs IO = 50 µA
4.5
−
−
−
−
0.1
0.36
0.1
0.1
0.44
1.0
±2.5
0.1
0.55
2.0
V
LOW-level output
voltage
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
V
II
input leakage
current
VI = VIH or VIL
5.5
−
−
µA
IOZ
3-state output OFF VI = VIH or VIL;
5.5
±0.25 −
−
±10.0 µA
current
VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
−
−
2.0
−
−
20
−
−
40
µA
∆ICC
additional
VI = VCC − 2.1 V; 4.5 to 5.5
1.35
1.5
1.5
mA
quiescent supply
current per input
pin
other inputs at
VCC or GND;
IO = 0
CI
input capacitance
−
−
3
10
−
10
−
10
pF
1999 Sep 17
6
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
AC CHARACTERISTICS
Type 74AHC86
Voltage are referenced to GND (ground = 0 V); tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay see Figs 5 and 6 15 pF
−
−
4.8
6.8
11.0 1.0
14.5 1.0
13.0 1.0
16.5 1.0
14.0 ns
18.5 ns
nA, nB to nY
50 pF
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH
propagation delay see Figs 5 and 6 15 pF
−
−
3.4
4.8
6.8
8.8
1.0
1.0
8.0
1.0
8.5
ns
nA, nB to nY
50 pF
10.0 1.0
11.0 ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
Type 74AHCT86
Ground = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
WAVEFORMS CL
T
amb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay see Figs 5 and 6 15 pF
−
−
3.4
4.9
6.9
8.8
1.0
1.0
8.0
1.0
9.0
ns
nA, nB to nY
50 pF
10.0 1.0
11.0 ns
Note
1. Typical values at VCC = 5.0 V.
1999 Sep 17
7
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
AC WAVEFORMS
V
handbook, halfpage
nA, nB input
I
V
M
GND
t
t
PHL
PLH
V
nY output
M
MNA244
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
FAMILY
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
Fig.5 The input (nA, nB) to output (nY) propagation delays.
S1
V
CC
open
V
CC
GND
1000 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
R
L
T
MNA245
TEST
S1
open
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Definitions for test circuit:
VCC
CL = load capacitance including jig and probe capacitance (see “AC characteristics” for values).
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
GND
Fig.6 Load circuitry for switching times.
8
1999 Sep 17
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.050
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT108-1
076E06S
MS-012AB
1999 Sep 17
9
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT402-1
MO-153
1999 Sep 17
10
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Sep 17
11
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 17
12
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
NOTES
1999 Sep 17
13
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
NOTES
1999 Sep 17
14
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
NOTES
1999 Sep 17
15
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/01/pp16
Date of release: 1999 Sep 17
Document order number: 9397 750 06109
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