74AHCT157PW,112 [NXP]
74AHC(T)157 - Quad 2-input multiplexer TSSOP 16-Pin;
| 型号： | 74AHCT157PW,112 |
| 厂家： | 
NXP |
| 描述： | 74AHC(T)157 - Quad 2-input multiplexer TSSOP 16-Pin 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC157; 74AHCT157
Quad 2-input multiplexer
Rev. 02 — 9 November 2007
Product data sheet
1. General description
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with
Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two
sources under the control of a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of
all other input conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74AHC/AHCT157. The state of the common data select input (S) determines
the particular register from which the data comes. It can also be used as function
generator. The device is useful for implementing highly irregular logic by generating any
four of the 16 different functions of two variables with one variable common. The
74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determine by the logic levels applied to S.
The logic equations are:
1Y = E × (1I1 × S + 1I0 × S)
2Y = E × (2I1 × S + 2I0 × S)
3Y = E × (3I1 × S + 3I0 × S)
4Y = E × (4I1 × S + 4I0 × S)
The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true)
outputs.
2. Features
■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ Inputs accepts voltages higher than VCC
■ Multiple input enable for easy expansion
■ Ideal for memory chip select decoding
■ For 74AHC157 only: operates with CMOS input levels
■ For 74AHCT157 only: operates with TTL input levels
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AHC157D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHCT157D
74AHC157PW
74AHCT157PW
74AHC157BQ
74AHCT157BQ
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
4. Functional diagram
S
E
1I1
1Y
2Y
1I0
2I1
2I0
2
3
5
6
11 10 14 13
3I1
3I0
3Y
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
1
S
E
15
4I1
1Y
4
2Y
7
3Y
9
4Y
12
4Y
4I0
mna484
mna481
Fig 1. Logic diagram
Fig 2. logic symbol
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
2 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
1
G1
1I0
1I1
2
3
1Y
2Y
3Y
4Y
4
7
15
EN
2I0
2I1
3I0
3I1
4I0
5
6
2
1
1
MUX
4
7
9
3
5
6
MULTIPLEXER
OUTPUTS
SELECTOR
11
10
14
9
11
10
12
13 4I1
14
13
12
S
1
E
mna483
15
mna482
Fig 3. Logic symbol
Fig 4. IEC logic symbol
5. Pinning information
5.1 Pinning
terminal 1
index area
74AHC157
74AHCT157
2
3
4
5
6
7
15
1I0
1I1
1Y
2I0
2I1
2Y
E
14
13
12
11
10
4I0
4I1
4Y
3I0
3I1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1I0
V
E
CC
157
1I1
4I0
4I1
4Y
3I0
3I1
3Y
1Y
(1)
GND
2I0
2I1
2Y
001aac931
GND
001aah066
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO16, TSSOP16
Fig 6. Pin configuration DHVQFN16
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
3 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
5.2 Pin description
Table 2.
Symbol
S
Pin description
Pin
Description
1
common data select input
data inputs from source 0
data inputs from source 1
multiplexer outputs
ground (0 V)
1I0 to 4I0
1I1 to 4I1
1Y to 4Y
GND
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
E
15
16
enable input (active LOW)
supply voltage
VCC
6. Functional description
Table 3.
Function table[1]
Input
Output
E
H
L
L
L
L
S
X
L
nI0
X
nI1
X
nY
L
L
X
L
L
H
X
X
H
L
H
H
L
X
H
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
4 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−20
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
±20
±25
75
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−75
−65
-
storage temperature
total power dissipation
SO16 package
+150
Tamb = −40 °C to +125 °C
[2]
[3]
[4]
-
-
-
500
500
500
mW
mW
mW
TSSOP16 package
DHVQFN16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 °C.
[3] Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] Ptot derates linearly with 4.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC157
74AHCT157
Unit
Min
2.0
0
Typ
Max
5.5
Min
4.5
0
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
5.0
5.0
V
V
V
-
5.5
-
5.5
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
0
-
VCC
Tamb
∆t/∆V
−40
-
+25
−40
-
+25
+125 °C
input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
-
-
-
-
-
ns/V
ns/V
-
-
20
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
5 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
For type 74AHC157
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.8
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
CI
CO
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
4.0
10
-
-
-
-
40
10
-
-
-
-
80
10
-
µA
pF
pF
V
input
capacitance
3.0
4.0
output
capacitance
For type 74AHCT157
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
3.8
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
0
-
0.1
-
-
0.1
-
-
0.1
V
V
IO = 8.0 mA
0.36
0.44
0.55
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
6 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
-
-
-
-
-
0.1
-
1.0
-
2.0
µA
µA
mA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
4.0
-
-
40
-
-
80
V
additional
per input pin;
1.35
1.5
1.5
supply current VI = VCC − 2.1 V; IO = 0 A;
other pins at VCC or GND;
V
CC = 4.5 V to 5.5 V
CI
input
capacitance
-
-
3
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
4.0
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 Unit
°C
Min Typ[1] Max Min
Max
Min
Max
For type 74AHC157
[2]
[2]
[2]
tpd
propagation nI0, nI1 to nY; see Figure 7
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.4
9.7
1.0
1.0
11.5
15.0
1.0
1.0
12.5
16.5
ns
ns
CL = 50 pF
6.3 13.2
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.2
4.6
6.4
8.4
1.0
1.0
7.5
9.5
1.0
1.0
8.0
ns
ns
CL = 50 pF
10.5
S to nY; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.8 13.6
6.8 17.1
1.0
1.0
16.0
19.5
1.0
1.0
17.0
21.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.6
8.6
1.0
1.0
10.0
12.0
1.0
1.0
11.0
13.5
ns
ns
CL = 50 pF
5.2 10.6
E to nY; see Figure 8
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.9 13.2
8.4 16.7
1.0
1.0
15.5
19.0
1.0
1.0
16.5
21.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.2
8.1
1.0
1.0
9.5
1.0
1.0
10.5
13.0
ns
ns
CL = 50 pF
6.0 10.1
11.5
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
7 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
Table 7.
Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 Unit
°C
Min Typ[1] Max Min
Max
Min
Max
[3]
CPD
power
dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
4 outputs switching via S
1 outputs switching via I
-
-
31
13
-
-
-
-
-
-
-
-
-
-
pF
pF
For type 74AHCT157
[2]
tpd
propagation nI0, nI1 to nY; see Figure 7
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
-
-
3.2
4.6
6.4
8.7
1.0
1.0
7.5
9.8
1.0
1.0
8.0
ns
ns
11.0
S to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.7
8.6
1.0
1.0
10.0
12.0
1.0
1.0
11.0
13.0
ns
ns
CL = 50 pF
5.2 10.4
[2]
[3]
E to nY; see Figure 8
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.7
8.1
1.0
1.0
9.5
1.0
1.0
10.5
13.5
ns
ns
CL = 50 pF
6.7 10.6
12.0
CPD
power
dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
4 outputs switching via S
1 outputs switching via I
-
-
41
16
-
-
-
-
-
-
-
-
-
-
pF
pF
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation PD (µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
8 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
11. Waveforms
V
I
nI0, nI1, S
input
V
M
GND
t
t
PHL
PLH
V
OH
V
M
nY output
mna486
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (nI0, nI1, S) to output (nYn)
V
CC
V
M
E input
GND
t
t
PHL
PLH
V
OH
V
nY output
M
mna485
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Propagation delay input (E) to output (nY)
Table 8.
Type
Measurement points
Input
VM
Output
VM
74AHC157
0.5VCC
1.5 V
0.5VCC
0.5VCC
74AHCT157
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
9 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
PULSE
GENERATOR
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 9. Load circuitry for switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC157
VCC
3.0 V
3.0 ns
3.0 ns
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74AHCT157
open
GND
VCC
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
10 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 10. Package outline SOT109-1 (SO16)
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
11 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 11. Package outline SOT403-1 (TSSOP16)
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
12 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 12. Package outline SOT763-1 (DHVQFN16)
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
13 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged-Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20071109
Data sheet status
Change notice
Supersedes
74AHC_AHCT157_2
Modifications:
Product data sheet
-
74AHC_AHCT157_1
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN16 package added.
• Section 8: derating values added for DHVQFN16 package.
• Section 12: outline drawing added for DHVQFN16 package.
74AHC_AHCT157_1
19990924
Product specification
-
-
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
14 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
15 of 16
74AHC157; 74AHCT157
NXP Semiconductors
Quad 2-input multiplexer
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 November 2007
Document identifier: 74AHC_AHCT157_2
相关型号：
74AHCT157PW-T
IC AHCT/VHCT/VT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Multiplexer/Demultiplexer
NXP
74AHCT157PW/T3
IC AHCT/VHCT/VT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Multiplexer/Demultiplexer
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