74AHCT595BQ [NXP]
NPN general-purpose double transistors output latches; 3-state; NPN通用晶体管双输出锁存器;三态
| 型号： | 74AHCT595BQ |
| 厂家： | 
NXP |
| 描述： | NPN general-purpose double transistors output latches; 3-state |
| 文件： | 总21页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with
output latches; 3-state
Rev. 04 — 11 August 2009
Product data sheet
1. General description
The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger action
I Inputs accept voltages higher than VCC
I Input levels:
N The 74AHC595 operates with CMOS input levels
N The 74AHCT595 operates with TTL input levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
I Serial-to-parallel data conversion
I Remote control holding register
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AHC595
74AHC595D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74AHC595PW
74AHC595BQ
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5 × 3.5 × 0.85 mm
74AHCT595
74AHCT595D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74AHCT595PW
74AHCT595BQ
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
9
12 STCP
13 OE
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q0
15
Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
2
3
4
5
6
7
mna554
Fig 1. Functional diagram
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
2 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
13
EN3
12
C2
11
12
10
SHCP
STCP
SRG8
R
11
9
15
1
C1/
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
14
15
1
1D
2D
3
2
2
14
3
DS
3
4
4
5
5
6
6
7
Q7
OE
7
MR
10
9
13
mna552
mna553
Fig 2. Logic symbol
Fig 3. IEC logic symbol
STAGE 0
Q
STAGES 1 TO 6
STAGE 7
DS
Q7S
D
D
Q
D
Q
FF7
CP
FF0
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
STCP
OE
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 4. Logic diagram
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
3 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
6. Pinning information
6.1 Pinning
74AHC595
74AHCT595
terminal 1
index area
74AHC595
74AHCT595
2
3
4
5
6
7
15
14
13
12
11
10
Q2
Q3
Q4
Q5
Q6
Q7
Q0
DS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
Q0
OE
Q3
DS
STCP
SHCP
MR
Q4
OE
Q5
STCP
SHCP
MR
Q6
Q7
001aae483
GND
Q7S
001aae538
Transparent top view
Fig 5. Pin configuration SO16 and TSSOP16
Fig 6. Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q1
Pin description
Pin
1
Description
parallel data output 1
parallel data output 2
parallel data output 3
parallel data output 4
parallel data output 5
parallel data output 6
parallel data output 7
ground (0 V)
Q2
2
Q3
3
Q4
4
Q5
5
Q6
6
Q7
7
GND
Q7S
MR
8
9
serial data output
10
11
12
13
14
15
16
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
SHCP
STCP
OE
DS
Q0
parallel data output 0
supply voltage
VCC
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
4 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
7. Functional description
Table 3.
Control
Function table[1]
Input Output
Function
SHCP STCP OE
MR
L
DS
X
Q7S
L
Qn
NC
L
X
X
X
↑
X
↑
L
L
H
L
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
L
X
L
X
X
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X
↑
↑
L
L
H
H
X
X
NC
QnS
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑
Q6S
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
SHCP
DS
STCP
MR
OE
Q0
Z-state
Z-state
Q1
Z-state
Z-state
Q6
Q7
Q7S
mna556
Fig 7. Timing diagram
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
5 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
IO
ICC
supply current
IGND
Tstg
Ptot
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
9. Recommended operating conditions
Table 5.
Symbol
74AHC595
VCC
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
input voltage
2.0
5.0
5.5
V
VI
0
-
5.5
V
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
V
Tamb
−40
+25
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT595
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
−40
-
+25
-
°C
ns/V
input transition rise and fall rate VCC = 4.5 V to 5.5 V
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
6 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC595
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9 2.0
2.9 3.0
4.4 4.5
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
2.58
3.94
-
-
2.48
3.80
2.40
3.70
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
-
µA
current
VCC = 0 V to 5.5 V
IOZ
ICC
CI
OFF-state
VI = VIH or VIL;
-
-
-
-
-
±0.25
4.0
-
-
-
±2.5
40
-
-
-
±10
80
µA
µA
pF
output current VO = VCC or GND; VCC = 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
input
3
10
10
10
capacitance
74AHCT595
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4 4.5
-
-
4.4
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
-
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
0
-
0.1
-
-
0.1
-
-
0.1
V
V
IO = 8.0 mA
0.36
0.44
0.55
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
7 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
-
-
0.1
-
1.0
-
2.0
µA
µA
current
VCC = 0 V to 5.5 V
IOZ
OFF-state
VI = VIH or VIL;
-
-
±0.25
-
±2.5
-
±10
output current VO = VCC or GND per input pin;
other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
-
-
-
-
4.0
-
-
40
-
-
80
µA
VCC = 5.5 V
∆ICC
additional
per input pin; VI = VCC − 2.1 V;
1.35
1.5
1.5
mA
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
CI
input
-
3
10
-
10
-
10
pF
capacitance
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
8 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions
74AHC595
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
[2]
[2]
[3]
[4]
[5]
tpd
propagation SHCP to Q7S; see Figure 8
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.7 13.0
7.7 16.5
1.0
1.0
15.0
18.5
1.0
1.0
16.5
20.1
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.0
8.2
1.0
1.0
9.4
1.0
1.0
10.5
12.5
ns
ns
CL = 50 pF
5.4 10.0
11.4
STCP to Qn; see Figure 9
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.9 11.9
7.7 15.4
1.0
1.0
13.5
17.0
1.0
1.0
15.0
18.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.2
5.5
7.4
9.0
1.0
1.0
8.5
1.0
1.0
9.5
ns
ns
CL = 50 pF
10.5
11.5
MR to Q7S; see Figure 11
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.9 12.8
7.4 16.3
1.0
1.0
13.7
17.2
1.0
1.0
15.0
18.7
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.4
8.0
1.0
1.0
9.1
1.0
1.0
10.0
12.0
ns
ns
CL = 50 pF
5.6 10.0
11.1
ten
enable time OE to Qn; see Figure 12
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.6 11.5
7.4 15.0
1.0
1.0
13.5
17.0
1.0
1.0
15.0
18.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.0
8.6
1.0
1.0
10.0
12.0
1.0
1.0
11.0
13.0
ns
ns
CL = 50 pF
5.3 10.6
tdis
disable time OE to Qn; see Figure 12
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.4 11.0
8.7 15.7
1.0
1.0
13.0
16.2
1.0
1.0
14.5
17.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.8
8.0
1.0
1.0
9.5
1.0
1.0
10.5
12.0
ns
ns
CL = 50 pF
5.8 10.3
11.0
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
9 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
fmax
maximum
frequency
SHCP or STCP;
see Figure 8 and 9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
80
125
170
-
-
60
-
-
40
90
-
-
MHz
MHz
130
110
tW
pulse width SHCP HIGH or LOW;
see Figure 8
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
STCP HIGH or LOW;
see Figure 9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
MR LOW; see Figure 11
VCC = 3.0 V to 3.6 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
tsu
set-up time DS to SHCP; see Figure 9
VCC = 3.0 V to 3.6 V
3.5
3.0
-
-
-
-
3.5
3.0
-
-
3.5
3.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
SHCP to STCP;
see Figure 10
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
8.5
5.0
-
-
-
-
8.5
5.0
-
-
8.5
5.0
-
-
ns
ns
th
hold time
DS to SHCP; see Figure 10
VCC = 3.0 V to 3.6 V
1.5
2.0
-
-
-
-
1.5
2.0
-
-
1.5
2.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
trec
recovery
time
MR to SHCP; see Figure 11
VCC = 3.0 V to 3.6 V
3.0
2.5
-
-
-
-
-
-
3.0
2.5
-
-
-
-
3.0
2.5
-
-
-
-
ns
ns
pF
VCC = 4.5 V to 5.5 V
[6]
[7]
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
180
74AHCT595; VCC = 4.5 V to 5.5 V
tpd propagation SHCP to Q7S; see Figure 8
[2]
[2]
[3]
delay
CL = 15 pF
-
-
3.8
8.2
1.0
1.0
9.0
1.0
1.0
10.0
12.0
ns
ns
CL = 50 pF
5.2 10.0
11.0
STCP to Qn; see Figure 9
CL = 15 pF
-
-
4.0
5.3
7.4
9.0
1.0
1.0
8.5
1.0
1.0
9.5
ns
ns
CL = 50 pF
10.5
11.5
MR to Q7S; see Figure 11
CL = 15 pF
-
-
4.6
8.2
1.0
1.0
9.5
1.0
1.0
10.5
12.5
ns
ns
CL = 50 pF
5.8 10.5
11.5
74AHC_AHCT595_4
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Product data sheet
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10 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
[4]
[5]
ten
enable time OE to Qn; see Figure 12
CL = 15 pF
CL = 50 pF
-
-
4.8
9.0
1.0
1.0
11.0
13.0
1.0
1.0
12.0
14.5
ns
ns
6.2 11.6
tdis
disable time OE to Qn; see Figure 12
CL = 15 pF
-
-
3.6
6.9
1.0
1.0
110
8.0
11.0
-
1.0
1.0
90
9.0
12.0
-
ns
CL = 50 pF
5.8 10.3
ns
fmax
tW
maximum
frequency
SHCP and STCP;
see Figure 8 and 9
130
170
-
-
-
MHz
pulse width SHCP HIGH or LOW;
see Figure 8
5.0
5.0
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
STCP HIGH or LOW;
see Figure 9
MR LOW; see Figure 11
5.0
3.0
5.0
-
-
-
-
-
-
5.0
3.0
5.0
-
-
-
5.0
3.0
5.0
-
-
-
ns
ns
ns
tsu
set-up time DS to SHCP; see Figure 9
SHCP to STCP;
see Figure 10
th
hold time
DS to SHCP; see Figure 10
MR to SHCP; see Figure 11
2.0
3.0
-
-
-
-
2.0
3.0
-
-
2.0
3.0
-
-
ns
ns
trec
recovery
time
[6]
[7]
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
-
190
-
-
-
-
-
pF
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH
.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH
.
[5] tdis is the same as tPLZ and tPHZ
.
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[7] All 9 outputs switching.
74AHC_AHCT595_4
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Product data sheet
Rev. 04 — 11 August 2009
11 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
12. Waveforms
1/f
max
V
I
SHCP input
GND
V
M
t
W
t
t
PHL
PLH
V
OH
V
Q7S output
M
V
OL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Shift clock pulse, maximum frequency and input to output propagation delays
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
M
Qn output
V
OL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Storage clock to output propagation delays
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
12 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Data set-up and hold times
V
I
V
MR input
M
GND
t
t
rec
W
V
I
SHCP input
Q7S output
V
M
GND
t
PHL
V
OH
V
M
V
OL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Master reset to output propagation delays
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
13 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
V
I
V
OE input
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
+ 0.3 V
V
OL
V
OL
t
t
PHZ
PZH
V
OH
− 0.3 V
OH
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna450
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
Table 8.
Type
Measurement points
Input
Output
VM
VM
74AHC595
0.5VCC
1.5 V
0.5VCC
0.5VCC
74AHCT595
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
14 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 13. Load circuitry for switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC595
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74AHCT595
open
GND
VCC
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
15 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 14. Package outline SOT109-1 (SO16)
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
16 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 15. Package outline SOT403-1 (TSSOP16)
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
17 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 16. Package outline SOT763-1 (DHVQFN16)
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
18 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
14. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
ESD
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date
20090811
Data sheet status
Change notice
Supersedes
74AHC_AHCT595_4
Modifications:
Product data sheet
-
74AHC_AHCT595_3
• Added type number 74AHCT595BQ (DHVQFN16 package)
74AHC_AHCT595_3
74AHC_AHCT595_2
74AHC_AHCT595_1
20080425
20060323
20000315
Product data sheet
Product data sheet
Product specification
-
-
-
74AHC_AHCT595_2
74AHC_AHCT595_1
-
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
19 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT595_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 11 August 2009
20 of 21
74AHC595; 74AHCT595
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register with output latches
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 August 2009
Document identifier: 74AHC_AHCT595_4
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