74ALS10AN [NXP]
Triple 3-Input NAND gate; 三路3输入与非门
| 型号： | 74ALS10AN |
| 厂家： | 
NXP |
| 描述： | Triple 3-Input NAND gate |
| 文件： | 总7页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALS10A
Triple 3-Input NAND gate
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74ALS10A
PIN CONFIGURATION
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPICAL
PROPAGATION DELAY
TYPE
1A
1B
2A
2B
2C
1
2
3
4
5
14 V
CC
74ALS10A
4.0ns
1.8mA
13 1C
12 1Y
11 3C
10 3B
ORDERING INFORMATION
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
2Y
6
7
9
8
3A
3Y
V
CC
= 5V ±10%,
= 0°C to +70°C
GND
T
amb
SC00014
14-pin plastic DIP
14-pin plastic SO
74ALS10AN
74ALS10AD
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
PINS
DESCRIPTION
HIGH/LOW
20µA/0.1mA
0.4mA/8mA
nA, nB, nC
nY
Data inputs
1.0/1.0
20/80
Data outputs
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
1
2
&
1
2
13
3
4
5
9
10 11
12
13
3
4
5
1A 1B 1C 2A 2B 2C 3A 3B 3C
6
1Y 2Y 3Y
9
10
11
8
12
6
8
V
= Pin 14
CC
GND = Pin 7
SC00016
SC00017
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUT
1
2
1A
12
6
1B
1C
1Y
2Y
3Y
nA
H
L
nB
H
X
nC
H
X
nY
L
13
3
4
2A
2B
H
5
2C
X
L
X
H
9
3A
3B
X
X
L
H
10
8
H
L
X
=
=
=
High voltage level
Low voltage level
Don’t care
11
V
= Pin 14
CC
3C
GND = Pin 7
SC00015
2
1991 Feb 08
853–0858 01670
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74ALS10A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
CC
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
V
V
IN
IN
I
mA
V
V
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
16
CC
I
mA
°C
°C
OUT
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
CC
Supply voltage
5.0
5.5
V
V
V
IH
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
IL
0.8
–18
–0.4
8
V
I
Ik
mA
mA
mA
°C
I
High-level output current
Low-level output current
OH
I
OL
T
amb
Operating free-air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
±10%, V = MAX, V = MIN, I = –0.4mA
UNIT
2
MIN
TYP
MAX
V
OH
V
V – 2
CC
V
V
CC
IL
IH
OH
I
OL
I
OL
= 4mA
= 8mA
0.25
0.35
-0.73
0.40
0.50
-1.5
0.1
V
V
= MIN, V = MAX,
IL
= MIN
CC
IH
V
OL
V
V
IK
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
V
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
mA
µA
mA
mA
mA
mA
I
I
IH
= MAX, V = 2.7V
20
I
I
IL
Low-level input current
= MAX, V = 0.5V
-0.1
-112
0.6
I
3
I
O
Output current
= MAX, V = 2.25V
-30
O
I
V = 0V
0.5
1.6
CCH
I
I
Supply current (total)
V
CC
= MAX
CC
I
V = 4.5V
I
2.2
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. The output conditions have been chosen to produce a current that closely approximate one half of the true short-circuit output current, I
.
OS
3
1991 Feb 08
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74ALS10A
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
MAX
t
t
Propagation delay
nA, nB, nC to nY
2.0
2.0
11.0
10.0
PLH
PHL
Waveform 1
ns
AC WAVEFORMS
For all waveforms, V = 1.3V.
M
nA, nB, nC
V
V
t
M
M
t
PHL
PLH
V
V
M
M
nY
SC00018
Waveform 1. Propagation Delay for Data to Output
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
V
CC
90%
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0.3V
PULSE
GENERATOR
D.U.T.
t
t )
f
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0.3V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Totem-pole Outputs
10%
10%
t
w
Input Pulse Definition
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
V
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
Family
Rep.Rate
t
w
t
t
THL
Amplitude
M
TLH
2.0ns
2.0ns
of
74ALS
3.5V
1.3V
1MHz
500ns
OUT
SC00005
4
1991 Feb 08
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74ALS10A
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
5
f1991 Feb 08
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74ALS10A
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
6
f1991 Feb 08
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74ALS10A
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
Document order number:
Philips
Semiconductors
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