74ALVC32BQ [NXP]
Quad 2-input OR gate; 四2输入或门
| 型号： | 74ALVC32BQ |
| 厂家： | 
NXP |
| 描述： | Quad 2-input OR gate |
| 文件： | 总13页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVC32
Quad 2-input OR gate
Rev. 02 — 10 December 2007
Product data sheet
1. General description
The 74ALVC32 is a quad 2-input OR gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features
■ Wide supply voltage range from 1.65 V to 3.6 V
■ 3.6 V tolerant inputs/outputs
■ CMOS low power consumption
■ Direct interface with TTL levels (2.7 V to 3.6 V)
■ Power-down mode
■ Latch-up performance exceeds 250 mA
■ Complies with JEDEC standards:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8B/JESD36 (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVC32D
−40 °C to +85 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74ALVC32PW −40 °C to +85 °C
74ALVC32BQ −40 °C to +85 °C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
4. Functional diagram
1
2
≥1
≥1
≥1
≥1
3
6
4
5
1
2
1A
1B
1Y
2Y
3Y
3
6
8
4
5
2A
2B
9
8
10
9
3A
3B
10
12
13
12
13
4A
4B
4Y 11
11
mna242
mna243
Fig 1. Logic symbol
Fig 2. IEC logic symbol
A
B
Y
mna241
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
terminal 1
index area
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
2
3
4
5
6
13
12
11
10
9
1B
1Y
2A
2B
2Y
4B
4A
4Y
3B
3A
1Y
32
2A
32
(1)
GND
2B
2Y
001aad102
8
GND
Transparent top view
001aad101
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
2 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
5.2 Pin description
Table 2.
Symbol
nA
Pin description
Pin
Description
data input
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
14
nB
data input
nY
data output
supply voltage
ground (0 V)
VCC
GND
7
6. Functional description
Table 3.
Function table[1]
Input nA
Input nB
Output nY
L
L
L
L
H
L
H
H
H
H
H
H
[1] H = HIGH voltage level
L = LOW voltage level
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
+4.6
±50
VCC + 0.5
+4.6
+4.6
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
output HIGH or LOW state
output 3-state
mA
V
[1] [2]
[2]
VO
−0.5
−0.5
−0.5
-
V
power-down mode, VCC = 0 V
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = −40 °C to +85 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
3 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
0
Max
3.6
3.6
VCC
3.6
3.6
+85
20
Unit
V
supply voltage
input voltage
output voltage
VI
V
VO
output HIGH or LOW state
output 3-state
0
V
0
V
power-down mode; VCC = 0 V
in free air
0
V
Tamb
ambient temperature
−40
0
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
VIH
HIGH-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
1.7
2.0
VIL
LOW-level input voltage
-
-
-
0.35 × VCC
0.7
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 3.6 V
V
CC − 0.2
1.25
1.8
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
IO = −6 mA; VCC = 1.65 V
IO = −12 mA; VCC = 2.3 V
IO = −18 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
1.51
2.10
2.01
2.53
2.76
2.68
1.7
2.2
2.4
2.2
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 3.6 V
IO = 6 mA; VCC = 1.65 V
IO = 12 mA; VCC = 2.3 V
IO = 18 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 3.0 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 3.6 V or GND
-
-
-
-
-
-
-
-
-
-
0.2
0.3
0.4
0.6
0.4
0.4
0.55
±5
V
0.11
0.17
0.25
0.16
0.23
0.30
±0.1
±0.1
V
V
V
V
V
V
II
input leakage current
µA
µA
IOFF
power-off leakage current VCC = 0 V; VI or VO = 0 V to 3.6 V
±10
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
4 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
ICC
∆ICC
CI
supply current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.2
10
µA
µA
pF
additional supply current
input capacitance
per input pin; VCC = 3.0 V to 3.6 V;
VI = VCC − 0.6 V; IO = 0 A
-
-
5
750
-
3.5
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
[2]
tpd
propagation delay
CP to Qn; see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
2.8
2.0
2.2
2.0
25
4.7
3.1
2.9
2.8
-
ns
ns
ns
ns
pF
1.0
1.0
1.0
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
[3]
CPD
power dissipation
capacitance
per gate; VI = GND to VCC; VCC = 3.3 V
[1] Typical values are measured at Tamb = 25 °C
[2] tpd is the same as tPHL and tPLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
5 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
11. Waveforms
V
I
V
nA, nB input
M
GND
t
t
PLH
PHL
V
nY output
M
mna244
Measurement points are given in Table 8.
Fig 6. Inputs nA, nB to output nY propagation delay times
Table 8. Measurement points
Supply voltage VCC
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
Input VI
VCC
VM
0.5VCC
0.5VCC
1.5 V
1.5 V
VCC
2.7 V
2.7 V
3.0 V to 3.6 V
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
6 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuitry for switching times
Table 9.
Test data
Supply voltage VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
6 V
tPHZ, tPZH
GND
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
open
GND
open
GND
3.0 V to 3.6 V
open
6 V
GND
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
7 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 8. Package outline SOT108-1 (SO14)
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
8 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 9. Package outline SOT402-1 (TSSOP14)
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
9 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 10. Package outline SOT762-1 (DHVQFN14)
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
10 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20071210
Data sheet status
Change notice
Supersedes
74ALVC32_2
Product data sheet
-
74ALVC32_1
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN14 package added.
• Section 7: derating values added for DHVQFN14 package.
• Section 12: outline drawing added for DHVQFN14 package.
74ALVC32_1
20021115
Product specification
-
-
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
11 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
12 of 13
74ALVC32
NXP Semiconductors
Quad 2-input OR gate
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 December 2007
Document identifier: 74ALVC32_2
相关型号：
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