74ALVC373PW [NXP]
Octal D-type transparent latch 3-state; 八D型透明锁存器3 -STATE
| 型号： | 74ALVC373PW |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch 3-state |
| 文件： | 总20页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVC373
Octal D-type transparent latch;
3-state
Product specification
2002 Feb 26
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
FEATURES
DESCRIPTION
The 74ALVC373 is a high-performance, low-power,
• Wide supply voltage range from 1.65 to 3.6 V
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
• Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
The 74ALVC373 is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
internal latches.
• 3.6 V tolerant inputs/outputs
• CMOS LOW power consumption
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
The 74ALVC373 consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state
each time its corresponding D-input changes.
• Latch-up performance exceeds ≤250 mA
• ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’
have a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
propagation delay inputs Dn to output Qn VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.3
CONDITIONS
TYP.
UNIT
ns
t
PHL/tPLH
3.0
ns
ns
ns
pF
V
V
CC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.4
CC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2
3.5
CI
input capacitance
CPD
power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2
outputs enable
35
14
pF
pF
outputs disabled
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC and the latch is in transparent mode.
2002 Feb 26
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
PACKAGE
MATERIAL
CODE
74ALVC373D
20
20
SO
plastic
plastic
SOT163-1
SOT360-1
74ALVC373PW
TSSOP
FUNCTION TABLE
See note 1.
INPUT
OUTPUTS
INTERNAL
LATCHES
OPERATING MODES
OE
LE
Dn
Q0 to Q7
Enable and read register
(transparent mode)
L
L
H
H
L
L
H
l
L
H
L
L
H
L
Latch and read register
L
L
L
h
X
h
H
X
H
H
Z
Z
Latch register and disable
outputs
H
H
X
L
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
PINNING
PIN
SYMBOL
OE
DESCRIPTION
output enable input (active LOW)
1
2, 5, 6, 9, 12, 15, 16, 19
Q0 to Q7
D0 to D7
GND
3-state latch output
data input
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
ground (0 V)
LE
latch enable input (active HIGH)
supply voltage
VCC
2002 Feb 26
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
handbook, halfpage
V
OE
1
2
20
19
18
17
16
15
14
13
12
11
CC
handbook, halfpage
11
LE
Q
0
Q
D
7
3
4
2
5
6
9
D
0
3
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
7
6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
D
D
1
4
7
Q
Q
D
Q
1
5
8
6
5
373
13
14
17
18
12
Q
2
6
15
16
19
D
2
7
5
4
D
D
3
8
OE
Q
Q
3
9
4
1
MNA186
GND
LE
10
MNA185
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
handbook, halfpage
EN
11
D
Q
Q
Q
Q
Q
Q
Q
Q
C1
3
4
2
5
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
3
2
7
6
1D
8
9
4
7
8
5
6
9
LATCH
1 to 8
3-STATE
OUTPUTS
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
LE
11
1
OE
MNA184
MNA187
Fig.3 IEE/IEC logic symbol.
Fig.4 Function diagram.
2002 Feb 26
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
LE
LE
handbook, halfpage
LE
D
Q
MNA692
LE
Fig.5 Logic diagram (one latch).
D
D
D
D
D
D
5
D
6
D
7
0
1
2
3
4
a n d b o o k , f u l l p a g e w
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
MNA199
Fig.6 Logic diagram.
5
2002 Feb 26
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
3.6
UNIT
V
VI
input voltage
0
3.6
VCC
3.6
3.6
+85
20
V
VO
output voltage
enable mode; VCC = 1.65 to 3.6 V 0
disable mode; VCC = 1.65 to 3.6 V 0
V
V
Power-down mode; VCC = 0 V
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +4.6
V
IIK
input diode current
input voltage
VI < 0
−
−50
mA
V
VI
−0.5
−
+4.6
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
enable mode; notes 1 and 2
disable mode
±50
mA
V
−0.5
−0.5
−0.5
−
VCC + 0.5
+4.6
V
Power-down mode; note 2
VO = 0 to VCC
+4.6
V
IO
output diode current
VCC or GND current
storage temperature
power dissipation per package
SO package
±50
mA
mA
°C
IGND, ICC
−
±100
+150
Tstg
Ptot
−65
above 70 °C derate linearly with
8 mW/K
−
−
500
500
mW
mW
TSSOP package
above 60 °C derate linearly with
5.5 mW/K
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
2002 Feb 26
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
TYP.(1)
UNIT
OTHER
VCC (V)
MIN.
MAX.
VIH
HIGH-level input
voltage
1.65 to 1.95 0.65 × VCC
−
−
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.7
2
−
−
−
−
VIL
LOW-level input
voltage
−
−
0.35 × VCC
−
−
0.7
0.8
0.2
0.3
0.4
0.6
0.4
0.4
0.55
−
−
−
VOL
LOW-level output
voltage
VI = VIH or VIL; IO = 100 µA 1.65 to 3.6
−
−
VI = VIH or VIL; IO = 6 mA
VI = VIH or VIL; IO = 12 mA
VI = VIH or VIL; IO = 18 mA
VI = VIH or VIL; IO = 12 mA
VI = VIH or VIL; IO = 18 mA
VI = VIH or VIL; IO = 24 mA
1.65
2.3
2.3
2.7
3.0
3.0
−
0.11
0.17
0.25
0.16
0.23
0.30
−
−
−
−
−
−
VOH
HIGH-level output
voltage
VI = VIH or VIL; IO = −100 µA 1.65 to 3.6
VI = VIH or VIL; IO = −6 mA 1.65
V
CC − 0.2
1.25
1.8
1.7
2.2
2.4
2.2
−
1.51
2.10
2.01
2.53
2.76
2.68
±0.1
−
VI = VIH or VIL; IO = −12 mA 2.3
VI = VIH or VIL; IO = −18 mA 2.3
VI = VIH or VIL; IO = −12 mA 2.7
VI = VIH or VIL; IO = −18 mA 3.0
VI = VIH or VIL; IO = −24 mA 3.0
−
−
−
−
−
II
input leakage
current
VI = 3.6 V or GND
3.6
±5
IOZ
Ioff
ICC
∆ICC
3-state output
OFF-state current
VI = VIH or VIL;
VO = 3.6 V or GND; note 2
1.65 to 3.6
0.0
−
−
−
−
0.1
±0.1
0.2
5
±10
±10
10
µA
µA
µA
µA
power OFF leakage VI or VO = 0 to 3.6 V
current
quiescent supply
current
VI = VCC or GND; IO = 0
3.6
additional
VI = VCC − 0.6 V; IO = 0
3.0 to 3.6
750
quiescent supply
current per input
pin
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For transceivers, the parameter IOZ includes the input leakage current.
2002 Feb 26
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
AC CHARACTERISTICS
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
UNIT
WAVEFORMS
see Figs 7 and 11
VCC (V)
MIN.
TYP.(1)
MAX.
tPHL/tPLH propagation delay Dn to Qn
1.65 to 1.95
2.3 to 2.7
2.7
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
3.8
3.3
3.3
3.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.7
2.5
2.0
2.3
2.2
2.8
2.1
2.4
2.3
3.0
2.4
3.0
2.3
3.4
2.2
2.8
2.7
1.0
0.8
2.0
2.2
0.1
0.1
0.1
0.1
−0.1
−0.2
−0.3
−0.1
5.4
3.5
3.6
3.3
6.0
3.8
3.7
3.3
6.4
4.5
4.6
4.0
7.0
4.4
4.4
4.4
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
t
t
t
PHL/tPLH propagation delay LE to Qn see Figs 8 and 11
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
PZH/tPZL
3-state output enable time
OE to Qn
see Figs 9 and 11
see Figs 9 and 11
see Figs 8 and 11
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
PHZ/tPLZ
3-state output disable time
OE to Qn
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
tW
tsu
th
LE pulse with HIGH
set-up time Dn to LE
hold time Dn to LE
−
−
3.0 to 3.6
−
see Figs 10 and 11 1.65 to 1.95
−
2.3 to 2.7
−
2.7
−
3.0 to 3.6
−
see Figs 10 and 11 1.65 to 1.95
−
2.3 to 2.7
2.7
−
−
3.0 to 3.6
−
Note
1. All typical values are measured at Tamb = 25 °C.
2002 Feb 26
8
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
AC WAVEFORMS
V
handbook, halfpage
I
V
D
input
M
n
GND
t
t
PHL
PLH
V
OH
V
Q
output
M
n
MNA693
V
OL
INPUT
tr = tf
VCC
VM
VI
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
Fig.7 Input Dn to output Qn propagation delay times.
1/f
max
V
I
LE input
V
M
t
GND
t
W
t
PHL
PLH
V
OH
V
Q
output
M
n
V
OL
MNA694
INPUT
tr = tf
VCC
VM
VI
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
Fig.8 Latch enable (LE) input pulse width and latch enable input to output (Qn) propagation delays.
2002 Feb 26
9
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CC
Q
output
n
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
Q
output
n
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA395
INPUT
tr = tf
VCC
VM
VI
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
1.65 to 1.95 V 0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
VX = VOL + 0.15 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.15 V at VCC < 2.7 V.
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.9 3-state enable and disable times.
2002 Feb 26
10
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
V
I
V
D
input
M
n
GND
t
t
h
h
t
t
su
su
V
I
LE input
V
M
GND
MNA695
INPUT
tr = tf
VCC
VM
VI
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.10 The data set-up and hold times for Dn input to LE input.
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
VCC
VI
CL
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
30 pF
30 pF
1 kΩ
open
open
open
open
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
500 Ω
500 Ω
500 Ω
2.7 V 50 pF
2.7 V 50 pF
3.0 to 3.6 V
6 V
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.11 Load circuitry for switching times.
11
2002 Feb 26
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT163-1
075E04
MS-013
2002 Feb 26
12
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.10
0.25
0.65
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT360-1
MO-153
2002 Feb 26
13
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Feb 26
14
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Feb 26
15
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Feb 26
16
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
NOTES
2002 Feb 26
17
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
NOTES
2002 Feb 26
18
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC373
NOTES
2002 Feb 26
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp20
Date of release: 2002 Feb 26
Document order number: 9397 750 09437
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