74ALVCH16823DL,112 [NXP]

74ALVCH16823 - 18-bit bus-interface D-type flip-flop with reset and enable (3-State) SSOP 56-Pin;


型号：	74ALVCH16823DL,112
厂家：	NXP
描述：	74ALVCH16823 - 18-bit bus-interface D-type flip-flop with reset and enable (3-State) SSOP 56-Pin
文件：	总12页 (文件大小：109K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

74ALVCH16823

18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

Product specification

IC24 Data Handbook

1998 Jul 29

Philips

Semiconductors

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

DESCRIPTION

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring

separate D-type inputs for each flip-flop and 3-state outputs for bus

oriented applications. Incorporates bushold data inputs which

eliminate the need for external pull-up resistors to hold unused

inputs. The74ALVCH16823 consists of two sections of nine

edge-triggered flip-flops. A clock (CP) input, an output-enable (OE)

input, a Master reset (MR) input and a clock-enable( CE) input are

provided for each total 9-bit section.

• Complies with JEDEC standard no. 8-1A.

• CMOS low power consumption

• Direct interface with TTL levels

• Current drive ± 24 mA at 3.0 V

• Multibyte flow-through standard pin-out architecture

With the clock-enable (CE) input LOW, the D-type flip-flops will store

the state of their individual D-inputs that meet the set-up and hold

time requirements on the LOW-to-HIGH CP transition. Taking CE

HIGH disables the clock buffer, thus latching the outputs. Taking the

Master reset (MR) input LOW causes all the Q outputs to go LOW

independently of the clock.

• Low inductance multiple V and GND pins to minimize noise and

ground bounce

• All data inputs have bus hold

• Output drive capability 50Ω transmission lines @ 85°C

When OE is LOW, the contents of the flip-flops are available at the

outputs. When the OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the

state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data

inputs at a valid logic level.

QUICK REFERENCE DATA

GND = 0V; T

= 25°C; t = t ≤ 2.5ns

amb

r f

SYMBOL

PARAMETER

CONDITIONS

= 2.5V, CL = 30pF

TYPICAL

UNIT

Propagation delay

CP to Qn

2.1

PHL PLH

= 3.3V, CL = 50pF

= 2.5V, CL = 30pF

= 3.3V, CL = 50pF

300

350

Maximum clock frequency

Input capacitance

MHz

max

5.0

Outputs enabled

Outputs disabled

Power dissipation capacitance per latch

V = GND to V

NOTES:

is used to determine the dynamic power dissipation (P in mW):

= C × V

× f + S (C × V × f ) where:

CC o

f = input frequency in MHz; C = output load capacity in pF;

f = output frequency in MHz; V = supply voltage in V;

S (C × V

× f ) = sum of outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

SOT371-1

56-Pin Plastic SSOP Type II

56-Pin Plastic TSSOP Type II

-40°C to +85°C

74ALVCH16823 DL

ACH16823 DL

74ALVCH16823 DGG

ACH16823 DGG

SOT364-1

1998 Jul 29

853–2100 19800

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

PIN DESCRIPTION

PIN NUMBER

2, 27

SYMBOL

FUNCTION

1OE, 2OE

Output enable input (active-Low)

Data inputs

54, 52, 51, 49, 48, 47, 45, 44, 43

42, 41, 40, 38, 37, 36, 34, 33, 31

1D0-1D8

2D0-2D8

3, 5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24, 26

1Q0-1Q8

2Q0-2Q8

Data outputs

56, 29

55, 30

1CP, 2CP

1CE, 2CE

1MR, 2MR

GND

Clock pulse input (active rising edge)

Clock enable input (active-Low)

Master reset input (active-Low)

Ground (0V)

1, 28

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

Positive supply voltage

PIN CONFIGURATION

LOGIC SYMBOL

1MR

1OE

1Q0

GND

1Q1

1Q2

1CP

1CE

1D0

GND

1D1

1D2

1MR 2MR 1OE 2OE

1Q3

1Q4

1Q5

GND

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

GND

2Q3

2Q4

2Q5

1D3

1D4

1D5

GND

1D6

1D7

1D8

2D0

2D1

2D2

GND

2D3

2D4

2D5

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

1CP 2CP 1CE 2CE

48 29 55 30

SW00341

2Q6

2Q7

GND

2Q8

2OE

2MR

2D6

2D7

GND

2D8

2CE

2CP

SH00014

1998 Jul 29

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

LOGIC SYMBOL (IEEE/IEC)

BUS HOLD CIRCUIT

1OE

1MR

1CE

1CP

2OE

2MR

2CE

2CP

EN1

3C4

EN5

Data Input

To internal circuit

7C8

1, 2

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

SW00044

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

5, 6

SH00015

LOGIC DIAGRAM

nCE

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

nD8

nCP

nMR

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

nQ8

SH00016

n = 1 or 2

1998 Jul 29

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

FUNCTION TABLE

INPUTS

OUTPUT

nQx

OPERATING MODES

nOE

nMR

nCE

nCP

nDx

↑

Clear

Load and read data

↑

Hold

Disable outputs

H = HIGH voltage level

↑

HIGH voltage level one set-up time prior to the Low-to-High clock transition

LOW voltage level

LOW voltage level one set-up time prior to the Low-to-High clock transition

Don’t care

HIGH impedance “off” state

LOW to High clock transition

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MIN

MAX

DC supply voltage 2.5V range (for max. speed

performance @ 30 pF output load)

2.3

2.7

DC supply voltage 3.3V range (for max. speed

performance @ 50 pF output load)

3.0

3.6

DC supply voltage (for low-voltage applications)

1.2

for data input pins

for control pins

DC Input voltage range

5.5

DC output voltage range

amb

Operating free-air temperature range

–40

+85

°C

= 2.3 to 3.0V

= 3.0 to 3.6V

t , t

Input rise and fall times

ns/V

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

–0.5 to +4.6

–50

UNIT

DC input diode current

V t0

For control pins

–0.5 to +5.5

DC input voltage

For data inputs

uV or V t 0

–0.5 to V +0.5

DC output diode current

DC output voltage

"50

Note 1

= 0 to V

–0.5 to V +0.5

DC output source or sink current

°C

"50

"100

, I

DC V or GND current

GND CC

stg

Storage temperature range

–65 to +150

Power dissipation per package

–plastic medium-shrink (SSOP)

–plastic thin-medium-shrink (TSSOP) above +55°C derate linearly with 8 mW/K

For temperature range: –40 to +125 °C

above +55°C derate linearly with 11.3 mW/K

850

600

TOT

NOTE:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jul 29

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = -40°C to +85°C

UNIT

MIN

TYP

MAX

= 1.2V

= 1.8V

0.7*V

0.9

1.2

1.5

–

HIGH level Input voltage

= 2.3 to 2.7V

= 2.7 to 3.6V

= 1.2V

1.7

2.0

GND

= 1.8V

0.9

1.2

1.5

0.2*V

LOW level Input voltage

HIGH level output voltage

= 2.3 to 2.7V

= 2.7 to 3.6V

0.7

0.8

–

= 1.8 to 3.6V; V = V or V ; I = –100µA

*0.2

= 1.8V; V = V or V ; I = –6mA

0.4

0.3

0.5

0.6

0.5

0.10

0.08

0.17

0.26

0.14

0.28

–

= 2.3V; V = V or V ; I = –6mA

–

= 2.3V; V = V or V ; I = –12mA

–

= 2.3V; V = V or V ; I = –18mA

–

= 2.7V; V = V or V ; I = –12mA

–

= 3.0V; V = V or V

= –24mA

*1.0

–

IL; O

= 1.8 to 3.6V; V = V or V ; I = 100µA

GND

0.09

0.07

0.15

0.23

0.14

0.27

0.20

0.30

0.20

0.40

0.60

0.40

0.55

= 1.8V; V = V or V ; I = 6mA

= 2.3V; V = V or V ; I = 6mA

LOW level output voltage

= 2.3V; V = V or V ; I = 12mA

= 2.3V; V = V or V ; I = 18mA

= 2.7V; V = V or V ; I = 12mA

= 3.0V; V = V or V

I = 24mA

IL; O

Input leakage current per

control pin

= 1.8 to 3.6V;

0.1

150

V = 5.5V or GND

µA

Input leakage current per data

= 1.8 to 3.6V;

V = V or GND

= 1.8 to 2.7V;

V = V or GND

Input current for common I/O

pins

IHZ ILZ

= 3.6V;

V = V or GND

= 1.8 to 2.7V; V = V or V ;

I IH IL

= V or GND

3-State output OFF-state

current

= 2.7 to 3.6V; V = V or V ;

I IH IL

750

= V or GND

Additional quiescent supply

current given per data I/O pin

∆I

= 2.7V to 3.6V; V = V – 0.6V; I = 0

µA

= 2.3V; V = 0.7V

–

Bus hold LOW sustaining

current

BHL

= 3.0V; V = 0.8V

–45

–75

300

450

–300

–450

150

= 2.3V; V = 1.7V

Bus hold HIGH sustaining

current

µA

BHH

= 3.0V; V = 2.0V

–175

= 2.7V

Bus hold LOW overdrive current

BHLO

= 3.6V

= 2.7V

Bus hold HIGH overdrive

current

BHHO

= 3.6V

NOTES:

1. All typical values are at T

= 25°C.

amb

2. Valid for data inputs of bus hold parts.

1998 Jul 29

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

AC CHARACTERISTICS FOR V = 2.3V TO 2.7V RANGE AND V < 2.3V

GND = 0V; t = t ≤ 2.0ns; C = 30pF

LIMITS

SYMBOL

PARAMETER

WAVEFORM

= 2.3 to 2.7V

= 1.8V

= 1.2V

UNIT

1, 2

MIN TYP

MAX MIN TYP1 MAX

TYP

Propagation delay

nCP to nQ

1, 5

2, 5

4, 5

1.0

2.8

4.9

5.0

5.3

4.1

1.5

4.5

4.6

4.4

3.3

7.5

7.4

7.7

5.5

10.6

9.9

PLH PHL

Propagation delay

nMR to nQ

2.9

2.8

2.2

PLH PHL

3-State output enable time

nOE to nQ

10.4

6.7

PZH PZL

3-State output disable time

nOE to nQ

PHZ PLZ

nCP pulse width

1, 5

3, 5

3.0

1.2

1.8

0.8

0.3

1.0

150

1.6

0.4

4.0

1.5

2.0

0.6

0.3

0.8

125

2.0

0.8

nMR pulse width, LOW

Set up time nD to nCP

0.2

3, 5

Set up time nCE to nCP

–0.2

–0.1

0.2

–0.2

0.2

Hold time nD to nCP

Hold time nCE to nCP

Recovery time nMR to nCP

Maximum clock pulse frequency

2, 5

1, 5

0.3

0.2

rec

max

300

250

MHz

NOTE:

1. All typical values are measured at T

= 25°C.

amb

2. Typical value is measured at V = 2.5V.

AC CHARACTERISTICS FOR V = 3.0V TO 3.6V RANGE AND V = 2.7V

GND = 0V; t = t ≤ 2.5ns; C = 50pF

LIMITS

SYMBOL

PARAMETER

WAVEFORM

= 3.0 ± 0.3V

= 2.7V

UNIT

1, 2

MIN TYP

MAX

MIN

TYP

MAX

Propagation delay

nCP to nQ

1, 5

2, 5

4, 5

1.0

2.5

2.6

3.7

1.0

2.7

3.1

4.3

PLH PHL

Propagation delay

nMR to nQ

4.0

4.3

3.9

1.0

4.6

5.2

4.3

PLH PHL

3-State output enable time

nOE to nQ

2.5

2.8

PZH PZL

3-State output disable time

nOE to nQ

PHZ PLZ

nCP pulse width HIGH or LOW

nMR pulse width HIGH or LOW

1, 5

3, 5

2.5

1.2

1.5

0.8

0.5

1.0

200

1.4

0.3

0.2

–0.1

0.0

0.1

0.2

350

3.0

1.5

1.9

0.6

0.4

0.8

150

1.6

0.6

Set up time nD to nCP

0.4

3, 5

Set up time nCE to nCP

–0.1

–0.2

0.1

Hold time nD to nCP

Hold time nCE to nCP

Recovery time nMR to nCP

Maximum clock pulse frequency

2, 5

1, 5

0.1

rec

max

300

MHz

NOTES:

1. All typical values are measured at T

= 25°C.

amb

2. Typical value is measured at V = 3.3V.

1998 Jul 29

Philips Semiconductors

Product specification

18-bit D-type flip-flop (3-State)

74ALVCH16823

AC WAVEFORMS FOR V = 2.3V TO 2.7V AND

< 2.3V RANGE

= 0.5 V

= V + 0.15V

= V –0.15V

and V are the typical output voltage drop that occur with the

nOE INPUT

GND

output load.

= V

AC WAVEFORMS FOR V = 3.0V TO 3.6V AND

PZL

PLZ

= 2.7V RANGE

OUTPUT

LOW-to-OFF

OFF-to-LOW

= 1.5 V

= V + 0.3V

= V –0.3V

and V are the typical output voltage drop that occur with the

output load.

= 2.7V

PZH

PHZ

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

1/f

MAX

3.0V or V

whichever

is less

nCP

nQn

GND

outputs

enabled

outputs

disabled

outputs

enabled

PLH

PHL

SW00308

Waveform 4. 3-State Enable and Disable Times

TEST CIRCUIT

SH00017

Waveform 1. Clock (nCP) to Output (nQn) Propagation Delays,

Clock Pulse Width, and Maximum Clock Pulse Frequency

2<V

Open

GND

R =500 Ω

OUT

3.0V or V

whichever

is less

PULSE

GENERATOR

D.U.T.

nMR

R =500 Ω

3.0V or V

REC

whichever

is less

nCP

nQn

Test Circuit for 3-State Outputs

SWITCH POSITION

PHL

TEST

SWITCH

Open

t 2.7V

2.7 – 3.6V 2.7V

PLH PHL

SH00018

2<V

PLZ PZL

GND

Waveform 2. Master Reset (MR) Pulse WIdth, MR to

PHZ PZH

Output propagation Delay and MR to Clock Recovery Time

DEFINITIONS

R = Load resistor

C = Load capacitance includes jig and probe capacitance

nCP INPUT

GND

R = Termination resistance should be equal to Z

OUT

of pulse generators.

SW00047

Waveform 5. Load circuitry for switching times

nCE, nD INPUT

GND

nQ OUTPUT

NOTE: The data set-up and hold times for D or CE input to the CP input

SH00155

Waveform 3. Data Setup and Hold Times for the D or CE input

to the CP input

1998 Jul 29

Philips Semiconductors

Product specification

18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

74ALVCH16823

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm

SOT371-1

1998 Jul 29

Philips Semiconductors

Product specification

18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

74ALVCH16823

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm

SOT364-1

1998 Jul 29

Philips Semiconductors

Product specification

18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

74ALVCH16823

NOTES

1998 Jul 29

Philips Semiconductors

Product specification

18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

74ALVCH16823

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Sunnyvale, California 94088–3409

Telephone 800-234-7381

print code

Date of release: 05-96

9397-750-04554

Document order number:

Philips

Semiconductors

1998 Jul 29

74ALVCH16823DL,112 [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E