74ALVCH32501EC-S [NXP]
IC ALVC/VCX/A SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA114, 16 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-537-1, LFBGA-114, Bus Driver/Transceiver;
| 型号： | 74ALVCH32501EC-S |
| 厂家： | 
NXP |
| 描述： | IC ALVC/VCX/A SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA114, 16 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-537-1, LFBGA-114, Bus Driver/Transceiver 总线收发器 |
| 文件： | 总15页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVCH32501
36-bit universal bus transceiver with
direction pin; 3-state
Product specification
2004 Oct 13
Supersedes data of 2000 Mar 16
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
FEATURES
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
• 3-state non-inverting outputs for bus oriented
applications
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CPAB and CPBA).
For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When input LEAB is
LOW, the A data is latched if input CPAB is held at a HIGH
or LOW level. If input LEAB is LOW, the A data is stored in
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A
• Current drive ±24 mA at 3.0 V
• Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
the latch/flip-flop on the LOW-to-HIGH transition of CPAB
.
• CMOS low power consumption
When input OEAB is HIGH, the outputs are active. When
input OEAB is LOW, the outputs are in the high-impedance
state.
• Direct interface with TTL levels
• All inputs have bus-hold circuitry
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OEBA, LEBA and CPBA. The output enables are
complimentary (OEAB is active HIGH, and OEBA is active
LOW).
• Output drive capability 50 Ω transmission lines at 85 °C
• Plastic fine-pitch ball grid array package.
DESCRIPTION
To ensure the high-impedance state during power-up or
power-down, pin OEBA should be tied to VCC through a
pull-up resistor and pin OEAB should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
The 74ALVCH32501 is a high-performance CMOS
product designed for VCC operation at 2.5 V and 3.3 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
CL = 30 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
TYP.
2.8
UNIT
tPHL/tPLH
propagation delay An to Bn; Bn to An
ns
ns
3.0
4.0
8.0
CI
input capacitance
pF
pF
CI/O
CPD
input/output capacitance
power dissipation capacitance per latch VI = GND to VCC; note 1
outputs enabled
outputs disabled
21
3
pF
pF
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
2004 Oct 13
2
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
FUNCTION TABLE
See notes 1 and 2.
INPUT
OUTPUT
INTERNAL
REGISTERS
OPERATING MODE
nOEAB
nLEAB
nCPAB
nAn
nBn
L
H
X
X
X
Z
disabled
L
L
↓
↓
X
X
h
l
H
L
Z
Z
disabled; latch data
L
L
H or L
X
NC
Z
disabled; hold data
disabled; clock data
L
L
L
L
↑
↑
h
l
H
L
Z
Z
H
H
H
H
X
X
H
L
H
L
H
L
transparent
H
H
↓
↓
X
X
h
l
H
L
H
L
latch data and display
clock data and display
hold data and display
H
H
L
L
↑
↑
h
l
H
L
H
L
H
H
L
L
H or L
H or L
X
X
H
L
H
L
Notes
1. A-to-B data flow is shown; B-to-A flow is similar but uses nOEBA, nLEBA and nCPBA
2. H = HIGH voltage level;
.
h = HIGH voltage level on set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level on set-up time prior to the enable or clock transition;
NC = no change;
X = don’t care;
↑ = LOW-to-HIGH enable or clock transition;
↓ = HIGH-to-LOW enable or clock transition;
Z = high impedance OFF-state.
2004 Oct 13
3
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
RANGE
74ALVCH32501EC
−40 °C to +85 °C
114
LFBGA114
plastic
SOT537-1
PINNING
SYMBOL
DESCRIPTION
nAn
nBn
data inputs
data outputs
ground (0 V)
DC supply voltage
GND
VCC
nOEAB
nOEBA
nLEAB
nLEBA
nCPAB
nCPBA
output enable inputs A to B (active HIGH)
output enable inputs B to A (active LOW)
latch enable inputs A to B
latch enable inputs B to A
clock input A to B
clock input B to A
1B
1B
1B
1B
1B
1B
1B
V
1B
1B
1B
1B
1B
1B
V
1B
1B
1B
1B
n.c.
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
11
2B
2B
2B14 2B
6
5
4
3
2
1
1
3
5
7
9
11
13
14
16
1
3
5
7
9
13
16
1B
2CP
AB
2B
10
2B
15
2B
0
2
4
6
8
10
12
15
17
0
2
4
6
8
12
17
1CP
GND GND
GND GND
GND GND
GND 1CP
GND 1OE
GND GND GND
V
V
GND GND
GND GND
V
GND 2CP
GND 2OE
GND
AB
CC
CC
BA
BA
17
BA
BA
15
CC
CC
1LE
1OE
AB
GND
V
V
1LE
2LE
2OE
2A
GND
V
2LE
BA
AB
CC
CC
BA
AB
CC
CC
1A
1A
1A
1A
4
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
2A
2
2A
2A
2A
2A
2A
2A
10
2A
2A
2A
2A
2A
2A
0
2
3
6
8
10
12
15
AB
0
4
6
8
12
17
16
1A
1A
5
n.c.
2A
2A
3
2A
2A
11
1
7
9
11
13
14
16
1
5
7
9
13
14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
MNA562
Fig.1 Pin configuration.
4
2004 Oct 13
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
1OE
AB
1CP
BA
1LE
BA
1CP
AB
1LE
AB
V
handbook, halfpage
CC
1OE
BA
data
input
to internal circuit
C1
1D
C1
1D
MNA473
1B
0
1A
0
C1
1D
C1
1D
18 IDENTICAL CHANNELS
Fig.3 Bus-hold circuit.
2OE
AB
2CP
2LE
2CP
2LE
BA
BA
AB
AB
2OE
BA
C1
C1
1D
2B
0
2A
1D
0
C1
1D
C1
1D
18 IDENTICAL CHANNELS
MNA563
Fig.2 Logic symbol.
2004 Oct 13
5
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
2.7
UNIT
VCC
2.5 V range (for maximum speed 2.3
performance at 30 pF output load)
V
V
3.3 V range (for maximum speed 3.0
performance at 50 pF output load)
3.6
VI
input voltage
0
VCC
VCC
+85
20
V
V
VO
output voltage
output HIGH or LOW state
0
Tamb
tr, tf
ambient temperature
−40
0
°C
input rise and fall time ratios
(∆t/∆V)
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+4.6
+4.6
UNIT
VCC
VI
V
V
input voltage
for control pins; note 1
for data input pins; note 1
VI < 0 V
−0.5
−0.5
−
VCC + 0.5 V
IIK
input diode current
output clamping diode current
output voltage
−50
mA
mA
IOK
VO < 0 V; note 1
see note 1
−
50
VO
−0.5
−
VCC + 0.5 V
IO
output sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 V to VCC
−50
mA
mA
ICC, IGND
Tstg
Ptot
−
±100
+150
1000
−65
−
°C
Tamb = −40 °C to +85 °C; note 2
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of Ptot derates linearly with 1.8 mW/K.
2004 Oct 13
6
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-level input
voltage
2.3 to 2.7 1.7
2.7 to 3.6 2.0
1.2
−
V
1.5
1.2
1.5
−
V
V
V
LOW-level input
voltage
2.3 to 2.7
2.7 to 3.6
−
−
0.7
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −6 mA
IO = −12 mA
IO = −12 mA
IO = −12 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 6 mA
2.3 to 3.6
2.3
V
V
V
V
V
V
CC − 0.2 VCC
−
V
V
V
V
V
V
CC − 0.3
CC − 0.6
CC − 0.5
CC − 0.6
CC − 1.0
V
V
V
V
V
CC − 0.08 −
2.3
CC − 0.26 −
CC − 0.14 −
CC − 0.09 −
CC − 0.28 −
2.7
3.0
3.0
VOL
LOW-level output
voltage
2.3 to 3.6
2.3
−
−
−
−
−
−
−
GND
0.07
0.15
0.14
0.27
±0.1
0.1
0.20
0.40
0.70
0.40
0.55
±5
V
V
IO = 12 mA
IO = 12 mA
IO = 24 mA
2.3
V
2.7
V
3.0
V
II
input leakage current VI = VCC or GND
2.3 to 3.6
2.3 to 3.6
µA
µA
IOZ
3-state output
VI = VIH or VIL;
±10
OFF-state current
VO = VCC or GND; note 2
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0 A
2.3 to 3.6
2.7 to 3.6
−
−
0.4
80
µA
µA
∆ICC
additional quiescent
supply current given
per data I/O pin with
bus-hold
VI = VCC − 0.6 V;
IO = 0 A
150
750
IBHL
bus-hold LOW
sustaining current
VI = 0.7 V; note 3
VI = 0.8 V; note 3
VI = 1.7 V; note 3
VI = 2.0 V; note 3
note 3
2.3
3.0
2.3
3.0
3.6
45
−
−
−
−
−
−
µA
µA
µA
µA
µA
75
150
−
IBHH
bus-hold HIGH
sustaining current
−45
−75
500
−175
−
IBHLO
IBHHO
bus-hold LOW
overdrive current
bus-hold HIGH
note 3
3.6
−500
−
−
µA
overdrive current
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For I/O ports, the parameter IOZ includes the input leakage current.
3. Valid for data inputs of bus-hold parts.
2004 Oct 13
7
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
AC CHARACTERISTICS
Tamb = −40 °C to +85 °C; GND = 0 V
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
WAVEFORMS
CL
VCC = 2.3 V to 2.7 V; tr = tf ≤ 2.0 ns; note 1
tPHL/tPLH propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 30 pF 1.0
see Figs 5 and 8 30 pF 1.1
see Figs 5 and 8 30 pF 1.0
see Figs 6 and 8 30 pF 1.0
see Figs 6 and 8 30 pF 1.3
2.8
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
nLEBA to nAn; nLEAB to nBn
nCPBA to nAn; nCPAB to nBn
3.5
3.3
2.5
2.8
2.5
2.5
0.8
2.0
6.1
6.1
5.8
6.3
6.2
5.3
−
tPZH/tPZL
tPHZ/tPLZ
tW
3-state output enable time nOEAB to nBn
3-state output enable time nOEBA to nAn
3-state output disable time nOEAB to nBn see Figs 6 and 8 30 pF 1.5
3-state output disable time nOEBA to nAn see Figs 6 and 8 30 pF 1.3
nLEAB or nLEBA pulse width HIGH
see Figs 5 and 8 30 pF 3.3
see Figs 5 and 8 30 pF 3.3
nCPAB or nCPBA pulse width
HIGH or LOW
−
tsu
set-up time
nAn before nCPAB↑ or nBn before nCPBA
see Figs 7 and 8 30 pF 1.7
see Figs 7 and 8 30 pF 1.1
see Figs 7 and 8 30 pF 1.7
see Figs 7 and 8 30 pF 1.6
see Figs 5 and 8 30 pF 150
0.1
0.1
0.3
0.3
330
−
−
−
−
−
ns
↑
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA
ns
↓
th
hold time
ns
nAn after nCPAB↑ or nBn after nCPBA
↑
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA
ns
↓
fmax
maximum clock frequency
MHz
VCC = 2.7 V; tr = tf ≤ 2.5 ns; note 2
tPHL/tPLH propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 50 pF
see Figs 5 and 8 50 pF
see Figs 5 and 8 50 pF
see Figs 6 and 8 50 pF
see Figs 6 and 8 50 pF
−
−
−
−
−
−
−
3.0
3.6
3.4
2.7
3.3
3.6
3.3
0.7
1.4
4.6
5.3
5.6
5.3
6.0
5.7
4.6
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
nLEBA to nAn; nLEAB to nBn
nCPBA to nAn; nCPAB to nBn
tPZH/tPZL
tPHZ/tPLZ
tW
3-state output enable time nOEAB to nBn
3-state output enable time nOEBA to nAn
3-state output disable time nOEAB to nBn see Figs 6 and 8 50 pF
3-state output disable time nOEBA to nAn see Figs 6 and 8 50 pF
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8 50 pF 3.3
see Figs 5 and 8 50 pF 3.3
pulse width nCPAB or nCPBA
HIGH or LOW
−
tsu
set-up time
nAn before nCPAB↑ or nBn before nCPBA
see Figs 7 and 8 50 pF +1.4
see Figs 7 and 8 50 pF +1.0
−0.1
−0.2
−
−
ns
ns
↑
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA
↓
2004 Oct 13
8
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
0.3
MAX. UNIT
WAVEFORMS
CL
th
hold time
see Figs 7 and 8 50 pF 1.6
see Figs 7 and 8 50 pF 1.5
see Figs 5 and 8 50 pF 150
−
ns
nAn after nCPAB↑ or nBn after nCPBA
↑
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA
0.1
−
−
ns
↓
fmax
maximum clock frequency
333
MHz
VCC = 3.0 V to 3.6 V; tr = tf ≤ 2.5 ns; note 3
tPHL/tPLH propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 50 pF 1.0
see Figs 5 and 8 50 pF 1.3
see Figs 5 and 8 50 pF 1.4
see Figs 6 and 8 50 pF 1.0
see Figs 6 and 8 50 pF 1.1
3.0
3.4
3.3
2.4
2.5
2.9
3.1
0.9
1.1
4.2
4.8
4.9
4.6
5.0
5.0
4.2
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
nLEBA to nAn; nLEAB to nBn
nCPBA to nAn; nCPAB to nBn
tPZH/tPZL
tPHZ/tPLZ
tW
3-state output enable time nOEAB to nBn
3-state output enable time nOEBA to nAn
3-state output disable time nOEAB to nBn see Figs 6 and 8 50 pF 1.4
3-state output disable time nOEBA to nAn see Figs 6 and 8 50 pF 1.3
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8 50 pF 3.3
see Figs 5 and 8 50 pF 3.3
pulse width nCPAB or nCPBA
HIGH or LOW
−
tsu
set-up time
nAn before nCPAB↑ or nBn before nCPBA
see Figs 7 and 8 50 pF +1.3
see Figs 7 and 8 50 pF 1.0
see Figs 7 and 8 50 pF +1.3
see Figs 7 and 8 50 pF 1.2
see Figs 5 and 8 50 pF 150
−0.3
0.3
−
−
−
−
−
ns
↑
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA
ns
↓
th
hold time
−0.4
0.1
ns
nAn after nCPAB↑ or nBn after nCPBA
↑
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA
ns
↓
fmax
maximum clock frequency
340
MHz
Notes
1. All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
2. All typical values are measured at Tamb = 25 °C.
3. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Oct 13
9
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
AC WAVEFORMS
V
handbook, halfpage
nA , nB
I
n
n
V
M
input
GND
t
t
PHL
PLH
V
OH
nB , nA
n
output
n
V
M
MNA564
V
OL
VCC
2.3 V to 2.7 V 0.5 × VCC
2.7 V 1.5 V
3.0 V to 3.6 V 1.5 V
VM
VI
VCC
2.7 V
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Input nAn, nBn to output nBn, nAn propagation delay times.
1/f
max
V
I
nLE , nLE
AB
,
BA
nCP , nCP
V
AB
BA
M
t
input
GND
t
W
t
PHL
PLH
V
OH
nA , nB
n
n
V
M
output
V
OL
MNA565
VCC
VM
VI
2.3 V to 2.7 V 0.5 × VCC
2.7 V 1.5 V
3.0 V to 3.6 V 1.5 V
VCC
2.7 V
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Latch enable input (nLEAB, nLEBA) and clock input (nCPAB, nCPBA) to output propagation delays and their
pulse width.
2004 Oct 13
10
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
OE
OE
input
input
AB
V
V
M
M
BA
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
output
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA566
VCC
VM
VX
VY
OH − 150 mV VCC
VI
2.3 V to 2.7 V 0.5 × VCC
2.7 V 1.5 V
3.0 V to 3.6 V 1.5 V
VOL + 150 mV
VOL + 300 mV
VOL + 300 mV
V
V
V
OH − 300 mV 2.7 V
OH − 300 mV 2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state enable and disable times.
V
I
nA , nB
n
input
n
V
M
GND
t
t
h
h
t
t
su
su
V
I
nLE , nLE
AB
,
BA
nCP , nCP
V
M
AB
BA
input
GND
MNA567
The shaded areas indicate when the input is permitted to change for predictable output performance.
VCC
2.3 V to 2.7 V 0.5 × VCC
2.7 V 1.5 V
3.0 V to 3.6 V 1.5 V
VM
VI
VCC
2.7 V
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Data set-up and hold times for the nAn and nBn inputs to the nLEAB, nLEBA, nCPAB and nCPBA inputs.
2004 Oct 13
11
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
S1
2 × V
CC
open
GND
V
CC
R
500 Ω
L
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
50 pF
R
L
500 Ω
L
R
T
MNA479
TEST
S1
open
t
PLH/tPHL
Definitions for test circuit:
RL = Load resistor.
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
CL = Load capacitance including jig and probe capacitance.
GND
RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.8 Load circuitry for switching times.
2004 Oct 13
12
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
PACKAGE OUTLINE
LFBGA114: plastic low profile fine-pitch ball grid array package; 114 balls; body 16 x 5.5 x 1.05 mm SOT537-1
A
B
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2
e
y
y
v
M
M
C
C
A B
C
1
e
w
b
W
V
U
T
R
P
N
M
L
e
e
K
J
2
H
G
F
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
0
5
scale
10 mm
X
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
y
D
E
e
e
v
w
y
1
2
1
2
1
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
16.1
15.9
mm
1.5
4
14.4
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT537-1
2004 Oct 13
13
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
74ALVCH32501
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Oct 13
14
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/02/pp15
Date of release: 2004 Oct 13
Document order number: 9397 750 14053
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