74ALVCH373PY [IDT]
SSOP-20, Tube;
| 型号： | 74ALVCH373PY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SSOP-20, Tube |
| 文件： | 总6页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS OCTAL
IDT74ALVCH373
TRANSPARENT D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
FEATURES:
–
–
–
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
VCC = 3.3V ±0.3V, Normal Range
This octal transparent D-type latch is built using advanced dual metal
CMOS technology. The ALVCH373 device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and
workingregisters.While the latch-enable (LE)inputis high,the Qoutputs
followthe data (D)inputs.WhenLEis takenlow,the Qoutputs are latched
atthe logiclevels setupatthe Dinputs.
–
–
–
–
–
–
V
CC
= 2.7V to 3.6V, Extended Range
VCC = 2.5V ±0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP, QSOP, and TSSOP packages
Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs
ineithera normallogicstate (highorlowlogiclevels)ora high-impedance
state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebus
lines significantly.The high-impedance state andincreaseddrive provide
the capabilitytodrive bus lines withoutinterface orpullupcomponents.
Drive Features for ALVCH373:
–
–
High Output Drivers: ±24mA
Suitable for heavy loads
The ALVCH373 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
APPLICATIONS:
The ALVCH373 has a “bus-hold” which retains the inputs’ last state
wheneverthe inputbus goes toa highimpedance.This prevents floating
inputs andeliminates the needforpull-up/downresistors.
• 3.3V High Speed Systems
• 3.3Vandlowervoltagecomputingsystems
FUNCTIONALBLOCKDIAGRAM
1
OE
11
LE
C1
1D
2
1Q
3
1
D
TO SEVEN OTHER CHANNELS
MARCH1999
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
DSC-4474/-
IDT74ALVCH373
INDUSTRIALTEMPERATURERANGE
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Max.
Unit
(2)
VTERM
Terminal Voltage with Respect to GND
– 0.5 to +4.6
V
20
19
18
17
16
15
14
13
12
11
VCC
8Q
8D
1
2
OE
1Q
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC +0.5
V
IOUT
IIK
DC Output Current
– 50 to +50
±50
mA
mA
Continuous Clamp Current,
VI < 0 or VI > VCC
3
1D
4
7D
2D
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
SO20-2
SO20-7
SO20-8
SO20-9
ICC
ISS
TSTG
Continuous Current through each VCC
or GND
±100
5
7Q
6Q
6D
2Q
3Q
6
Storage Temperature
– 65 to +150
°C
ALVC Link
NOTES:
3D
7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
5D
4D
8
4Q
9
5Q
LE
GND
10
CC
3. All terminals except V
.
SSOP/ TVSOP/ TSSOP/ QSOP
TOP VIEW
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
CI/O
Output Capacitance
I/O Port Capacitance
VOUT = 0V
VIN = 0V
7
7
9
9
pF
pF
ALVC Link
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
OE
LE
xD
Output Enable Input (Active LOW)
Latch Enable Input (Active HIGH)
(1)
Data Inputs
xQ
3-State Outputs
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
(1)
FUNCTION TABLE
Inputs
Output
OE
LE
xD
xQ
L
H
H
H
L
L
H
H
L
L
X
X
L
Q0
X
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
Q = Level of Q before the indicated steady-state input conditions were
0
established.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVCH373
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7 V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
V
2
—
—
—
0.7
VIL
Input LOW Voltage Level
—
—
—
—
—
—
—
—
—
V
—
0.8
IIH
Input HIGH Current
VI = VCC
—
± 5
± 5
± 10
± 10
– 1.2
—
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
VO = VCC
VO = GND
—
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
VCC = 3.6V
—
µA
µA
V
—
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
– 0.7
100
0.1
mV
µA
ICCL
ICCH
ICCZ
∆ICC
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
Quiescent Power Supply
Current Variation
One input at VCC – 0.6V,
other inputs at VCC or GND
—
—
750
µA
ALVC Link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter(1)
Test Conditions
Min.
Typ.(2)
Max.
Unit
IBHH
Bus-Hold Input Sustain Current
VCC = 3.0V
VCC = 2.3V
VCC = 3.6V
VI = 2.0V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
– 75
—
—
µA
IBHL
75
– 45
45
—
—
—
—
—
—
IBHH
IBHL
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
µA
—
IBHHO
IBHLO
—
± 500
µA
ALVC Link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
CC
2. Typical values are at V = 3.3V, +25°C ambient.
3
IDT74ALVCH373
INDUSTRIALTEMPERATURERANGE
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
CC = 2.3V
VCC – 0.2
—
V
V
IOH = – 6mA
IOH = – 12mA
2
—
—
VCC = 2.3V
1.7
2.2
2.4
2
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3.0V
ALVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
o
OPERATING CHARACTERISTICS, T = 25 C
A
VCC = 2.5V ±0.2V
Typical
VCC = 3.3V±0.3V
Typical
Unit
Symbol
Parameter
Power Dissipation Capacitance
Outputs enabled
Test Conditions
CPD
CL = 0pF, f = 10Mhz
pF
CPD
Power Dissipation Capacitance
Outputs disabled
pF
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V±0.2V
VCC = 2.7V
VCC = 3.3V±0.3V
Symbol
tPLH
Parameter
Propagation Delay
Min
Max.
Min
Max.
Min
.
Max.
Unit
.
.
1.5
7.9
—
6.9
1.5
5.9
ns
tPHL
tPLH
xD to xQ
Propagation Delay
LE to xQ
2
8.7
8.5
7.5
—
—
—
7.7
7.5
6.5
2
6.7
6.5
5.5
ns
ns
ns
tPHL
tPZH
tPZL
Output Enable Time
OE to xQ
1.5
1.5
1.5
1.5
tPHZ
tPLZ
Output Disable Time
OE to xQ
3.3
2
—
—
—
3.3
2
—
—
—
3.3
2
—
—
—
ns
ns
ns
tW
tSU
Pulse Duration, LE HIGH
Setup Time, data before LE↓
Hold Time, data after LE↓
1.5
1.5
1.5
tH
(2)
tSK(o)
Output Skew
—
—
—
—
—
500
ps
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH373
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
PROPAGATIONDELAY
TESTCONDITIONS
Symbol
(1)
(1)
(2)
VIH
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V
Unit
SAME PHASE
INPUT TRANSITION
T
V
VLOAD
6
6
2 xVcc
Vcc
V
0V
tPHL
tPLH
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
VOH
VT
VOL
OUTPUT
VCC / 2
150
V
LZ
mV
mV
tPHL
tPLH
VIH
VT
0V
VHZ
CL
150
OPPOSITE PHASE
INPUT TRANSITION
30
pF
ALVC Link
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLEANDDISABLETIMES
LOAD
V
CC
V
Open
GND
DISABLE
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
VIN
VOUT
0V
Pulse(1, 2)
Generator
tPLZ
tPZL
D.U.T.
VLOAD/2
VLOAD/2
VLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
T
V
500Ω
RT
CL
VOL
tPHZ
tPZH
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
ALVC Link
VT
0V
HZ
V
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
0V
ALVC Link
Generator.
SET-UP, HOLD, AND RELEASE TIMES
NOTES:
F
R
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t ≤ 2.5ns; t ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
SWITCHPOSITION
DATA
INPUT
T
V
0V
SU
t
tH
Test
Switch
VIH
TIMING
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
T
V
0V
tREM
VIH
ASYNCHRONOUS
CONTROL
T
V
GND
Open
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
ALVC Link
H
t
ALVC Link
OUTPUT SKEW - TSK (x)
VIH
VT
0V
PULSEWIDTH
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
PULSE
VT
VT
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
SK (x)
t
tW
VOH
HIGH-LOW-HIGH
PULSE
T
VT
V
VOL
ALVC Link
tPLH2
tPHL2
SK(x)
PLH2 - PLH1 or PHL2 - PHL1
t t t
t
= t
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH373
INDUSTRIALTEMPERATURERANGE
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
ORDERINGINFORMATION
XX
X
XXX
ALVC
IDT
XX
Device Type Package
Bus-Hold
Temp. Range
SO
PY
Q
Small Outline IC (SO20-2)
Shrink Small Outline Package (SO20-7)
Quarter-size Small Outline Package (SO20-8)
Thin Shrink Small Outline Package (SO20-9)
PG
373
Octal Transparent D-Type Latch with 3-State Outputs
H
Bus-Hold
74
–40°C to +85°C
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6
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