74ALVCH32501EC [NXP]
36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state; 36位通用总线收发器的方向针;可承受5V电压;三态
| 型号： | 74ALVCH32501EC |
| 厂家： | 
NXP |
| 描述： | 36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state |
| 文件： | 总16页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVCH32501
36-bit universal bus transceiver with
direction pin; 5 V tolerant; 3-state
Product specification
2000 Mar 16
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
FEATURES
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
• 3-state non-inverting outputs for bus oriented
applications
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CPAB and CPBA).
For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When input LEAB is
LOW, the A data is latched if input CPAB is held at a HIGH
or LOW level. If input LEAB is LOW, the A data is stored in
• Wide supply voltage range of 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A
• Current drive ±24 mA at 3.0 V
• Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
the latch/flip-flop on the LOW-to-HIGH transition of CPAB
.
• CMOS low power consumption
When input OEAB is HIGH, the outputs are active. When
input OEAB is LOW, the outputs are in the high-impedance
state.
• Direct interface with TTL levels
• All inputs have bus-hold circuitry
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OEBA, LEBA and CPBA. The output enables are
complimentary (OEAB is active HIGH, and OEBA is active
LOW).
• Output drive capability 50 Ω transmission lines at 85 °C
• Plastic fine-pitch ball grid array package.
DESCRIPTION
To ensure the high-impedance state during power-up or
power-down, pin OEBA should be tied to VCC through a
pull-up resistor and pin OEAB should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
The 74ALVCH32501 is a high-performance CMOS
product designed for VCC operation at 2.5 and 3.3 V with
I/O compatibility up to 5 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
CL = 30 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
TYP.
2.8
UNIT
t
PHL/tPLH
propagation delay An to Bn; Bn to An
ns
ns
3.0
4.0
8.0
CI
input capacitance
pF
pF
CI/O
CPD
input/output capacitance
power dissipation capacitance per latch VI = GND to VCC; note 1
outputs enabled
outputs disabled
21
3
pF
pF
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2000 Mar 16
2
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
FUNCTION TABLE
See notes 1 and 2.
INPUT
OUTPUT
INTERNAL
REGISTERS
OPERATING MODE
nOEAB
nLEAB
nCPAB
nAn
nBn
L
H
X
X
X
Z
disabled
L
L
↓
↓
X
X
h
l
H
L
Z
Z
disabled; latch data
L
L
H or L
X
NC
Z
disabled; hold data
disabled; clock data
L
L
L
L
↑
↑
h
l
H
L
Z
Z
H
H
H
H
X
X
H
L
H
L
H
L
transparent
H
H
↓
↓
X
X
h
l
H
L
H
L
latch data and display
clock data and display
hold data and display
H
H
L
L
↑
↑
h
l
H
L
H
L
H
H
L
L
H or L
H or L
X
X
H
L
H
L
Notes
1. A-to-B data flow is shown; B-to-A flow is similar but uses nOEBA, nLEBA and nCPBA
2. H = HIGH voltage level;
.
h = HIGH voltage level on set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level on set-up time prior to the enable or clock transition;
NC = no change;
X = don’t care;
↑ = LOW-to-HIGH enable or clock transition;
↓ = HIGH-to-LOW enable or clock transition;
Z = high impedance OFF-state.
2000 Mar 16
3
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
RANGE
74ALVCH32501EC
−40 to +85 °C
114
LFBGA114
plastic
SOT537-1
PINNING
SYMBOL
DESCRIPTION
nAn
nBn
data inputs
data outputs
ground (0 V)
DC supply voltage
GND
VCC
nOEAB
nOEBA
nLEAB
nLEBA
nCPAB
nCPBA
output enable inputs A to B (active HIGH)
output enable inputs B to A (active LOW)
latch enable inputs A to B
latch enable inputs B to A
clock input A to B
clock input B to A
1B
1B
1B
1B
1B
1B
1B
V
1B
1B
1B
1B
1B
1B
V
1B
1B
1B
1B
n.c.
2B
2B
2B
2B
2B
2B
V
2B
2B
2B
2B
2B
11
2B
2B
2B14 2B
6
5
4
3
2
1
1
3
5
7
9
11
13
14
16
1
3
5
7
9
13
12
16
17
1B
2CP
2B
10
2B
2B
0
2
4
6
8
10
12
15
17
AB
0
2
4
6
8
15
1CP
GND GND
GND GND
GND GND
GND 1CP
GND 1OE
GND GND GND
GND GND
GND GND
V
GND 2CP
GND 2OE
GND
AB
CC
CC
BA
BA
17
BA
BA
15
CC
CC
1LE
1OE
GND
V
V
1LE
2LE
2OE
2A
GND
V
V
2LE
BA
AB
AB
CC
CC
BA
AB
AB
CC
CC
1A
1A
1A
1A
4
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
2A
2
2A
2A
2A
2A
2A
2A
10
2A
2A
2A
2A
2A
2A
0
2
3
6
8
10
12
15
0
4
5
6
8
12
13
17
16
1A
1A
5
n.c.
2A
2A
3
2A
2A
11
1
7
9
11
13
14
16
1
7
9
14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
MNA562
Fig.1 Pin configuration.
4
2000 Mar 16
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
1OE
AB
1CP
BA
1LE
BA
1CP
AB
1LE
AB
V
handbook, halfpage
CC
1OE
BA
data
input
to internal circuit
C1
1D
C1
1D
MNA473
1B
0
1A
0
C1
1D
C1
1D
18 IDENTICAL CHANNELS
Fig.3 Bus-hold circuit.
2OE
AB
2CP
2LE
2CP
2LE
BA
BA
AB
AB
2OE
BA
C1
C1
1D
2B
0
2A
1D
0
C1
1D
C1
1D
18 IDENTICAL CHANNELS
MNA563
Fig.2 Logic symbol.
2000 Mar 16
5
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
MAX.
2.7
UNIT
VCC
2.5 V range (for maximum speed 2.3
performance at 30 pF output load)
V
V
3.3 V range (for maximum speed 3.0
performance at 50 pF output load)
3.6
VI
DC input voltage
0
VCC
VCC
+85
20
V
V
VO
DC output voltage
ambient temperature
output HIGH or LOW state
0
Tamb
tr, tf
−40
0
°C
input rise and fall time ratios
(∆t/∆V)
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+4.6
+4.6
UNIT
VCC
VI
V
V
DC input voltage
for control pins; note 1
for data input pins; note 1
VI < 0
−0.5
−0.5
−
VCC + 0.5 V
IIK
DC input diode current
−50
mA
mA
IOK
VO
IO
DC output clamping diode current VO < 0; note 1
−
50
DC output voltage
see note 1
−0.5
−
VCC + 0.5 V
DC output sink current
DC VCC or GND current
storage temperature
VO = 0 to VCC
−50
mA
I
CC, IGND
−
±100
+150
1000
mA
°C
Tstg
PD
−65
−
power dissipation per packages
for temperature range:
mW
−40 to +85 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of PD derates linearly with 1.8 mW/K.
2000 Mar 16
6
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
TYP.(1)
UNIT
OTHER VCC (V)
MIN.
MAX.
VIH
VIL
HIGH-level input
voltage
2.3 to 2.7 1.7
2.7 to 3.6 2.0
1.2
1.5
1.2
1.5
−
V
−
V
V
V
LOW-level input
voltage
2.3 to 2.7
2.7 to 3.6
−
−
0.7
0.8
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −6 mA
IO = −12 mA
IO = −12 mA
IO = −12 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 6 mA
2.3 to 3.6
2.3
V
V
V
V
V
V
CC − 0.2 VCC
−
V
V
V
V
V
V
CC − 0.3
CC − 0.6
CC − 0.5
CC − 0.6
CC − 1.0
V
V
V
V
V
CC − 0.08 −
2.3
CC − 0.26 −
CC − 0.14 −
CC − 0.09 −
CC − 0.28 −
2.7
3.0
3.0
VOL
LOW-level output
voltage
2.3 to 3.6
2.3
−
−
−
−
−
−
−
GND
0.07
0.15
0.14
0.27
±0.1
0.1
0.20
0.40
0.70
0.40
0.55
±5
V
V
IO = 12 mA
IO = 12 mA
IO = 24 mA
2.3
V
2.7
V
3.0
V
II
input leakage current VI = VCC or GND
2.3 to 3.6
2.3 to 3.6
µA
µA
IOZ
3-state output
VI = VIH or VIL;
±10
OFF-state current
VO = VCC or GND; note 2
ICC
quiescent supply
current
VI = VCC or GND; IO = 0 2.3 to 3.6
−
−
0.4
80
µA
µA
∆ICC
additional quiescent
supply current given
per data I/O pin with
bus-hold
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
150
750
IBHL
bus-hold LOW
sustaining current
VI = 0.7 V; note 3
VI = 0.8 V; note 3
VI = 1.7 V; note 3
VI = 2.0 V; note 3
note 3
2.3
3.0
2.3
3.0
3.6
45
−
−
−
−
−
−
µA
µA
µA
µA
µA
75
150
−
IBHH
bus-hold HIGH
sustaining current
−45
−75
500
−175
−
IBHLO
IBHHO
bus-hold LOW
overdrive current
bus-hold HIGH
note 3
3.6
−500
−
−
µA
overdrive current
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For I/O ports, the parameter IOZ includes the input leakage current.
3. Valid for data inputs of bus-hold parts.
2000 Mar 16
7
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
AC CHARACTERISTICS
GND = 0 V
TEST CONDITIONS
WAVEFORMS CL
Tamb = −40 to +85 °C
SYMBOL
PARAMETER
UNIT
MIN.
TYP. MAX.
VCC = 2.3 to 2.7 V; tr = tf ≤ 2.0 ns; note 1
tPHL/tPLH
propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 30 pF 1.0
2.8
5.1
6.1
6.1
5.8
6.3
6.2
5.3
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
nLEBA to nAn; nLEAB to nBn
nCPBA to nAn; nCPAB to nBn
3-state output enable time nOEAB to nBn
3-state output enable time nOEBA to nAn
see Figs 5 and 8
see Figs 5 and 8
see Figs 6 and 8
see Figs 6 and 8
1.1
1.0
1.0
1.3
1.5
1.3
3.3
3.3
3.5
3.3
2.5
2.8
2.5
2.5
0.8
2.0
tPZH/tPZL
tPHZ/tPLZ
3-state output disable time nOEAB to nBn see Figs 6 and 8
3-state output disable time nOEBA to nAn see Figs 6 and 8
tW
nLEAB or nLEBA pulse width HIGH
see Figs 5 and 8
see Figs 5 and 8
nCPAB or nCPBA pulse width
HIGH or LOW
−
tsu
set-up time
nAn before nCPAB↑ or nBn before nCPBA
see Figs 7 and 8
see Figs 7 and 8
see Figs 7 and 8
see Figs 7 and 8
see Figs 5 and 8
1.7
1.1
1.7
1.6
150
0.1
0.1
0.3
0.3
330
−
−
−
−
−
ns
↑
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA
ns
↓
th
hold time
ns
nAn after nCPAB↑ or nBn after nCPBA
↑
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA
ns
↓
fmax
maximum clock frequency
MHz
VCC = 2.7 V; tr = tf ≤ 2.5 ns; note 2
tPHL/tPLH
propagation delay
nAn to nBn; nBn to nAn
nLEBA to nAn; nLEAB to nBn
nCPBA to nAn; nCPAB to nBn
see Figs 4 and 8 50 pF
see Figs 5 and 8
see Figs 5 and 8
see Figs 6 and 8
see Figs 6 and 8
−
3.0
3.6
3.4
2.7
3.3
3.6
3.3
0.7
1.4
4.6
5.3
5.6
5.3
6.0
5.7
4.6
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
tPZH/tPZL
3-state output enable time nOEAB to nBn
3-state output enable time nOEBA to nAn
−
−
tPHZ/tPLZ
3-state output disable time nOEAB to nBn see Figs 6 and 8
3-state output disable time nOEBA to nAn see Figs 6 and 8
−
−
tW
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8
see Figs 5 and 8
3.3
3.3
pulse width nCPAB or nCPBA
HIGH or LOW
−
2000 Mar 16
8
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
TEST CONDITIONS
WAVEFORMS CL
see Figs 7 and 8 50 pF +1.4
Tamb = −40 to +85 °C
SYMBOL
tsu
PARAMETER
UNIT
MIN.
TYP. MAX.
set-up time
−0.1
−0.2
0.3
−
−
−
−
−
ns
nAn before nCPAB↑ or nBn before nCPBA
↑
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA
see Figs 7 and 8
see Figs 7 and 8
see Figs 7 and 8
see Figs 5 and 8
+1.0
1.6
ns
↓
th
hold time
ns
nAn after nCPAB↑ or nBn after nCPBA
↑
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA
1.5
0.1
ns
↓
fmax
maximum clock frequency
150
333
MHz
VCC = 3.0 to 3.6 V; tr = tf ≤ 2.5 ns; note 3
tPHL/tPLH
propagation delay
nAn to nBn; nBn to nAn
nLEBA to nAn; nLEAB to nBn
nCPBA to nAn; nCPAB to nBn
see Figs 4 and 8 50 pF 1.0
3.0
3.4
3.3
2.4
2.5
2.9
3.1
0.9
1.1
4.2
4.8
4.9
4.6
5.0
5.0
4.2
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
see Figs 5 and 8
see Figs 5 and 8
see Figs 6 and 8
see Figs 6 and 8
1.3
1.4
1.0
1.1
1.4
1.3
3.3
3.3
tPZH/tPZL
3-state output enable time nOEAB to nBn
3-state output enable time nOEBA to nAn
tPHZ/tPLZ
3-state output disable time nOEAB to nBn see Figs 6 and 8
3-state output disable time nOEBA to nAn see Figs 6 and 8
tW
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8
see Figs 5 and 8
pulse width nCPAB or nCPBA
HIGH or LOW
−
tsu
set-up time
nAn before nCPAB↑ or nBn before nCPBA
see Figs 7 and 8
see Figs 7 and 8
see Figs 7 and 8
see Figs 7 and 8
see Figs 5 and 8
+1.3
1.0
−0.3
0.3
−
−
−
−
−
ns
↑
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA
ns
↓
th
hold time
+1.3
1.2
−0.4
0.1
ns
nAn after nCPAB↑ or nBn after nCPBA
↑
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA
ns
↓
fmax
maximum clock frequency
150
340
MHz
Notes
1. All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
2. All typical values are measured at Tamb = 25 °C.
3. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2000 Mar 16
9
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
AC WAVEFORMS
V
handbook, halfpage
nA , nB
I
n
n
V
M
input
GND
t
t
PHL
PLH
V
OH
nB , nA
n
output
n
V
M
MNA564
V
OL
VCC
2.3 to 2.7 V
2.7 V
VM
VI
0.5 × VCC
1.5 V
VCC
2.7 V
2.7 V
3.0 to 3.6 V
1.5 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Input nAn, nBn to output nBn, nAn propagation delay times.
1/f
max
V
I
nLE , nLE
AB
,
BA
nCP , nCP
V
AB
BA
M
t
input
GND
t
W
t
PHL
PLH
V
OH
nA , nB
n
n
V
M
output
V
OL
MNA565
VCC
VM
VI
2.3 to 2.7 V
2.7 V
0.5 × VCC
1.5 V
VCC
2.7 V
2.7 V
3.0 to 3.6 V
1.5 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Latch enable input (nLEAB, nLEBA) and clock input (nCPAB, nCPBA) to output propagation delays and their
pulse width.
2000 Mar 16
10
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
OE
OE
input
input
AB
V
V
M
M
BA
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
output
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA566
VCC
VM
VX
VY
OH − 150 mV VCC
VI
2.3 to 2.7 V
2.7 V
0.5 × VCC
VOL + 150 mV
VOL + 300 mV
VOL + 300 mV
V
V
V
1.5 V
1.5 V
OH − 300 mV 2.7 V
OH − 300 mV 2.7 V
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state enable and disable times.
V
I
nA , nB
n
input
n
V
M
GND
t
t
h
h
t
t
su
su
V
I
nLE , nLE
AB
,
BA
nCP , nCP
V
M
AB
BA
input
GND
MNA567
The shaded areas indicate when the input is permitted to change for predictable output performance.
VCC
VM
VI
2.3 to 2.7 V
2.7 V
0.5 × VCC
1.5 V
VCC
2.7 V
2.7 V
3.0 to 3.6 V
1.5 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Data set-up and hold times for the nAn and nBn inputs to the nLEAB, nLEBA, nCPAB and nCPBA inputs.
2000 Mar 16
11
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
S1
2 × V
CC
open
GND
V
CC
R
500 Ω
L
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
50 pF
R
L
500 Ω
L
R
T
MNA479
TEST
S1
open
t
PLH/tPHL
PLZ/tPZL
Definitions for test circuit:
RL = Load resistor.
t
2 × VCC
CL = Load capacitance including jig and probe capacitance.
tPHZ/tPZH
GND
RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.8 Load circuitry for switching times.
2000 Mar 16
12
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
PACKAGE OUTLINE
LFBGA114: plastic low profile fine-pitch ball grid array package; 114 balls; body 16 x 5.5 x 1.05 mm SOT537-1
A
B
D
ball A1
index area
A
2
A
E
A
1
detail X
C
e
v M
w M
B
1
b
y
1
y
C
e
v M
A
W
V
U
T
e
R
P
N
M
L
e
K
J
2
H
G
F
E
D
C
B
A
X
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
y
D
E
e
e
v
w
y
0
5
10 mm
1
2
1
2
1
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
16.1
15.9
scale
mm
1.5
4.0
14.4
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
EIAJ
99-12-02
00-03-04
SOT537-1
2000 Mar 16
13
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Mar 16
14
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 16
15
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/01/pp16
Date of release: 2000 Mar 16
Document order number: 9397 750 06819
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