74ALVT162823DGG,11 [NXP]
74ALVT162823 - 18-bit bus-interface D-type flip-flop TSSOP 56-Pin;
| 型号： | 74ALVT162823DGG,11 |
| 厂家： | 
NXP |
| 描述： | 74ALVT162823 - 18-bit bus-interface D-type flip-flop TSSOP 56-Pin 驱动 信息通信管理 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with
30 Ω termination resistors; 3-state
Rev. 02 — 11 August 2005
Product data sheet
1. General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider data
or address paths of buses carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and
master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and
pull-down output structures. This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus receivers or transmitters.
2. Features
■ Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
■ 5 V I/O compatible
■ Ideal where high speed, light loading or increased fan-in are required with MOS
microprocessors
■ Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
■ Live insertion and extraction permitted
■ Power-up 3-state
■ Power-up reset
■ Output capability: +12 mA to −12 mA
■ Outputs include series resistance of 30 Ω making external termination resistors
unnecessary
■ Latch-up protection:
◆ JESD78: exceeds 500 mA
■ ESD protection:
◆ MIL STD 883, method 3015: exceeds 2000 V
◆ Machine Model: exceeds 200 V
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
3. Quick reference data
Table 1:
Quick reference data
Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
3.7
2.9
2.8
2.3
3
Max
Unit
ns
tPLH
propagation delay
CL = 50 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
VI = 0 V or VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nCP to nQx
ns
tPHL
propagation delay
nCP to nQx
ns
ns
Ci
input capacitance
output capacitance
pF
pF
µA
Co
ICC
VI/O = 0 V or 3.0 V
9
quiescent supply
current
outputs disabled;
40
VCC = 2.5 V
outputs disabled;
VCC = 3.3 V
-
70
-
µA
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVT162823DL
−40 °C to +85 °C
SSOP56
plastic shrink small outline package; 56 leads; body SOT371-1
width 7.5 mm
74ALVT162823DGG −40 °C to +85 °C
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
2 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
5. Functional diagram
2
EN1
R2
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1
55
56
27
28
30
29
G3
3C4
EN5
R6
G7
7C8
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
5
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
4D
1,2
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
8D
5,6
001aad242
Fig 1. IEC logic symbol
V
CC
V
CC
V
CC
27 Ω
output
27 Ω
data input
to internal circuit
001aad245
001aad244
Fig 2. Schematic of each output
Fig 3. Bus hold circuit
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
3 of 20
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
nCE
nCP
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
CP
nD
Q
Q
Q
Q
Q
Q
Q
Q
Q
R
R
R
R
R
R
R
R
R
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
001aad243
Fig 4. Logic diagram
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
6. Pinning information
6.1 Pinning
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1MR
1OE
1Q0
GND
1Q1
1Q2
1CP
1CE
1D0
GND
1D1
1D2
2
3
4
5
6
7
V
CC
V
CC
8
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
74ALVT162823
V
CC
V
CC
2Q6
2Q7
GND
2Q8
2OE
2MR
2D6
2D7
GND
2D8
2CE
2CP
001aab433
Fig 5. Pin configuration
6.2 Pin description
Table 3:
Symbol
1MR
1OE
Pin description
Pin
1
Description
1 master reset input (active LOW)
1 output enable input (active LOW)
1 data output 0
2
1Q0
3
GND
1Q1
4
ground (0 V)
5
1 data output 1
1Q2
6
1 data output 2
VCC
7
supply voltage
1Q3
8
1 data output 3
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
5 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Table 3:
Symbol
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
VCC
Pin description …continued
Pin
9
Description
1 data output 4
1 data output 5
ground (0 V)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
1 data output 6
1 data output 7
1 data output 8
2 data output 0
2 data output 1
2 data output 2
ground (0 V)
2 data output 3
2 data output 4
2 data output 5
supply voltage
2Q6
2Q7
GND
2Q8
2OE
2MR
2CP
2CE
2D8
GND
2D7
2D6
VCC
2 data output 6
2 data output 7
ground (0 V)
2 data output 8
2 output enable input (active LOW)
2 master reset input (active LOW)
2 clock pulse input (active rising edge)
2 clock enable input (active LOW)
2 data input 8
ground (0 V)
2 data input 7
2 data input 6
supply voltage
2D5
2D4
2D3
GND
2D2
2D1
2D0
1D8
1D7
1D6
GND
1D5
1D4
1D3
2 data input 5
2 data input 4
2 data input 3
ground (0 V)
2 data input 2
2 data input 1
2 data input 0
1 data input 8
1 data input 7
1 data input 6
ground (0 V)
1 data input 5
1 data input 4
1 data input 3
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
6 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Table 3:
Symbol
VCC
Pin description …continued
Pin
50
51
52
53
54
55
56
Description
supply voltage
1D2
1 data input 2
1D1
1 data input 1
GND
1D0
ground (0 V)
1 data input 0
1CE
1 clock enable input (active LOW)
1 clock pulse input (active rising edge)
1CP
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Operating mode
Input
nOE
L
Output
nMR
L
nCE
X
nCP
X
nDx
nQx
L
Clear
X
h
l
Load and read data
L
H
L
↑
H
L
Hold
L
H
X
H
X
NC
X
X
X
NC
Z
High-impedance
H
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition;
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+4.6
+7.0
+7.0
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state
or HIGH-state
V
IIK
input diode current
output diode current
VI < 0 V
-
-
−50
−50
mA
mA
IOK
VO < 0 V
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
7 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
128
Unit
mA
mA
°C
IO
output current
output in LOW-state
output in HIGH-state
-
-
−64
Tstg
Tj
storage temperature
junction temperature
−65
+150
150
[2]
-
°C
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
VCC = 2.5 V
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.3
-
-
-
-
-
-
-
-
2.7
5.5
-
V
input voltage
0
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
1.7
V
VIL
-
0.7
−8
12
10
+85
V
IOH
-
mA
mA
ns/V
°C
IOL
-
∆t/∆V
Tamb
input transition rise or fall rate outputs enabled
ambient temperature in free air
-
−40
VCC = 3.3 V
VCC
VI
supply voltage
3.0
-
-
-
-
-
-
-
-
3.6
5.5
-
V
input voltage
0
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
2.0
V
VIL
-
0.8
−12
12
V
IOH
-
mA
mA
ns/V
°C
IOL
-
∆t/∆V
Tamb
input transition rise or fall rate outputs enabled
ambient temperature in free air
-
10
−40
+85
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
8 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ
Max Unit
VCC = 2.5 V ± 0.2 V[1]
VIK
input diode voltage
VCC = 2.3 V; IIK = −18 mA
-
−0.85 −1.2
V
V
V
V
VOH
VOL
VRST
HIGH-level output voltage
LOW-level output voltage
VCC = 2.3 V; IOH = −8 mA
1.7
2.5
0.3
0.2
-
VCC = 2.3 V; IOL = 12 mA
-
-
0.5
0.55
[2]
power-up LOW-state output
voltage
VCC = 2.7 V; IO = 1 mA; VI = VCC or GND
ILI
input leakage current
control pins
VCC = 2.7 V; VI = GND
VCC = 2.7 V; VI = 5.5 V
VCC = 2.7 V; VI = 5.5 V
VCC = 2.7 V; VI = VCC
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.5
±1
10
10
1
µA
µA
µA
µA
µA
[3]
[3]
[3]
data pins
VCC = 2.7 V; VI = 0 V
+0.1 −5
IOFF
power-down output current
bus hold current data inputs
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 2.5 V; VI = 0.7 V
VCC = 2.5 V; VI = 1.7 V
+0.1 ±100 µA
[4]
[4]
IHOLD
100
−70
10
-
µA
µA
µA
-
IEX
IPU
IPD
IOZ
external current into output
output HIGH-state when VO > VCC
VO = 5.5 V; VCC = 2.5 V
;
125
[5]
[5]
power-up 3-state output current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
-
1
1
±100 µA
±100 µA
VI = GND or VCC
power-down 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC
;
3-state output current
VCC = 2.7 V; VI = VIL or VIH
output HIGH-state; VO = 2.3 V
output LOW-state; VO = 0.5 V
-
-
0.5
5
µA
µA
+0.5 −5
ICC
quiescent supply current
VCC = 2.7 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
-
0.04 0.1
mA
mA
mA
mA
outputs LOW-state
2.7
4.5
[6]
[7]
outputs disabled
0.04 0.1
0.04 0.4
∆ICC
additional quiescent supply
current per input pin
VCC = 2.3 V to 2.7 V; one input at
CC − 0.6 V, other inputs at VCC or GND
V
Ci
input capacitance
output capacitance
VI = 0 V or VCC
-
-
3
9
-
-
pF
pF
Co
VI/O = 0 V or 3.0 V
VCC = 3.3 V ± 0.3 V[8]
VIK
input diode voltage
VCC = 3.0 V; IIK = −18 mA
-
−0.85 −1.2
V
V
V
V
VOH
VOL
VRST
HIGH-level output voltage
LOW-level output voltage
VCC = 3.0 V; IOH = −12 mA
2.0
2.3
0.5
-
-
VCC = 3.0 V; IOL = 12 mA
-
-
0.8
0.55
[2]
power-up LOW-state output
voltage
VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
9 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ
Max Unit
ILI
input leakage current
control pins
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = 5.5 V
-
0.1
0.1
0.1
0.5
±1
10
10
1
µA
µA
µA
µA
µA
-
[3]
[3]
[3]
data pins
-
VCC = 3.6 V; VI = VCC
-
VCC = 3.6 V; VI = 0 V
-
+0.1 −5
IOFF
power-down output current
bus hold current data inputs
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 3 V; VI = 0.8 V
-
0.1
130
−140
-
±100 µA
[9]
[9]
[9]
IHOLD
75
-
µA
µA
µA
µA
VCC = 3 V; VI = 2.0 V
−75
±500
-
-
VCC = 3.6 V; VI = 0V to 3.6 V
-
IEX
IPU
IPD
IOZ
external current into output
output HIGH-state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
;
10
125
[10]
[10]
power-up 3-state output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
-
1
1
±100 µA
±100 µA
VI = GND or VCC
power-down 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
;
VI = GND or VCC
3-state output current
VCC = 3.6 V; VI = VIL or VIH
output HIGH-state; VO = 3.0 V
output LOW-state; VO = 0.5 V
-
-
0.5
5
µA
µA
+0.5 −5
ICC
quiescent supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
-
0.05 0.1
mA
mA
mA
mA
outputs LOW-state
3.9
5.5
[6]
[7]
outputs disabled
0.06 0.1
0.04 0.4
∆ICC
additional quiescent supply
current per input pin
VCC = 3 V to 3.6 V; one input at VCC − 0.6 V,
other inputs at VCC or GND
Ci
input capacitance
output capacitance
VI = 0 V or VCC
-
-
3
9
-
-
pF
pF
Co
VI/O = 0 V or 3.0 V
[1] All typical values are at VCC = 2.5 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] Not guaranteed.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[6] ICC is measured with outputs pulled up to VCC or pulled down to ground.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[8] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
[9] This is the bus hold overdrive current required to force the input to the opposite logic state.
[10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
10 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
11. Dynamic characteristics
Table 8:
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11;
amb = −40 °C to +85 °C.
Dynamic characteristics
T
Symbol Parameter
Conditions
Min
Typ
Max Unit
VCC = 2.5 V ± 0.2 V[1]
tPLH
tPHL
propagation delay nCP to nQx
see Figure 6
2.1
3.7
5.8
ns
propagation delay
nCP to nQx
see Figure 6
see Figure 8
see Figure 9
see Figure 10
2.0
2.0
2.8
2.0
2.3
2.0
2.8
3.0
4.4
3.4
3.2
2.5
4.6
4.6
6.6
5.2
4.6
3.5
ns
ns
ns
ns
ns
ns
nMR to nQx
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
output enable time to HIGH-level
output enable time to LOW-level
output disable time from HIGH-level see Figure 9
output disable time from LOW-level see Figure 10
set-up time HIGH
nDx to nCP
nCE to nCP
see Figure 7
see Figure 7
1.0
1.0
0.5
0.2
-
-
ns
ns
tsu(L)
th(H)
th(L)
set-up time LOW
nDx to nCP
see Figure 7
see Figure 7
2.0
1.3
-
-
ns
ns
nCE to nCP
+0.5 −0.1
hold time HIGH
nDx to nCP
see Figure 7
see Figure 7
+0.1 −1.4
-
-
ns
ns
nCE to nCP
1.0
0.2
hold time LOW
nDx to nCP
see Figure 7
see Figure 7
see Figure 6
+0.1 −0.5
+1.0 −0.1
-
-
-
ns
ns
ns
nCE to nCP
tWH
tWL
pulse width HIGH nCP
pulse width LOW
nCP
2.0
0.8
see Figure 6
see Figure 8
see Figure 8
3.0
2.0
2.3
2.1
0.8
1.3
-
-
-
ns
ns
ns
nMR
trec
recovery time nMR to nCP
VCC = 3.3 V ± 0.3 V[2]
tPLH propagation delay nCP to nQx
tPHL
see Figure 6
1.8
2.9
4.4
ns
propagation delay
nCP to nQx
see Figure 6
see Figure 8
see Figure 9
see Figure 10
1.6
1.8
2.0
1.7
2.4
1.9
2.3
2.5
3.5
2.8
3.5
2.8
3.6
3.7
5.2
3.8
4.7
3.8
ns
ns
ns
ns
ns
ns
nMR to nQx
tPZH
tPZL
tPHZ
tPLZ
output enable time to HIGH-level
output enable time to LOW-level
output disable time from HIGH-level see Figure 9
output disable time from LOW-level see Figure 10
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
11 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Table 8:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11;
amb = −40 °C to +85 °C.
T
Symbol Parameter
Conditions
Min
Typ
Max Unit
tsu(H)
tsu(L)
th(H)
th(L)
set-up time HIGH
nDx to nCP
nCE to nCP
see Figure 7
see Figure 7
1.0
1.0
0.5
0.1
-
-
ns
ns
set-up time LOW
nDx to nCP
see Figure 7
see Figure 7
1.6
1.1
-
-
ns
ns
nCE to nCP
+0.5 −0.5
hold time HIGH
nDx to nCP
see Figure 7
see Figure 7
+0.1 −0.5
-
-
ns
ns
nCE to nCP
1.0
−0.1
hold time LOW
nDx to nCP
see Figure 7
see Figure 7
see Figure 6
+0.1 −0.7
-
-
-
ns
ns
ns
nCE to nCP
1.0
1.5
0.5
0.7
tWH
tWL
pulse width HIGH nCP
pulse width LOW
nCP
see Figure 6
see Figure 8
see Figure 8
2.5
2.0
2.0
1.4
1.5
1.1
-
-
-
ns
ns
ns
nMR
trec
recovery time nMR to nCP
[1] All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
[2] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
12. Waveforms
1/f
max
V
I
input nCP
0 V
V
V
M
M
t
t
WL
WH
t
t
PLH
PHL
V
OH
output nQx
V
V
M
M
0 V
001aad399
Measurement points are given in Table 9.
VOH is a typical voltage output drop that occur with the output load.
Fig 6. Propagation delay clock input (nCP) to output (nQx), clock pulse width and
maximum clock frequency (nCP)
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
12 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
V
I
input nCP
0 V
V
V
M
M
t
t
t
t
h(L)
su(H)
h(H)
su(L)
V
I
input nDx,
nCE
V
M
V
V
M
V
M
M
0 V
001aad448
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 7. Data set-up and hold times
V
I
V
V
t
input nMR
0 V
M
M
t
WL
rec
V
I
input nCP
0 V
V
M
t
PHL
V
OH
V
output nQx
M
0 V
001aad400
Measurement points are given in Table 9.
VOH is a typical voltage output drop that occur with the output load.
Fig 8. Master reset (MR) pulse width, propagation delay master reset (MR) to output
(nQx) and master reset (MR) to clock (nCP) recovery time
V
I
V
V
M
input nOE
0 V
M
t
t
PZH
PHZ
V
OH
V
Y
output nQx
0 V
V
M
001aad402
Measurement points are given in Table 9.
VOH is a typical voltage output drop that occur with the output load.
Fig 9. 3-state output enable time to HIGH-level and output disable time from HIGH-level
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
13 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
V
I
input nOE
0 V
V
V
M
M
t
t
PZL
PLZ
V
I
output nQx
V
M
V
X
V
OL
001aad404
Measurement points are given in Table 9.
VOL is a typical voltage output drop that occur with the output load.
Fig 10. 3-state output enable time to LOW-level and output disable time from LOW-level
Table 9: Measurement points
Supply voltage
Input
VM
Output
VM
VX
VY
≥ 3 V
1.5 V
1.5 V
VOL + 0.3 V
VOL + 0.3 V
V
OH − 0.3 V
OH − 0.3 V
≤ 2.7 V
0.5 × VCC
0.5 × VCC
V
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
14 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
(t )
f
t
(t )
TLH r
THL
t
(t )
t
(t )
THL f
TLH
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
10 %
0 V
t
W
001aac221
Measurement points are given in Table 9.
a. Input pulse definition
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
L
R
T
mna616
Test data is given in Table 10.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
b. Test circuit
Fig 11. Load circuitry for switching times
Table 10: Test data
Input
Load
CL
VEXT
VI
fi
tW
tr, tf
RL
tPLZ, tPZL tPLH, tPHL tPHZ, tPZH
3.0 V or VCC
whichever is
less
≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω 6 V or
2 × VCC
open
GND
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
15 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
13. Package outline
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
D
E
A
X
c
y
H
v
M
A
E
Z
29
56
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
28
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 18.55
0.13 18.30
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT371-1
MO-118
Fig 12. Package outline SOT371-1 (SSOP56)
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
16 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Fig 13. Package outline SOT364-1 (TSSOP56)
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
17 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
14. Revision history
Table 11: Revision history
Document ID
74ALVT162823_2
Modifications:
Release date Data sheet status
20050811 Product data sheet
Change notice Doc. number
Supersedes
-
-
74ALVT162823_1
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Section 2 “Features”: modified ‘Jedec Std 17’ into ‘JESD78’
• Table 1 and Table 8: changed propagation delays.
74ALVT162823_1
19980827
Product specification
-
9397 750 03577
-
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
18 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
16. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Trademarks
Notice — All referenced brands, product names, service names and
17. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74ALVT162823_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 August 2005
19 of 20
74ALVT162823
Philips Semiconductors
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information . . . . . . . . . . . . . . . . . . . . 19
9
10
11
12
13
14
15
16
17
18
19
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 11 August 2005
Document number: 74ALVT162823_2
Published in The Netherlands
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