74AUP1G09GM,132_技术文档

74AUP1G09

Low-power 2-input AND gate with open-drain

Rev. 4 — 28 June 2012

Product data sheet

1. General description

The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The

output of the device is an open-drain and can be connected to other open-drain outputs to

implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF

.

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 μA (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial Power-down mode operation

 Multiple package options

 Specified from −40 °C to +85 °C and −40 °C to +125 °C

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AUP1G09GW

74AUP1G09GM

74AUP1G09GF

74AUP1G09GN

74AUP1G09GS

74AUP1G09GX

−40 °C to +125 °C

TSSOP5

plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

SOT353-1

XSON6

X2SON5

plastic extremely thin small outline package; no leads; SOT886

6 terminals; body 1 × 1.45 × 0.5 mm

plastic extremely thin small outline package; no leads; SOT891

6 terminals; body 1 × 1 × 0.5 mm

extremely thin small outline package; no leads;

6 terminals; body 0.9 × 1.0 × 0.35 mm

SOT1115

SOT1202

SOT1226

extremely thin small outline package; no leads;

6 terminals; body 1.0 × 1.0 × 0.35 mm

X2SON5: plastic thermal enhanced extremely thin

small outline package; no leads; 5 terminals;

body 0.8 × 0.8 × 0.35 mm

4. Marking

Table 2.

Marking

Type number

Marking code^[1]

74AUP1G09GW

74AUP1G09GM

74AUP1G09GF

74AUP1G09GN

74AUP1G09GS

74AUP1G09GX

p9

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

Y

A

1

B

A

4

1

2

Y

&

2

4

GND

B

001aad598

001aad599

001aad600

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram

74AUP1G09

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Product data sheet

Rev. 4 — 28 June 2012

2 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

6. Pinning information

6.1 Pinning

74AUP1G09

B

A

1

2

3

6

5

4

V

CC

1

2

3

5

4

B

A

V

Y

CC

n.c.

Y

GND

001aai729

Transparent top view

001aai728

Fig 4. Pin configuration SOT353-1

Fig 5. Pin configuration SOT886

74AUP1G09

B

A

1

2

5

4

V

Y

CC

B

A

1

2

3

6

5

4

V

CC

3

GND

n.c.

Y

GND

001aai730

aaa-003001

Transparent top view

Fig 6. Pin configuration SOT891, SOT1115 and

SOT1202

Fig 7. Pin configuration SOT1226 (X2SON5)

6.2 Pin description

Table 3.

Symbol

Pin description

Description

TSSOP5 and X2SON5 XSON6

B

1

2

3

4

-

1

2

3

4

5

6

data input

A

data input

GND

Y

ground (0 V)

data output

not connected

supply voltage

n.c.

V_CC

5

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Product data sheet

Rev. 4 — 28 June 2012

3 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

7. Functional description

Table 4.

Function table^[1]

Input

Output

A

L

B

L

Y

L

Z

L

H

L

H

[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state.

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

-

Max

+4.6

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+4.6

-

I_OK

output clamping current

output voltage

V_O< 0 V

mA

V

V_O

Active mode and Power-down mode

V_O= 0 V to V_CC

+4.6

+20

+50

-

I_O

output current

mA

°C

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

−50

−65

-

storage temperature

total power dissipation

+150

250

[2]

T_amb= −40 °C to +125 °C

mW

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP5 packages: above 87.5 °C the value of P_totderates linearly with 4.0 mW/K.

For XSON6 and X2SON5 packages: above 118 °C the value of P_totderates linearly with 7.8 mW/K.

9. Recommended operating conditions

Table 6.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

0.8

0

Max

3.6

Unit

V

supply voltage

input voltage

V_I

3.6

V

V_O

output voltage

ambient temperature

Active mode and Power-down mode

0

3.6

V

T_amb

Δt/ΔV

−40

0

+125

200

°C

ns/V

input transition rise and fall rate V_CC= 0.8 V to 3.6 V

74AUP1G09

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Product data sheet

Rev. 4 — 28 June 2012

4 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

10. Static characteristics

Table 7.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 25 °C

V_IH

HIGH-level input voltage

V_CC= 0.8 V

0.7V_CC

-

V

V_CC= 0.9 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65V_CC

-

1.6

-

V_CC= 3.0 V to 3.6 V

2.0

-

V_IL

LOW-level input voltage

LOW-level output voltage

V_CC= 0.8 V

-

0.3V_CC

0.35V_CC

0.7

V_CC= 0.9 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

0.9

V_OL

V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

-

0.1

V

0.3V_CC

0.31

0.44

0.31

0.44

0.1

V

I_I

input leakage current

μA

I_OZ

OFF-state output current

V_I= V_IHor V_IL; V_O= 0 V to 3.6 V;

V_CC= 3.6 V

0.1

I_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

-

0.2

μA

ΔI_OFF

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V;

V_CC= 0 V to 0.2 V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

-

0.5

μA

ΔI_CC

C_I

additional supply current

input capacitance

V_I= V_CC− 0.6 V; I_O= 0 A; V_CC= 3.3 V

V_CC= 0 V to 3.6 V; V_I= GND or V_CC

output enabled; V_O= GND; V_CC= 0 V

output disabled; V_O= GND; V_CC= 0 V

-

40

-

μA

pF

0.8

1.7

1.1

C_O

output capacitance

-

T_amb= −40 °C to +85 °C

V_IHHIGH-level input voltage

V_CC= 0.8 V

0.7V_CC

-

V

V_CC= 0.9 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 0.8 V

0.65V_CC

-

1.6

-

2.0

-

V_IL

LOW-level input voltage

-

0.3V_CC

0.35V_CC

0.7

V_CC= 0.9 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

0.9

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Product data sheet

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74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_OL

LOW-level output voltage

V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

-

0.1

V

0.3V_CC

0.37

0.35

0.33

0.45

0.33

0.45

0.5

V

I_I

input leakage current

μA

I_OZ

OFF-state output current

V_I= V_IHor V_IL; V_O= 0 V to 3.6 V;

V_CC= 3.6 V

0.5

I_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

-

0.5

0.6

μA

ΔI_OFF

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V;

V_CC= 0 V to 0.2 V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

-

0.9

50

μA

ΔI_CC

additional supply current

V_I= V_CC− 0.6 V; I_O= 0 A; V_CC= 3.3 V

T_amb= −40 °C to +125 °C

V_IHHIGH-level input voltage

V_CC= 0.8 V

0.75V_CC

-

V

V_CC= 0.9 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.7V_CC

-

1.6

-

V_CC= 3.0 V to 3.6 V

2.0

-

V_IL

LOW-level input voltage

LOW-level output voltage

V_CC= 0.8 V

-

0.25V_CC

0.3V_CC

0.7

V_CC= 0.9 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

0.9

V_OL

V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

-

0.11

V

0.33V_CC

0.41

0.39

0.36

0.50

0.36

0.50

0.75

V

I_I

input leakage current

μA

I_OZ

OFF-state output current

V_I= V_IHor V_IL; V_O= 0 V to 3.6 V;

V_CC= 3.6 V

I_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

-

0.75

μA

74AUP1G09

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Product data sheet

Rev. 4 — 28 June 2012

6 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

ΔI_OFFadditional power-off

Conditions

Min

Typ

Max

0.75

Unit

V_Ior V_O= 0 V to 3.6 V;

V_CC= 0 V to 0.2 V

-

μA

leakage current

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

-

1.4

75

μA

V_CC= 0.8 V to 3.6 V

ΔI_CC

additional supply current

V_I= V_CC− 0.6 V; I_O= 0 A; V_CC= 3.3 V

11. Dynamic characteristics

Table 8.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min

Typ^[1]

Max

Min

Max

(85 °C) (125 °C)

C_L= 5 pF

[2]

t_pd

propagation delay A or B to Y; see Figure 8

V_CC= 0.8 V

-

13.5

4.6

3.3

2.9

2.2

2.3

-

ns

V_CC= 1.1 V to 1.3 V

1.9

1.5

1.2

1.0

0.9

10.4

6.5

5.1

3.8

4.0

1.8

1.4

1.1

0.9

0.8

11.4

7.4

5.9

4.5

12.6

8.2

6.5

4.9

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

C_L= 10 pF

t_pd

propagation delay A or B to Y; see Figure 8

V_CC= 0.8 V

-

16.3

5.6

4.1

3.8

2.9

3.2

-

ns

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

2.3

1.8

1.6

1.4

1.3

12.3

7.6

6.1

4.6

5.7

2.1

1.7

1.4

1.2

1.1

13.7

8.8

7.1

5.4

6.4

15.1

9.7

7.8

5.9

7.0

C_L= 15 pF

t_pd

propagation delay A or B to Y; see Figure 8

V_CC= 0.8 V

-

19.0

6.6

4.8

4.6

3.6

4.1

-

ns

V_CC= 1.1 V to 1.3 V

2.6

2.1

1.9

1.6

14.2

8.7

7.6

5.6

7.5

2.4

1.9

1.7

1.5

1.4

15.8

10.1

8.5

17.4

11.1

9.3

6.9

9.1

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

6.3

V_CC= 3.0 V to 3.6 V

8.3

C_L= 30 pF

74AUP1G09

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Product data sheet

Rev. 4 — 28 June 2012

7 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

Table 8.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min

Typ^[1]

Max

Min

Max

(85 °C) (125 °C)

[2]

t_pd

propagation delay A or B to Y; see Figure 8

V_CC= 0.8 V

-

27.0

9.5

7.0

5.4

6.5

-

ns

V_CC= 1.1 V to 1.3 V

3.6

2.9

2.6

2.4

2.3

19.5

11.5

12.1

8.9

3.2

2.6

2.3

2.1

21.8

13.6

13.3

9.9

24.0

15.0

14.6

10.9

15.3

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

12.7

13.9

C_L= 5 pF, 10 pF, 15 pF and 30 pF

C_PDpower dissipation f_i= 1 MHz;

capacitance V_I= GND to V_CC

[3]

V_CC= 0.8 V

-

0.6

0.7

0.8

0.9

1.1

1.4

-

pF

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

[2] _pdis the same as t_PZLand t_PLZ

.

t

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N where:

f_i= input frequency in MHz;

V_CC= supply voltage in V;

N = number of inputs switching.

12. Waveforms

V

I

A, B input

Y output

V

M

t

GND

t

PLZ

PZL

V

CC

V

M

V

X

V

OL

001aai731

Measurement points are given in Table 9.

V_OLis a typical output voltage level that occurs with the output load.

Fig 8. The data input (A or B) to output (Y) propagation delays

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Product data sheet

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8 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

Table 9.

Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

V_X

0.8 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

0.5V_CC

V_OL+ 0.1 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V

CC

V

EXT

5 kΩ

V

O

I

G

DUT

R

T

C

L

R

L

001aac521

Test data is given in Table 10.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 9. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

V_CC

Load

V_EXT

[1]

C_L

R_L

t_PLH, t_PHL

t_PZH, t_PHZ

t_PZL, t_PLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

5 kΩ or 1 MΩ open

GND

2V_CC

[1] For measuring enable and disable times R_L= 5 kΩ.

For measuring propagation delays, set-up and hold times, and pulse width, R_L= 1 MΩ.

74AUP1G09

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Product data sheet

Rev. 4 — 28 June 2012

9 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

13. Package outline

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm

SOT353-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

4

A

2

A

(A )

3

A

1

θ

L

p

1

3

e

w M

b

p

detail X

e

1

0

1.5

3 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

A

b

c

D

E

e

1

H

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

E

max.

0.1

0

1.0

0.8

0.30

0.15

0.25

0.08

2.25

1.85

1.35

1.15

2.25

2.0

0.46

0.21

0.60

0.15

7°

0°

mm

1.1

0.65

1.3

0.15

0.425

0.3

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-09-01

03-02-19

SOT353-1

MO-203

SC-88A

Fig 10. Package outline SOT353-1 (TSSOP5)

74AUP1G09

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Product data sheet

Rev. 4 — 28 June 2012

10 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

SOT886

b

1

2

3

4x

(2)

L

1

e

6

5

4

e

1

e

1

6x

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

Dimensions (mm are the original dimensions)

(1)

Unit

A

1

b

D

E

e

L

1

max 0.5 0.04 0.25 1.50 1.05

0.35 0.40

0.20 1.45 1.00 0.6 0.5 0.30 0.35

0.17 1.40 0.95 0.27 0.32

mm nom

min

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

sot886_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

MO-252

JEITA

04-07-22

12-01-05

SOT886

Fig 11. Package outline SOT886 (XSON6)

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

11 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

SOT891

b

1

2

3

4×

(1)

L

1

e

6

5

4

e

1

e

1

6×

A

(1)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

1

UNIT

b

D

E

e

L

1

max max

0.20 1.05 1.05

0.12 0.95 0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.55 0.35

Note

1. Can be visible in some manufacturing processes.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

05-04-06

07-05-15

SOT891

Fig 12. Package outline SOT891 (XSON6)

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

12 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

XSON6: extremely thin small outline package; no leads;

6 terminals; body 0.9 x 1.0 x 0.35 mm

SOT1115

b

3

(2)

(4×)

1

2

L

1

e

6

5

4

e

1

e

1

(2)

(6×)

A

1

A

D

E

terminal 1

index area

0

L

0.5

scale

1 mm

Dimensions

Unit

(1)

A

b

D

E

e

1

L

1

max 0.35 0.04 0.20 0.95 1.05

0.35 0.40

0.15 0.90 1.00 0.55 0.3 0.30 0.35

0.12 0.85 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1115_po

References

Outline

version

European

Issue date

projection

IEC

JEDEC

JEITA

10-04-02

10-04-07

SOT1115

Fig 13. Package outline SOT1115 (XSON6)

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

13 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

XSON6: extremely thin small outline package; no leads;

6 terminals; body 1.0 x 1.0 x 0.35 mm

SOT1202

b

3

(2)

1

2

(4×)

L

1

e

6

5

4

e

1

e

1

(2)

(6×)

A

1

A

D

E

terminal 1

index area

0

L

0.5

1 mm

scale

Dimensions

Unit

(1)

A

b

D

E

e

1

L

1

max 0.35 0.04 0.20 1.05 1.05

0.35 0.40

0.15 1.00 1.00 0.55 0.35 0.30 0.35

0.12 0.95 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1202_po

References

Outline

version

European

Issue date

projection

IEC

JEDEC

JEITA

10-04-02

10-04-06

SOT1202

Fig 14. Package outline SOT1202 (XSON6)

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

14 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;

5 terminals; body 0.8 x 0.8 x 0.35 mm

SOT1226

D

A

B

X

A

E

A

1

A

3

detail X

terminal 1

index area

e

C

v

C

A

B

b

y

C

1

w

1

2

terminal 1

index area

3

L

5

4

0

1 mm

scale

v

Dimensions

Unit

max 0.35 0.04 0.128 0.85 0.30 0.85 0.27

(1)

A

1

A

3

D

E

b

e

k

L

w

y

1

h

0.27

0.22 0.1 0.05 0.05 0.05

0.20 0.17

mm nom

min

0.80 0.25 0.80 0.22 0.48

0.040 0.75 0.20 0.75 0.17

Note

1. Dimension A is including plating thickness.

2. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1226_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

EIAJ

12-04-10

12-04-25

SOT1226

Fig 15. Package outline SOT1226 (X2SON5)

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

15 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

14. Abbreviations

Table 11. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

ESD

HBM

MM

15. Revision history

Table 12. Revision history

Document ID

74AUP1G09 v.4

Modifications:

Release date

20120628

Data sheet status

Change notice

Supersedes

Product data sheet

-

74AUP1G09 v.3

• Added type number 74AUP1G09GX (SOT1226)

• Package outline drawing of SOT886 (Figure 11) modified.

74AUP1G09 v.3

Modifications:

20111128

Product data sheet

-

74AUP1G09 v.2

• Legal pages updated.

74AUP1G09 v.2

74AUP1G09 v.1

20100709

20090115

Product data sheet

-

74AUP1G09 v.1

-

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

16 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

16.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

17 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74AUP1G09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 June 2012

18 of 19

74AUP1G09

NXP Semiconductors

Low-power 2-input AND gate with open-drain

18. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 June 2012

Document identifier: 74AUP1G09


型号：	74AUP1G09GM,132
厂家：	NXP
描述：	74AUP1G09 - Low-power 2-input AND gate with open-drain SON 6-Pin 栅光电二极管逻辑集成电路触发器
文件：	总19页 (文件大小：335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AUP1G09GM,132 [NXP]

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