74AUP1G125GW-Q100 [NXP]
AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, 1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5;
| 型号： | 74AUP1G125GW-Q100 |
| 厂家： | 
NXP |
| 描述： | AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, 1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总19页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G125-Q100
Low-power buffer/line driver; 3-state
Rev. 1 — 20 March 2013
Product data sheet
1. General description
The 74AUP1G125-Q100 provides a single non-inverting buffer/line driver with 3-state
output. The 3-state output is controlled by the output enable input (OE). A HIGH level at
pin OE causes the output to assume a high-impedance OFF-state. This device has the
input-disable feature, which allows floating input signals. The inputs are disabled when the
output enable input OE) is HIGH.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
Input-disable feature allows floating input conditions
IOFF circuitry provides partial Power-down mode operation
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74AUP1G125GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
SOT353-1
body width 1.25 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G125GW-Q100
pM
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
A
Y
4
2
1
A
Y
2
1
4
OE
EN
OE
mna118
mna119
001aad068
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
ꢀꢁꢂꢃꢄꢅꢆꢅꢇꢈꢉꢊꢅꢋꢋ
ꢉ
ꢊ
ꢋ
ꢌ
ꢀꢁ
ꢄ
ꢂ
ꢃꢃ
ꢍ
ꢅꢆꢇ
ꢈ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
Fig 4. Pin configuration SOT353-1
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
2 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
6.2 Pin description
Table 3.
Symbol
OE
Pin description
Pin
1
Description
output enable input
data input
A
2
GND
Y
3
ground (0 V)
data output
4
VCC
5
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
OE
L
Output
A
L
Y
L
L
H
X
H
Z
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = Don’t care;
Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
50
0.5
0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1]
[1]
VO
Active mode
VCC + 0.5
+4.6
20
+50
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
50
65
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
3 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
V
supply voltage
input voltage
output voltage
VI
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
0
+125
200
C
ns/V
t/V
input transition rise and fall rate VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 VCC
0.35 VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.1
0.75 VCC
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VIH or VIL
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 A; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
V
V
0.3 VCC
0.31
0.31
0.31
0.44
0.31
0.44
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
4 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
0.1
0.1
Unit
A
II
input leakage current
OFF-state output current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
IOZ
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
A
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
0.2
0.2
A
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
-
-
0.5
40
110
1
A
A
A
A
pF
[1]
[1]
[2]
ICC
additional supply current
data input; VI = VCC 0.6 V; IO = 0 A;
-
V
CC = 3.3 V
OE input; VI = VCC 0.6 V; IO = 0 A;
CC = 3.3 V
-
V
all inputs; VI = GND to 3.6 V;
OE = VCC; VCC = 0.8 V to 3.6 V
-
CI
input capacitance
output capacitance
output enabled
VCC = 0 V to 3.6 V; VI = GND or VCC
0.9
-
CO
VO = GND; VCC = 0 V
-
-
1.7
1.5
-
-
pF
pF
output disabled
VCC = 0 V to 3.6 V; VO = GND or VCC
Tamb = 40 C to +85 C
VIH HIGH-level input voltage
VCC = 0.8 V
0.70 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 VCC
0.35 VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.1
0.7 VCC
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
1.30
1.97
1.85
2.67
2.55
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
5 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 VCC
0.37
0.35
0.33
0.45
0.33
0.45
0.5
0.5
V
V
V
V
V
V
V
II
input leakage current
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
0.5
0.6
A
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
-
-
-
-
0.9
50
120
1
A
A
A
A
[1]
[1]
[2]
ICC
additional supply current
data input; VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
OE input; VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
all inputs; VI = GND to 3.6 V;
OE = VCC; VCC = 0.8 V to 3.6 V
Tamb = 40 C to +125 C
VIH HIGH-level input voltage
VCC = 0.8 V
0.75 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.25 VCC
0.30 VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
0.6 VCC
0.93
-
-
-
-
-
-
-
1.17
1.77
1.67
2.40
2.30
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
6 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
0.75
0.75
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
0.75
0.75
A
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
-
-
-
-
1.4
75
180
1
A
A
A
A
[1]
[1]
[2]
ICC
additional supply current
data input; VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
OE input; VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
all inputs; VI = GND to 3.6 V;
OE = VCC; VCC = 0.8 V to 3.6 V
[1] One input at VCC 0.6 V, other input at VCC or GND.
[2] To show ICC remains very low when the input-disable feature is enabled.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 25 C; CL = 5 pF
[2]
tpd
propagation delay
A to Y; see Figure 5
VCC = 0.8 V
-
20.6
5.5
3.9
3.2
2.6
2.4
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.8
2.2
1.9
1.6
1.4
10.5
6.1
4.8
3.6
3.1
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
7 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
[3]
ten
enable time
OE to Y; see Figure 6
VCC = 0.8 V
-
69.9
6.1
4.2
3.4
2.6
2.4
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 0.8 V
3.1
2.5
2.1
1.8
1.7
11.8
6.6
5.1
3.7
3.1
[4]
tdis
disable time
-
14.3
4.3
3.2
3.0
2.2
2.5
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.7
2.1
2.0
1.4
1.7
6.5
4.4
4.3
2.9
3.2
Tamb = 25 C; CL = 10 pF
propagation delay
[2]
[3]
[4]
tpd
ten
tdis
A to Y; see Figure 5
VCC = 0.8 V
-
24.0
6.4
4.5
3.8
3.2
3.0
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 0.8 V
3.2
2.1
1.9
2.1
1.8
12.3
7.3
5.5
4.2
3.8
enable time
-
73.7
6.9
4.8
3.9
3.2
3.0
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 0.8 V
3.6
2.3
2.0
1.8
1.7
13.5
7.7
5.8
4.3
3.9
disable time
-
32.7
5.4
4.1
4.2
3.0
3.8
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.4
2.2
2.2
1.7
2.1
7.9
5.5
5.6
3.8
4.8
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
8 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol
Tamb = 25 C; CL = 15 pF
propagation delay
Parameter
Conditions
Min
Typ [1]
Max
Unit
[2]
[3]
[4]
tpd
ten
tdis
A to Y; see Figure 5
VCC = 0.8 V
-
27.4
7.2
5.1
4.3
3.7
3.5
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 0.8 V
3.6
3.0
2.2
2.0
2.0
14.1
8.1
6.3
4.9
4.4
enable time
-
77.5
7.7
5.3
4.4
3.6
3.5
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 0.8 V
4.0
3.0
2.3
2.1
2.0
15.2
8.4
6.5
5.0
4.5
disable time
-
60.8
6.5
5.0
5.3
3.8
5.0
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.3
3.0
3.0
2.1
2.9
9.2
6.5
6.6
4.9
6.2
Tamb = 25 C; CL = 30 pF
tpd propagation delay
[2]
A to Y; see Figure 5
VCC = 0.8 V
-
37.4
9.5
6.7
5.6
4.8
4.6
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 0.8 V
4.8
4.0
2.9
2.7
2.7
19.0
10.8
8.4
6.3
5.8
[3]
ten
enable time
-
88.9
9.9
6.8
5.6
4.8
4.6
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
5.2
4.0
3.0
2.7
2.7
19.8
10.8
8.5
6.5
6.0
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Low-power buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
[4]
tdis
disable time
OE to Y; see Figure 6
VCC = 0.8 V
-
49.9
9.9
7.7
8.7
6.2
8.7
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.0
4.4
5.1
3.6
5.2
13.3
9.6
11.1
7.4
10.5
Tamb = 25 C
CPD
[5]
power dissipation capacitance f = 1 MHz; VI = GND to VCC
output enabled
VCC = 0.8 V
-
-
-
-
-
-
2.7
2.8
2.9
3.0
3.6
4.2
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
[2] tpd is the same as tPLH and tPHL
[3] ten is the same as tPZH and tPZL
[4] dis is the same as tPHZ and tPLZ
.
.
.
t
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Max
Min
Max
CL = 5 pF
[1]
tpd
propagation delay
A to Y; see Figure 5
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.5
2.0
1.7
1.4
1.2
11.7
7.3
6.1
4.3
3.9
2.5
2.0
1.7
1.4
1.2
12.9
8.1
6.7
4.9
4.4
ns
ns
ns
ns
ns
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Low-power buffer/line driver; 3-state
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Max
Min
Max
[2]
ten
enable time
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.9
2.3
2.0
1.7
1.7
13.9
7.7
6.2
4.5
3.5
2.9
2.3
2.0
1.7
1.7
15.4
8.3
6.8
5.0
3.9
ns
ns
ns
ns
ns
[3]
tdis
disable time
2.7
2.1
2.0
1.4
1.7
7.3
5.1
5.0
3.3
3.4
2.7
2.1
2.0
1.4
1.7
8.2
5.7
5.7
4.1
3.9
ns
ns
ns
ns
ns
CL = 10 pF
[1]
[2]
[3]
tpd
propagation delay
A to Y; see Figure 5
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.0
1.9
1.7
1.6
1.6
13.8
8.5
6.8
5.3
4.6
3.0
1.9
1.7
1.6
1.6
15.2
9.4
7.6
5.9
5.2
ns
ns
ns
ns
ns
ten
enable time
3.4
2.2
1.9
1.7
1.7
15.8
8.6
6.8
5.3
4.3
3.4
2.2
1.9
1.7
1.7
17.5
9.4
7.4
5.9
4.8
ns
ns
ns
ns
ns
tdis
disable time
3.4
2.2
1.9
1.7
1.7
8.8
6.2
6.3
4.5
5.0
3.4
2.2
1.9
1.7
1.7
9.9
7.1
7.1
5.1
5.6
ns
ns
ns
ns
ns
CL = 15 pF
[1]
tpd
propagation delay
A to Y; see Figure 5
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.3
2.5
2.0
1.8
1.8
15.8
9.8
7.9
6.0
5.4
3.3
2.5
2.0
1.8
1.8
17.5
10.9
8.8
ns
ns
ns
ns
ns
6.7
6.1
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NXP Semiconductors
Low-power buffer/line driver; 3-state
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Max
Min
Max
[2]
ten
enable time
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.7
2.5
2.1
2.0
1.9
17.6
9.8
7.7
6.1
4.9
3.7
2.5
2.1
2.0
1.9
19.6
10.7
8.5
ns
ns
ns
ns
ns
6.8
5.5
[3]
tdis
disable time
3.7
2.5
2.1
2.0
1.9
10.3
7.4
7.4
5.1
6.6
3.7
2.5
2.1
2.0
1.9
11.6
8.4
8.9
6.4
7.4
ns
ns
ns
ns
ns
CL = 30 pF
[1]
[2]
[3]
tpd
propagation delay
A to Y; see Figure 5
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
OE to Y; see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.4
3.0
2.6
2.5
2.5
21.6
13.0
10.3
7.8
4.4
3.0
2.6
2.5
2.5
24.0
14.5
11.5
8.7
ns
ns
ns
ns
ns
7.5
8.3
ten
enable time
4.8
3.1
2.8
2.6
2.6
22.8
12.6
10.2
7.8
4.8
3.1
2.8
2.6
2.6
25.3
14.1
11.3
8.8
ns
ns
ns
ns
ns
6.9
7.7
tdis
disable time
4.8
3.1
2.8
2.6
2.6
14.8
10.7
12.4
8.6
4.8
3.1
2.8
2.6
2.6
16.5
12.1
13.8
9.6
ns
ns
ns
ns
ns
10.8
13.1
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] dis is the same as tPHZ and tPLZ
.
.
t
.
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Low-power buffer/line driver; 3-state
12. Waveforms
V
I
V
A input
M
GND
t
t
PLH
PHL
Y output
V
M
001aad070
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage drops that occur with the output load.
Fig 5. The data input (A) to output (Y) propagation delays
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna644
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VI
tr = tf
VX
VY
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
0.5 VCC
0.5 VCC
0.5 VCC
VCC
VCC
VCC
3.0 ns
3.0 ns
3.0 ns
0.5 VCC
0.5 VCC
0.5 VCC
VOL 0.1 V
VOL 0.15 V
VOL 0.3 V
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
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Product data sheet
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NXP Semiconductors
Low-power buffer/line driver; 3-state
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M
GND
2 VCC
[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
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Product data sheet
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NXP Semiconductors
Low-power buffer/line driver; 3-state
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 8. Package outline SOT353-1 (TSSOP5)
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Product data sheet
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NXP Semiconductors
Low-power buffer/line driver; 3-state
14. Abbreviations
Table 12. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
ESD
HBM
MIL
MM
Machine Model
15. Revision history
Table 13. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1G125_Q100 v.1 20130320
Product data sheet
-
-
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Product data sheet
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NXP Semiconductors
Low-power buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
16.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
17 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP1G125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2013
18 of 19
74AUP1G125-Q100
NXP Semiconductors
Low-power buffer/line driver; 3-state
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 March 2013
Document identifier: 74AUP1G125_Q100
相关型号：
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