74AUP1G38GW-G [NXP]
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74AUP1G38
Low-power 2-input NAND gate (open drain)
Rev. 03 — 22 June 2009
Product data sheet
1. General description
The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The
output of the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G38GW
74AUP1G38GM
74AUP1G38GF
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
XSON6
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G38GW
74AUP1G38GM
74AUP1G38GF
aB
aB
aB
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Y
A
B
1
2
A
B
1
2
&
Y
4
4
GND
001aab716
001aab717
001aab715
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
2 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
6. Pinning information
6.1 Pinning
74AUP1G38
74AUP1G38
A
B
1
2
3
6
5
4
V
CC
74AUP1G38
1
2
3
5
4
A
B
V
Y
A
B
1
2
3
6
5
4
V
CC
CC
n.c.
Y
n.c.
Y
GND
GND
GND
001aaf533
001aaf534
Transparent top view
Transparent top view
001aaf532
Fig 4. Pin configuration
SOT353-1 (TSSOP5)
Fig 5. Pin configuration SOT886
(XSON6)
Fig 6. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP5
XSON6
A
1
2
3
4
-
1
2
3
4
5
6
data input
B
data input
GND
Y
ground (0 V)
data output
not connected
supply voltage
n.c.
VCC
5
7. Functional description
Table 4.
Function table[1]
Input
Output
A
L
B
L
Y
Z
Z
Z
L
L
H
L
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF state.
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
3 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
VO
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
+20
+50
-
IO
output current
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
V
supply voltage
input voltage
VI
3.6
V
VO
output voltage
ambient temperature
Active mode and Power-down mode
0
3.6
V
Tamb
∆t/∆V
−40
0
+125
200
°C
ns/V
input transition rise and fall rate VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
4 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.1
V
V
V
V
V
V
V
II
input leakage current
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL (and at least one input
LOW); VO = 0 V to 3.6 V; VCC = 0 V to
3.6 V
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
±0.2
±0.2
µA
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
0.5
µA
V
∆ICC
CI
additional supply current
input capacitance
VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V
VCC = 0 V to 3.6 V; VI = GND or VCC
output enabled; VO = GND; VCC = 0 V
output disabled; VO = GND; VCC = 0 V
-
-
-
-
-
40
-
µA
pF
pF
pF
0.8
1.7
1.1
CO
output capacitance
-
-
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
1.6
-
VCC = 3.0 V to 3.6 V
2.0
-
VIL
LOW-level input voltage
LOW-level output voltage
VCC = 0.8 V
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOL
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
V
V
µA
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
II
input leakage current
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
5 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IOZ
OFF-state output current
VI = VIH or VIL (and at least one input
LOW); VO = 0 V to 3.6 V; VCC = 0 V to
3.6 V
-
-
±0.5
µA
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
±0.5
±0.6
µA
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.70 × VCC
-
1.6
-
VCC = 3.0 V to 3.6 V
2.0
-
VIL
LOW-level input voltage
LOW-level output voltage
VCC = 0.8 V
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOL
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL (and at least one input
LOW); VO = 0 V to 3.6 V; VCC = 0 V to
3.6 V
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
±0.75
±0.75
µA
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
6 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 8
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
Max
(85 °C) (125 °C)
CL = 5 pF
[2]
[2]
[2]
[2]
tpd
propagation delay A or B to Y; see Figure 7
VCC = 0.8 V
-
13.5
4.6
3.3
2.9
2.2
2.3
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
1.9
1.5
1.2
1.0
0.9
10.4
6.5
5.1
3.8
4.0
1.8
1.4
1.1
0.9
0.8
11.4
7.4
5.9
4.5
4.5
12.6
8.2
6.5
4.9
4.9
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tpd
propagation delay A or B to Y; see Figure 7
VCC = 0.8 V
-
16.3
5.6
4.1
3.8
2.9
3.2
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.3
1.8
1.6
1.4
1.3
12.3
7.6
6.1
4.6
5.7
2.1
1.7
1.4
1.2
1.1
13.7
8.8
7.1
5.4
6.4
15.1
9.7
7.8
5.9
7.0
CL = 15 pF
tpd
propagation delay A or B to Y; see Figure 7
VCC = 0.8 V
-
19.0
6.6
4.8
4.6
3.6
4.1
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
2.6
2.1
1.9
1.6
1.6
14.2
8.7
7.6
5.6
7.5
2.4
1.9
1.7
1.5
1.4
15.8
10.1
8.5
17.4
11.1
9.3
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
6.3
6.9
VCC = 3.0 V to 3.6 V
8.3
9.1
CL = 30 pF
tpd
propagation delay A or B to Y; see Figure 7
VCC = 0.8 V
-
27.0
9.5
7.0
7.0
5.4
6.5
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.6
2.9
2.6
2.4
2.3
19.5
11.5
12.1
8.9
3.2
2.6
2.3
2.1
2.1
21.8
13.6
13.3
9.9
24.0
15.0
14.6
10.9
15.3
12.7
13.9
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
7 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 8
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
Max
(85 °C) (125 °C)
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation fi = 1 MHz;
capacitance VI = GND to VCC
[3]
VCC = 0.8 V
-
-
-
-
-
-
0.6
0.7
0.8
0.9
1.1
1.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPZL and tPLZ
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N where:
fi = input frequency in MHz;
VCC = supply voltage in V;
N = number of inputs switching.
12. Waveforms
V
I
A, B input
Y output
V
M
t
GND
t
PLZ
PZL
V
CC
V
M
V
X
V
OL
001aab719
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The data input (A or B) to output (Y) propagation delays
Table 9.
Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
0.5 × VCC
0.5 × VCC
0.5 × VCC
0.5 × VCC
0.5 × VCC
0.5 × VCC
VOL + 0.1 V
VOL + 0.15 V
VOL + 0.3 V
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
8 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
9 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 9. Package outline SOT353-1 (TSSOP5)
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
10 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 10. Package outline SOT886 (XSON6)
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
11 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 11. Package outline SOT891 (XSON6)
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
12 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
74AUP1G38_3
Modifications:
74AUP1G38_2
74AUP1G38_1
Release date
20090622
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AUP1G38_2
• Table 5: Derating factor XSON8 and XQFN8U has been changed.
20070614
Product data sheet
-
74AUP1G38_1
-
20061020
Product data sheet
-
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
13 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP1G38_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
14 of 15
74AUP1G38
NXP Semiconductors
Low-power 2-input NAND gate (open drain)
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 June 2009
Document identifier: 74AUP1G38_3
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