74AUP2G86GT-G [NXP]
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NXP |
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74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
Rev. 04 — 29 June 2009
Product data sheet
1. General description
The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP2G86DC
74AUP2G86GT
74AUP2G86GD
74AUP2G86GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
XSON8U plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
XQFN8U plastic extremely thin quad flat package; no leads;
SOT902-1
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking codes
Type number
74AUP2G86DC
74AUP2G86GT
74AUP2G86GT
74AUP2G86GM
Marking code[1]
p86
p86
p86
p86
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
= 1
1A
1Y
1B
2A
2Y
= 1
2B
001aah760
001aah761
Fig 1. Logic symbol
Fig 2. IEC logic symbol
B
A
Y
mna040
Fig 3. Logic diagram (one gate)
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
2 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
6. Pinning information
6.1 Pinning
74AUP2G86
1A
1B
1
2
3
4
8
7
6
5
V
CC
1Y
2B
2A
74AUP2G86
2Y
1
2
3
4
8
7
6
5
1A
1B
V
CC
1Y
2B
2A
GND
2Y
GND
001aaf174
Transparent top view
001aaf173
Fig 4. Pin configuration SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT833-1 (XSON8)
74AUP2G86
terminal 1
index area
1Y
1
7
6
5
1A
1B
2Y
74AUP2G86
1A
1B
1
2
3
4
8
7
6
5
V
CC
2B
2A
2
3
1Y
2B
2A
2Y
GND
001aaf175
001aaj918
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT996-2 (XSON8U)
Fig 7. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT765-1, SOT833-1 and SOT996-2 SOT902-1
1A, 2A
1B, 2B
GND
1, 5
2, 6
4
7, 3
6, 2
4
data input
data input
ground (0 V)
data output
supply voltage
1Y, 2Y
VCC
7, 3
8
1, 5
8
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
3 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
7. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nB
L
nY
L
L
H
L
H
H
L
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
VO
IO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
±20
50
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−50
−65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Operating conditions
Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
supply voltage
input voltage
V
VI
3.6
V
VO
output voltage
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
0
+125
200
°C
ns/V
∆t/∆V
input transition rise and fall rate
VCC = 0.8 V to 3.6 V
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
4 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
µA
µA
V
[1]
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
0.6
1.3
-
-
pF
pF
CO
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
5 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
[1]
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
6 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
±0.75
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
[1]
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
[1] One input at VCC − 0.6 V, other input at VCC or GND.
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
7 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Typ[1] Max Min
Max
(85 °C) (125 °C)
Unit
Min
Max
CL = 5 pF
[2]
[2]
[2]
[2]
tpd
propagation delay nA or nB to nY; see Figure 8
VCC = 0.8 V
-
21.2
5.9
4.1
3.3
2.6
2.3
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
2.3
1.8
1.5
1.2
1.0
13.1 2.1
14.3
8.8
6.9
5.3
4.7
15.8
9.7
7.6
5.9
5.2
VCC = 1.4 V to 1.6 V
7.7
5.9
4.4
4.0
1.6
1.4
1.1
0.9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tpd
propagation delay nA or nB to nY; see Figure 8
VCC = 0.8 V
-
24.7
6.8
4.8
3.9
3.1
2.9
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.6
2.2
1.8
1.5
1.3
14.8 2.4
16.2
10.0
8.0
6.2
5.6
17.9
11.0
8.8
6.9
6.2
8.7
6.7
5.2
4.8
1.9
1.7
1.4
1.3
CL = 15 pF
tpd
propagation delay nA or nB to nY; see Figure 8
VCC = 0.8 V
-
28.2
7.6
5.3
4.4
3.6
3.3
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
3.0
2.4
2.1
1.8
1.6
16.5 2.7
18.1
11.3
9.0
7.0
6.4
20.0
12.5
9.9
7.7
7.1
VCC = 1.4 V to 1.6 V
9.6
7.5
5.9
5.4
2.2
1.9
1.6
1.5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 30 pF
tpd
propagation delay nA or nB to nY; see Figure 8
VCC = 0.8 V
-
38.5
9.9
6.9
5.7
4.7
4.4
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.9
3.2
2.8
2.4
2.2
21.5 3.5
12.5 2.8
24.1
14.8
11.7
9.1
8.3
26.6
16.3
12.9
10.1
9.2
9.8
7.6
7.1
2.5
2.2
2.1
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
8 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Typ[1] Max Min
Max
(85 °C) (125 °C)
Unit
Min
Max
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation f = 1 MHz; VI = GND to VCC
[3]
capacitance
VCC = 0.8 V
-
-
-
-
-
-
2.7
2.9
3.0
3.1
3.6
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
nY output
V
M
V
OL
mna224
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The data input (nA or nB) to output (nY) propagation delays
Table 9.
Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
≤ 3.0 ns
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
9 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Load
VEXT
[1]
CL
RL
5 kΩ or 1 MΩ
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, set-up and hold times and pulse width RL = 1 MΩ.
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
10 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
13. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
11 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 11. Package outline SOT833-1 (XSON8)
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
12 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 12. Package outline SOT996-2 (XSON8U)
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
13 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
C
1
y
L
M
M
v
C A
C
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 13. Package outline SOT902-1 (XQFN8U)
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
14 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
15. Revision history
Table 12. Revision history
Document ID
74AUP2G86_4
Modifications:
74AUP2G86_3
74AUP2G86_2
74AUP2G86_1
Release date
20090629
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AUP2G86_3
• Table 5: Derating factor XSON8, XSON8U and XQFN8U packages has been changed.
20090504
20080319
20061009
Product data sheet
Product data sheet
Product data sheet
-
-
-
74AUP2G86_2
74AUP2G86_1
-
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
15 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP2G86_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 29 June 2009
16 of 17
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 June 2009
Document identifier: 74AUP2G86_4
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