74AUP2GU04 [NXP]
Low-power dual unbuffered inverter; 低功耗双缓冲逆变器
| 型号： | 74AUP2GU04 |
| 厂家： | 
NXP |
| 描述： | Low-power dual unbuffered inverter |
| 文件： | 总16页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP2GU04
Low-power dual unbuffered inverter
Rev. 02 — 3 July 2009
Product data sheet
1. General description
The 74AUP2GU04 provides two unbuffered inverting gates.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP2GU04GW −40 °C to +125 °C
SC-88
plastic surface-mounted package; 6 leads
SOT363
74AUP2GU04GM
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
74AUP2GU04GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP2GU04GW
74AUP2GU04GM
74AUP2GU04GF
aD
aD
aD
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
2A
1Y
6
4
1
3
1
1
V
CC
1
3
6
4
540 Ω
50 Ω
A
Y
2Y
mnb106
mnb107
001aad073
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74AUP2GU04
74AUP2GU04
1A
GND
2A
1
2
3
6
5
4
1Y
74AUP2GU04
1
2
3
6
5
4
1A
GND
2A
1Y
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
V
CC
V
CC
2Y
2Y
2Y
001aad700
001aad701
Transparent top view
Transparent top view
001aad699
Fig 4. Pin configuration SOT363
(SC-88)
Fig 5. Pin configuration SOT886
(XSON6)
Fig 6. Pin configuration SOT891
(XSON6)
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
2 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
6.2 Pin description
Table 3.
Symbol
1A
Pin description
Pin
1
Description
data input
GND
2A
2
ground (0 V)
data input
3
2Y
4
data output
supply voltage
data output
VCC
5
1Y
6
7. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nY
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
VI < 0 V
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
Unit
V
supply voltage
+4.6
input clamping current
input voltage
-
mA
V
[1]
[2]
VI
+4.6
IOK
output clamping current
output voltage
VO < 0 V
-
mA
V
VO
VCC + 0.5
±20
IO
output current
VO = 0 V to VCC
mA
mA
mA
°C
ICC
supply current
-
50
IGND
Tstg
Ptot
ground current
−50
−65
-
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
3 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
V
supply voltage
VI
input voltage
3.6
V
VO
output voltage
0
VCC
+125
200
V
Tamb
∆t/∆V
ambient temperature
−40
0
°C
ns/V
input transition rise and fall rate VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 0.8 V to 3.6 V
VCC = 0.8 V to 3.6 V
0.75 × VCC
-
-
-
V
V
-
0.25 × VCC
VOH
HIGH-level output voltage VI = GND or VCC
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = GND or VCC
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI = GND or VCC; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
0.5
V
V
V
V
V
V
V
II
input leakage current
supply current
µA
µA
ICC
VCC = 0.8 V to 3.6 V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
1.5
1.8
-
-
pF
pF
CO
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
4 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 0.8 V to 3.6 V
VCC = 0.8 V to 3.6 V
0.75 × VCC
-
-
-
V
V
-
0.25 × VCC
VOH
HIGH-level output voltage VI = GND or VCC
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = GND or VCC
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI = GND or VCC; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
0.9
V
V
V
V
V
V
V
II
input leakage current
supply current
µA
µA
ICC
VCC = 0.8 V to 3.6 V
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 0.8 V to 3.6 V
VCC = 0.8 V to 3.6 V
0.75 × VCC
-
-
-
V
V
-
0.25 × VCC
VOH
HIGH-level output voltage VI = GND or VCC
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
5 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = GND or VCC
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI = GND or VCC; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
supply current
±0.75
1.4
µA
µA
ICC
VCC = 0.8 V to 3.6 V
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
Max
(85 °C) (125 °C)
CL = 5 pF
[2]
tpd
propagation delay nA to nY; see Figure 7
VCC = 0.8 V
-
6.2
2.3
1.7
1.4
1.1
1.0
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
0.9
0.7
0.5
0.4
0.3
4.4
3.1
2.6
2.0
1.8
0.9
0.6
0.5
0.4
0.3
4.8
3.4
2.9
2.3
2.1
5.3
3.8
3.2
2.6
2.4
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
[2]
tpd
propagation delay nA to nY; see Figure 7
VCC = 0.8 V
-
9.6
3.1
2.3
1.9
1.5
1.3
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.2
1.0
0.8
0.6
0.5
6.1
4.0
3.3
2.7
2.4
1.2
0.9
0.7
0.6
0.5
6.8
4.6
3.8
3.1
2.7
7.5
5.1
4.2
3.5
3.0
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
6 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max
Min
Max
Max
(85 °C) (125 °C)
CL = 15 pF
[2]
tpd
propagation delay nA to nY; see Figure 7
VCC = 0.8 V
-
13.0
3.8
2.8
2.3
1.9
1.6
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
1.6
1.3
1.0
0.8
0.7
7.9
4.9
4.0
3.2
2.9
1.4
1.1
0.9
0.8
0.7
8.8
5.7
4.7
3.7
3.3
9.7
6.3
5.2
4.1
3.7
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 30 pF
tpd propagation delay nA to nY; see Figure 7
[2]
VCC = 0.8 V
-
23.2
6.0
4.2
3.6
2.9
2.5
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.4
2.0
1.7
1.4
1.2
13.1
7.6
6.1
4.8
4.3
2.2
1.8
1.5
1.3
1.1
14.8
9.0
7.2
5.7
5.1
16.3
9.9
8.0
6.3
5.7
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation fi = 1 MHz; VI = GND to VCC
[3][4]
capacitance
VCC = 0.8 V
-
-
-
-
-
-
1.1
1.1
1.3
1.5
3.0
4.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] All specified values are the average typical values over all stated loads.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
7 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
12. Waveforms
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
V
M
nY output
M
V
OL
mna344
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. The data input (nA) to output (nY) propagation delays
Table 9.
Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, set-up and hold times and pulse width
RL = 1 MΩ.
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
8 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
13. Additional characteristics
R
bias
= 560 kΩ
V
CC
0.47 µF
100 µF
input
output
V
I
A
I
O
(f = 1 kHz)
GND
mna050
∆IO
g fs
=
---------
∆VI
VO is constant.
Fig 9. Test set-up for measuring forward transconductance
001aad074
30
g
fs
(mA/V)
20
10
0
0
1
2
3
4
V
(V)
CC
Tamb = 25 °C.
Fig 10. Typical forward transconductance as a function of supply voltage
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
9 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
14. Application information
Some applications for the 74AUP2GU04 are:
• Linear amplifier (see Figure 11)
• Crystal oscillator (see Figure 12)
Remark: All values given are typical values unless otherwise specified.
R2
V
CC
1 µF
R1
U04
Z
L
mna052
ZL > 10 kΩ.
R1 ≥ 3 kΩ.
R2 ≤ 1 MΩ.
Open loop amplification: AOL = 20.
AOL
-----------------------------------------
Voltage amplification: AV = –
.
R1
1 +
(1 + A
)
------
OL
R2
Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC.
Unity gain bandwidth product is 5 MHz.
Fig 11. Linear amplifier application
R1
R2
U04
C1
C2
out
mna053
C1 = 47 pF.
C2 = 22 pF.
R1 = 1 MΩ to 10 MΩ.
R2 optimum value depends on the frequency and required stability against changes in VCC or
average minimum ICC (ICC = 2 mA at VCC = 3.3 V and f = 10 MHz).
Fig 12. Crystal oscillator application
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
10 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
15. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 13. Package outline SOT363 (SC-88)
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
11 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 14. Package outline SOT886 (XSON6)
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
12 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 15. Package outline SOT891 (XSON6)
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
13 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
16. Abbreviations
Table 11. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
17. Revision history
Table 12. Revision history
Document ID
74AUP2GU04_2
Modifications:
Release date
20090703
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AUP2GU04_1
• Section 8 “Limiting values”:
Changed: Derating factor XSON6 packages.
• Section 10 “Static characteristics”:
Changed: conditions for HIGH-level output voltage and LOW-level output voltage.
• Section 11 “Dynamic characteristics”:
Changed: typical power dissipation capacitance.
74AUP2GU04_1
20061215
Product data sheet
-
-
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
14 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP2GU04_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
15 of 16
74AUP2GU04
NXP Semiconductors
Low-power dual unbuffered inverter
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Additional characteristics. . . . . . . . . . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 July 2009
Document identifier: 74AUP2GU04_2
相关型号：
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