74AVC16334ADGG,512 [NXP]

74AVC16334A - 16-bit registered driver with inverted register enable and Dynamic Controlled Outputs™ (3‑state) TSSOP 48-Pin;
74AVC16334ADGG,512
型号: 74AVC16334ADGG,512
厂家: NXP    NXP
描述:

74AVC16334A - 16-bit registered driver with inverted register enable and Dynamic Controlled Outputs™ (3‑state) TSSOP 48-Pin

驱动 光电二极管 逻辑集成电路
文件: 总10页 (文件大小:97K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
74AVC16334A  
16-bit registered driver with  
inverted register enable and  
Dynamic Controlled Outputs (3-State)  
Product specification  
2000 Aug 03  
Supersedes data of 2000 May 02  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
FEATURES  
PIN CONFIGURATION  
Wide supply voltage range of 1.2 V to 3.6 V  
OE  
1
2
CP  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
Complies with JEDEC standard no. 8-1A/5/7.  
CMOS low power consumption  
Y
0
A
0
Y
1
3
A
1
Input/output tolerant up to 3.6 V  
GND  
4
GND  
Y
2
5
A
2
DCO (Dynamic Controlled Output) circuit dynamically changes  
output impedance, resulting in noise reduction without speed  
degradation  
Y
3
6
A
3
V
7
V
CC  
CC  
Y
4
8
A
4
Low inductance multiple V and GND pins for minimum noise  
CC  
and ground bounce  
Y
5
9
A
5
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
Power off disables 74AVC16334A outputs, permitting Live  
Y
6
A
6
Insertion  
Y
7
A
7
Integrated input diodes to minimize input overshoot and  
Y
8
A
8
undershoot  
Y
9
A
9
Full PC133 solution provided when used with PCK2509S or  
GND  
GND  
PCK2510S and CBT16292  
Y
A
10  
10  
Y
A
11  
11  
DESCRIPTION  
V
V
CC  
CC  
The 74AVC16334A is a 16-bit universal bus driver. Data flow is  
controlled by output enable (OE), latch enable (LE) and clock inputs  
(CP).  
Y
A
12  
12  
Y
A
29  
28  
13  
13  
GND  
GND  
This product is designed to have an extremely fast propagation  
delay and a minimum amount of power consumption.  
27  
26  
25  
Y
14  
Y
15  
A
A
14  
15  
To ensure the high-impedance state during power up or power  
NC  
LE  
down, OE should be tied to V through a pullup resistor (Live  
CC  
Insertion).  
SH00167  
A Dynamic Controlled Output (DCO) circuitry is implemented to  
support termination line drive during transient. See the graphs on  
page 8 for typical curves.  
QUICK REFERENCE DATA  
GND = 0 V; T  
= 25°C; t = t 2.0 ns; C = 30 pF.  
amb  
r
f
L
SYMBOL  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
V
V
V
= 1.8 V  
= 2.5 V  
= 3.3 V  
2.5  
1.7  
1.5  
CC  
CC  
CC  
Propagation delay  
An to Yn  
t
t
/t  
ns  
PHL PLH  
Propagation delay  
LE to Yn;  
CP to Yn  
V
CC  
V
CC  
V
CC  
= 1.8 V  
= 2.5 V  
= 3.3 V  
2.7  
2.0  
1.6  
/t  
ns  
PHL PLH  
C
C
Input capacitance  
3.8  
25  
6
pF  
pF  
I
Outputs enabled  
Output disabled  
1
Power dissipation capacitance per buffer  
V = GND to V  
I CC  
PD  
NOTE:  
1. C is used to determine the dynamic power dissipation (P in µW):  
PD  
D
2
2
P
= C × V  
× f + S (C × V  
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;  
CC o i L  
D
PD  
CC  
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V  
o
× f ) = sum of outputs.  
o
CC  
L
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE  
RANGE  
OUTSIDE NORTH  
AMERICA  
DRAWING  
NUMBER  
NORTH AMERICA  
48-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II  
–40°C to +85°C  
AVC16334A DGG  
SOT362-1  
2
2000 Aug 03  
853-2212 24282  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
PIN DESCRIPTION  
LOGIC SYMBOL (IEEE/IEC)  
PIN NUMBER  
SYMBOL NAME AND FUNCTION  
1
48  
25  
OE  
CP  
LE  
EN1  
2C3  
24  
NC  
No connection  
Data outputs  
2, 3, 5, 6, 8, 9, 11, 12, 13,  
14, 16, 17, 19, 20, 22, 23  
Y to Y  
C3  
G2  
0
15  
4, 10, 15, 21, 28, 34, 39,  
45  
GND  
Ground (0 V)  
2
3
47  
Y
Y
Y
Y
Y
Y
Y
Y
Y
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
46  
44  
43  
41  
40  
38  
37  
7, 18, 31, 42  
1
V
CC  
Positive supply voltage  
5
Output enable input  
(active LOW)  
OE  
6
11  
1
3D  
8
Latch enable input  
(active LOW)  
25  
48  
LE  
9
11  
12  
13  
CLK  
Clock input  
47, 46, 44, 43, 41, 40,  
38, 37, 36, 35, 33, 32,  
30, 29, 27, 26  
36  
35  
33  
32  
30  
29  
27  
26  
A to A  
0
Data inputs  
15  
14  
16  
17  
19  
20  
22  
23  
Y
A
A
A
A
A
A
A
9
9
Y
10  
10  
11  
12  
13  
14  
15  
Y
LOGIC SYMBOL  
11  
12  
13  
14  
15  
Y
Y
Y
Y
OE  
SH00168  
CP  
LE  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
OE  
H
L
LE  
X
CLK  
A
X
L
X
X
X
Z
L
L
L
L
H
L
H
L
L
H
H
H
A
D
1
L
H
X
H
Y
1
LE  
1
L
L or H  
Y
0
CP  
H
L
X
Z
=
=
=
=
=
HIGH voltage level  
LOW voltage level  
Don’t care  
High impedance “off” state  
LOW-to-HIGH level transition  
TO THE 17 OTHER CHANNELS  
NOTE:  
SH00202  
1. Output level before the indicated steady-state input conditions  
were established.  
3
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
168-pin SDR SDRAM DIMM  
BACK SIDE  
FRONT SIDE  
74AVC16334A 74AVC16334A 74AVC16334A PCK2509S or PCK2510S  
The PLL clock distribution device and AVC registered drivers reduce  
signal loads on the memory controller and prevent timing delays and  
waveform distortions that would cause unreliable operation  
SW00525  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
MAX  
UNIT  
1.65  
2.3  
3.0  
1.95  
2.7  
3.6  
DC supply voltage  
(according to JEDEC Low Voltage Standards)  
V
CC  
V
V
DC supply voltage (for low voltage applications)  
DC Input voltage range  
1.2  
0
3.6  
3.6  
3.6  
V
V
CC  
V
I
DC output voltage range; output 3-State  
DC output voltage range; output HIGH or LOW state  
Operating free-air temperature range  
0
V
V
O
0
V
CC  
T
amb  
–40  
+85  
°C  
V
V
V
= 1.65 to 2.3 V  
= 2.3 to 3.0 V  
= 3.0 to 3.6 V  
0
0
0
30  
20  
10  
CC  
t , t  
r
Input rise and fall times  
ns/V  
f
CC  
CC  
ABSOLUTE MAXIMUM RATINGS  
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).  
SYMBOL  
PARAMETER  
DC supply voltage  
CONDITIONS  
RATING  
UNIT  
V
V
CC  
I
IK  
–0.5 to +4.6  
–50  
DC input diode current  
V t0  
mA  
V
I
1
V
I
DC input voltage  
For data inputs  
–0.5 to 4.6  
"50  
I
DC output diode current  
V
O
uV or V t 0  
mA  
V
OK  
CC  
O
V
O
DC output voltage; output 3-State  
DC output voltage; output HIGH or LOW state  
DC output source or sink current  
Note 1  
Note 1  
–0.5 to 4.6  
V
O
–0.5 to V +0.5  
V
CC  
I
O
V
O
= 0 to V  
CC  
"50  
"100  
mA  
mA  
°C  
I
, I  
DC V or GND current  
GND CC  
CC  
T
stg  
Storage temperature range  
–65 to +150  
Power dissipation per package  
–plastic thin-medium-shrink (TSSOP)  
For temperature range: –40 to +125 °C  
above +55°C derate linearly with 8 mW/K  
P
TOT  
mW  
600  
NOTE:  
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
4
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
DC ELECTRICAL CHARACTERISTICS  
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).  
LIMITS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
Temp = -40°C to +85°C  
UNIT  
1
MIN  
TYP  
MAX  
V
V
V
V
V
V
V
V
V
= 1.2 V  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
= 1.65 to 1.95 V  
= 2.3 to 2.7 V  
= 3.0 to 3.6 V  
= 1.2 V  
0.65 V  
0.9  
1.2  
1.5  
CC  
V
HIGH level Input voltage  
V
IH  
1.7  
2.0  
GND  
= 1.65 to 1.95 V  
= 2.3 to 2.7 V  
= 3.0 to 3.6 V  
0.9  
1.2  
1.5  
0.35 V  
0.7  
CC  
V
LOW level Input voltage  
HIGH level output voltage  
V
V
IL  
0.8  
= 1.65 to 3.6 V; V = V or V ;  
= –100 µA  
I
IH  
IL  
V
*0.20  
V
CC  
CC  
I
O
V
CC  
V
CC  
V
CC  
V
CC  
= 1.65 V; V = V or V ; I = –4 mA  
V
V
V
0.45  
V
V
V
0.10  
*
*
*
*
I
IH  
IL  
O
CC  
CC  
CC  
CC  
V
OH  
= 2.3 V; V = V or V ; I = –8 mA  
0.55  
0.70  
0.28  
0.32  
*
*
I
IH  
IL  
O
CC  
CC  
= 3.0 V; V = V or V ; I = –12 mA  
I
IH  
IL  
O
= 1.65 to 3.6 V; V = V or V ;  
= 100 µA  
I
IH  
IL  
GND  
0.20  
I
O
V
V
V
V
= 1.65 V; V = V or V ; I = 4 mA  
0.10  
0.26  
0.36  
0.45  
0.55  
0.70  
CC  
CC  
CC  
CC  
I
IH  
IL  
O
V
LOW level output voltage  
V
OL  
= 2.3 V; V = V or V ; I = 8 mA  
I
IH  
IL  
O
= 3.0 V; V = V or V ; I = 12 mA  
I
IH  
IL  
O
= 3.6 V;  
CC  
I
Input leakage current  
0.1  
0.1  
0.1  
2.5  
"10  
5
µA  
µA  
I
V = V or GND  
I
I
3-State output OFF-state current  
V
CC  
= 0 V; V or V = 3.6 V  
I O  
OFF  
V
V
= 1.65 to 2.7 V; V = V or V ;  
I IH IL  
CC  
O
= V or GND  
CC  
I
3-State output OFF-state current  
Quiescent supply current  
µA  
µA  
OZ  
V
V
= 3.0 to 3.6 V; V = V or V ;  
I IH IL  
CC  
O
0.1  
10  
= V or GND  
CC  
V
= 1.65 to 2.7 V; V = V or GND; I = 0  
0.1  
0.2  
20  
40  
CC  
CC  
I
CC  
O
I
CC  
V
= 3.0 to 3.6 V; V = V or GND; I = 0  
I
CC  
O
NOTE:  
1. All typical values are at T  
= 25°C.  
amb  
5
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
AC CHARACTERISTICS  
GND = 0 V; t = t 2.0 ns; C = 30 pF  
r
f
L
LIMITS  
V = 1.8 ± 0.15 V  
CC  
V
=
V
1.2 V  
=
CC  
CC  
V
CC  
= 3.3 ± 0.3 V  
V
CC  
= 2.5 ± 0.2 V  
SYMBOL  
PARAMETER  
WAVEFORM  
UNIT  
1.5 ± 0.1 V  
1
1
1
MIN  
TYP  
MAX MIN  
TYP  
MAX  
MIN  
TYP  
MAX MIN MAX  
TYP  
Propagation  
delay  
An to Yn  
1
2
3
6
6
0.7  
1.5  
2.6  
3.2  
2.8  
3.4  
3.7  
0.8  
1.0  
0.8  
1.0  
0.9  
1.7  
3.0  
3.3  
3.0  
3.8  
3.9  
1.0  
1.2  
1.0  
1.5  
1.5  
2.5  
4.4  
4.8  
3.9  
5.3  
6.5  
1.7  
1.7  
1.4  
2.0  
1.7  
5.3  
6.0  
4.6  
6.7  
7.1  
5.0  
5.3  
4.1  
6.0  
6.1  
Propagation  
delay  
LE to Yn  
t
/t  
ns  
0.7  
0.7  
0.7  
1.0  
1.6  
1.6  
1.7  
2.1  
2.0  
1.7  
2.2  
2.0  
2.7  
2.3  
3.1  
3.7  
PHL PLH  
Propagation  
delay  
CP to Yn  
3-State output  
enable time  
OE to Yn  
t
t
/t  
ns  
ns  
PZH PZL  
3-State output  
disable time  
OE to Yn  
/t  
PHZ PLZ  
CP pulse width  
HIGH or LOW  
3
2
5
4
5
4
3
1.0  
1.0  
1.2  
1.2  
0.1  
0.5  
0.6  
0.4  
400  
2.0  
2.0  
0.1  
0.8  
0.6  
0.3  
250  
t
ns  
ns  
W
LE pulse width  
LOW  
Set-up time  
An to CP  
0.2 –0.1  
–0.1  
0.1  
0.2  
0.1  
–0.1  
0.3  
0.2  
0.1  
0.1  
1.2  
0.6  
0.3  
0.0  
1.0  
0.1  
–0.4  
t
SU  
Set-up time  
An to LE  
0.4  
0.6  
0.4  
500  
0.1  
0.2  
0.1  
Hold time  
An to CP  
t
ns  
h
Hold time  
An to LE  
Maximum clock  
pulse frequency  
f
MHz  
max  
NOTE:  
1. All typical values are measured at T  
= 25°C and at V = 1.8 V, 2.5 V, 3.3 V.  
amb  
CC  
6
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
AC WAVEFORMS FOR V = 3.0 V TO 3.6 V RANGE  
CC  
V
I
V
V
V
V
= 0.5 V  
M
X
Y
CC  
An  
INPUT  
V
= V + 0.300 V  
= V – 0.300 V  
M
OL  
OH  
GND  
and V are the typical output voltage drop that occur with the  
OL  
OH  
th  
th  
output load.  
V = V  
t
t
SU  
SU  
I
CC  
V
I
LE  
INPUT  
V
M
AC WAVEFORMS FOR V = 2.3 V TO 2.7 V AND  
CC  
GND  
V
< 2.3 V RANGE  
CC  
NOTE: The shaded areas indicate when the input is permitted to change  
V
V
V
V
= 0.5 V  
M
X
Y
OL  
CC  
for predictable output performance.  
V = 0.5V at V = 2.3 to 2.7 V  
= V + 0.15 V  
OL  
M CC CC  
= V – 0.15 V  
SH00166  
OH  
and V are the typical output voltage drop that occur with the  
OH  
Waveform 4. Data set-up and hold times for the An input to the  
LE input  
output load.  
V = V  
I
CC  
V
I
V
I
A
n
V
CP INPUT  
M
V
M
INPUT  
GND  
GND  
t
su  
t
su  
t
t
PLH  
PHL  
t
h
t
h
V
Y
OH  
n
V
I
V
M
An INPUT  
OUTPUT  
GND  
V
OL  
NOTE: V = 0.5V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00132  
V
OH  
Waveform 1. Input (An) to output (Yn) propagation delay  
V
M
Yn OUTPUT  
V
OL  
NOTE: The shaded areas indicate when the input is permitted to change  
V
I
for predictable output performance.  
V
= 0.5V at V = 2.3 to 2.7 V  
M
CC CC  
SH00136  
V
V
M
M
LE INPUT  
GND  
Waveform 5. Data set-up and hold times for the An input to the  
clock CP input  
t
W
t
t
PLH  
PHL  
V
OH  
V
M
Yn OUTPUT  
V
I
V
OL  
V
nOE INPUT  
GND  
M
NOTE: V = 0.5 V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00165  
Waveform 2. Latch enable input (LE) pulse width, the latch  
enable input to output (Yn) propagation delays.  
t
t
PZL  
PLZ  
V
CC  
OUTPUT  
LOW-to-OFF  
OFF-to-LOW  
V
1/f  
MAX  
M
V
I
V
X
V
OL  
V
V
M
M
CP INPUT  
GND  
t
W
t
t
PZH  
PHZ  
t
t
PLH  
PHL  
V
OH  
OUTPUT  
HIGH-to-OFF  
OFF-to-HIGH  
V
Y
V
OH  
V
M
V
Yn OUTPUT  
M
GND  
V
OL  
outputs  
enabled  
outputs  
disabled  
outputs  
enabled  
NOTE: V = 0.5V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00135  
Waveform 3. The clock (CP) to Yn propagation delays, the  
clock pulse width and the maximum clock frequency.  
NOTE: V = 0.5V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00137  
Waveform 6. 3-State enable and disable times  
7
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
TEST CIRCUIT  
GRAPHS  
S
1
2 * V  
V
CC  
CC  
3.5  
3
Open  
GND  
R
R
L
L
2.5  
2
V
V
O
I
V
= 3.3 V  
CC  
PULSE  
GENERATOR  
D.U.T.  
1.5  
1
R
T
C
V
CC  
L
= 2.5 V  
V
CC  
0.5  
= 1.8 V  
Test Circuit for switching times  
0
0
50  
100  
I
OUTPUT CURRENT (mA)  
OL  
150  
200  
250  
DEFINITIONS  
R
L
C
L
R
T
= Load resistor  
= Load capacitance includes jig and probe capacitance  
= Termination resistance should be equal to Z of pulse generators.  
OUT  
SH00204  
SWITCH POSITION  
TEST  
S
V
V
R
L
1
CC  
I
Figure 1. Output voltage (V ) vs. output current (I  
)
OL  
OL  
t
t
Open  
< 2.3 V  
2.3–2.7 V  
3.0 V  
V
V
1000  
500 Ω  
500 Ω  
PLH/ PHL  
CC  
CC  
t
t
t
PLZ/ PZL  
2 < V  
CC  
t
GND  
V
CC  
PHZ/ PZH  
3.5  
SV01018  
3.0  
2.5  
2.0  
Waveform 7. Load circuitry for switching times  
1.5  
1.0  
V
= 3.3 V  
CC  
0.5  
V
CC  
V
CC  
= 2.5 V  
–150  
= 1.8 V  
0.0  
–50  
–250  
–200  
–100  
0
I
OUTPUT CURRENT (mA)  
OH  
SH00205  
Figure 2. Output voltage (V ) vs. output current (I  
)
OH  
OH  
A Dynamic Controlled Output (DCO) circuit is designed in. During  
the transition, it initially lowers the output impedance to effectively  
drive the load and, subsequently, raises the impedance to reduce  
noise. Figures 1 and 2 show V vs. I and V vs. I curves to  
OL  
OL  
OH  
OH  
illustrate the output impedance and drive capability of the circuit. At  
the beginning of the signal transition, the DCO circuit provides a  
maximum dynamic drive that is equivalent to a high drive standard  
output device.  
8
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm  
SOT362-1  
9
2000 Aug 03  
Philips Semiconductors  
Product specification  
16-bit registered driver with inverted register enable and  
Dynamic Controlled Outputs (3-State)  
74AVC16334A  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make changes at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 2000  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Date of release: 08-00  
Document order number:  
9397-750 07394  
Philips  
Semiconductors  

相关型号:

74AVC16373

16-bit D-type transparent latch; 3.6 V tolerant; 3-state
NXP

74AVC16373DG

IC AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362, TSSOP-48, Bus Driver/Transceiver
NXP

74AVC16373DG-T

IC AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362, TSSOP-48, Bus Driver/Transceiver
NXP

74AVC16373DGG

16-bit D-type transparent latch; 3.6 V tolerant; 3-state
NXP

74AVC16373DGG,112

74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin
NXP

74AVC16373DGG,118

74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin
NXP

74AVC16373DGG,512

74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin
NXP

74AVC16373DGG,518

74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin
NXP

74AVC16373DGG-T

暂无描述
NXP

74AVC16373DGGRG4

16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85
TI

74AVC16373DGVRE4

AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TVSOP-48
TI

74AVC16373DGVRG4

16-Bit Transparent D-Type Latch With 3-State Outputs 48-TVSOP -40 to 85
TI