74AVC16373DGVRG4 [TI]
16-Bit Transparent D-Type Latch With 3-State Outputs 48-TVSOP -40 to 85;
| 型号： | 74AVC16373DGVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TVSOP -40 to 85 驱动 光电二极管 逻辑集成电路 电视 |
| 文件： | 总19页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
1
FEATURES
2
•
•
•
Member of the Texas Instruments Widebus™
Family
•
•
•
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Ioff Supports Partial-Power-Down Mode
Operation
DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
ESD Protection Exceeds JESD 22
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA at
2.5-V VCC
Package Options Include Plastic Thin Shrink
Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
T
A
= 25°C
T
A
= 25°C
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
CC
= 3.3 V
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
0
17
34
51
68
85 102 119 136 153 170
-160 -144 -128 -112 -96 -80 -64 -48 -32 -16
- Output Current - mA
0
I
- Output Current - mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at
the levels set up at the D inputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Widebus, EPIC, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2008, Texas Instruments Incorporated
SN74AVC16373
SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
DESCRIPTION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can
be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16373 is characterized for operation from –40°C to 85°C.
GQL/ZQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1LE
1D1
1
2
3
4
5
6
7
8
9
48
47
46 1D2
GND
1D3
1D4
VCC
45
44
43
42
G
H
J
41 1D5
40 1D6
39 GND
GND 10
1Q7
1Q8
2Q1
1D7
1D8
2D1
K
11
12
13
38
37
36
TERMINAL ASSIGNMENTS
(56-Ball GQL/ZQL Package)(1)
2Q2 14
GND 15
2Q3 16
2Q4 17
35 2D2
34 GND
33 2D3
32 2D4
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCCB
GND
GND
VCCA
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
VCC
VCC
18
31
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2LE
G
H
J
GND
VCCB
GND
NC
GND
VCCA
GND
NC
K
(1) NC - No internal connection
2
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Product Folder Link(s): SN74AVC16373
SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008
FUNCTION TABLE
(EACH 8-BIT LATCH)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q0
Z
H
X
LOGIC SYMBOL(1)
1
1OE
1LE
2OE
2LE
1EN
C3
48
24
25
2EN
C4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
3D
1
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
5
6
8
9
11
12
13
14
16
17
19
20
22
23
4D
2
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM (POSITIVE LOGIC)
1
24
2OE
2LE
1OE
1LE
25
48
C1
1D
C1
1D
2
13
2Q1
1Q1
47
36
2D1
1D1
To Seven Other Channels
To Seven Other Channels
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SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
4.6
4.6
4.6
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
DGG package
θJA
Package thermal impedance(4)
DGV package
58 °C/W
42
GQL/ZQL package
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
(4) The package thermal impedance is calculated in accordance with JESD 51.
4
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SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.4
1.2
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.2 V
VCC
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.2 V
0.65 × VCC
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
GND
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.35 × VCC
VIL
Low-level input voltage
0.35 × VCC
V
0.7
0.8
3.6
VCC
3.6
–2
–4
–8
–12
2
VI
Input voltage
0
0
0
V
V
Active state
VO
Output voltage
3-state
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 1.4 V to 3.6 V
IOHS
Static high-level output current(2)
Static low-level output current(2)
mA
mA
4
IOLS
8
12
5
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
TA
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH
vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA066,
and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
Copyright © 1998–2008, Texas Instruments Incorporated
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SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.4 V to 3.6 V
1.4 V
MIN TYP(1)
VCC – 0.2
MAX UNIT
IOHS = –100 µA
IOHS = –2 mA,
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
IOLS = 2 mA,
IOLS = 4 mA,
IOLS = 8 mA,
IOLS = 12 mA,
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
1.05
1.2
VOH
1.65 V
2.3 V
V
1.75
2.3
3 V
1.4 V to 3.6 V
1.4 V
0.2
0.4
VIL = 0.49 V
VIL = 0.57 V
VIL = 0.7 V
VIL = 0.8 V
VOL
1.65 V
2.3 V
0.45
0.55
0.7
V
3 V
II
VI = VCC or GND
VI or VO = 3.6 V
VO = VCC or GND
VI = VCC or GND,
3.6 V
±2.5
±10
±10
40
µA
µA
µA
µA
Ioff
IOZ
ICC
0
3.6 V
IO = 0
3.6 V
2.5 V
3
3
Control inputs
Data inputs
Outputs
VI = VCC or GND
VI = VCC or GND
VO = VCC or GND
3.3 V
Ci
pF
pF
2.5 V
2.5
2.5
6.5
6.5
3.3 V
2.5 V
Co
3.3 V
(1) Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.2 V
UNIT
MIN
MAX
MIN
MAX
MIN
2.2
1.1
1.1
MAX
MIN
2
MAX
MIN
1.8
0.8
1
MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
1.7
2
1.2
1.1
0.9
1.1
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
5.8
7.2
7.4
8.4
MIN
1.2
1.4
1.6
2.5
MAX
MIN
1
MAX
MIN
0.8
0.8
1.4
1.3
MAX
MIN
0.7
0.7
0.7
1.2
MAX
D
6.8
8.3
8.8
9.4
5.7
6.6
6.7
7.8
3.3
4
2.8
3.2
3.4
3.9
tpd
Q
ns
LE
OE
OE
1.1
1.6
2.3
ten
Q
Q
4.3
4.2
ns
ns
tdis
6
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Product Folder Link(s): SN74AVC16373
SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
40
TYP
43
TYP
47
Outputs enabled
Outputs disabled
Power dissipation
capacitance
Cpd
CL = 0,
f = 10 MHz
pF
20
22
24
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SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × V
CC
S1
Open
GND
2 kΩ
From Output
Under Test
TEST
S1
t
pd
Open
C = 15 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
2 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.1 V
CC
(see Note B)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.1 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
8
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www.ti.com ..................................................................................................................................... SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × V
CC
S1
Open
GND
1 kΩ
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
1 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
Copyright © 1998–2008, Texas Instruments Incorporated
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 4. Load Circuit and Voltage Waveforms
10
Submit Documentation Feedback
Copyright © 1998–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC16373
SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H–DECEMBER 1998–REVISED SEPTEMBER 2008
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × V
CC
TEST
S1
S1
500 Ω
Open
GND
From Output
Under Test
t
pd
Open
t
t
/t
2 × V
CC
GND
PLZ PZL
/t
C = 30 pF
(see Note A)
PHZ PZH
L
500 Ω
t
w
LOAD CIRCUIT
V
CC
V /2
CC
V /2
CC
Input
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Data
Input
Output
V
CC
V /2
CC
V /2
CC
Control
(low-level
enabling)
0 V
V /2
CC
V /2
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V
OL
+ 0.3 V
S1 at 2 × V
V /2
CC
V /2
CC
CC
(see Note B)
OL
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− 0.3 V
V /2
CC
V /2
CC
Output
V /2
CC
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 5. Load Circuit and Voltage Waveforms
Copyright © 1998–2008, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): SN74AVC16373
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2007
PACKAGING INFORMATION
Orderable Device
74AVC16373DGGRG4
74AVC16373DGVRE4
74AVC16373DGVRG4
SN74AVC16373DGGR
SN74AVC16373DGVR
SN74AVC16373GQLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
TSSOP
TVSOP
DGV
DGV
DGG
DGV
GQL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74AVC16373ZQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVC16373DGGR TSSOP
SN74AVC16373DGVR TVSOP
DGG
DGV
GQL
48
48
56
2000
2000
1000
330.0
330.0
330.0
24.4
16.4
16.4
8.6
7.1
4.8
15.8
10.2
7.3
1.8
1.6
12.0
12.0
8.0
24.0
16.0
16.0
Q1
Q1
Q1
SN74AVC16373GQLR BGA MI
1.45
CROSTA
R JUNI
OR
SN74AVC16373ZQLR BGA MI
ZQL
56
1000
330.0
16.4
4.8
7.3
1.45
8.0
16.0
Q1
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AVC16373DGGR
SN74AVC16373DGVR
TSSOP
TVSOP
DGG
DGV
GQL
48
48
56
2000
2000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
33.0
SN74AVC16373GQLR BGA MICROSTAR
JUNIOR
SN74AVC16373ZQLR BGA MICROSTAR
JUNIOR
ZQL
56
1000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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