74AVC16834ADG [NXP]
IC AVC SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56, Bus Driver/Transceiver;
| 型号： | 74AVC16834ADG |
| 厂家： | 
NXP |
| 描述： | IC AVC SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56, Bus Driver/Transceiver 总线驱动器 总线收发器 逻辑集成电路 光电二极管 |
| 文件： | 总10页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74AVC16834
18-bit registered driver
with inverted register enable (3-State)
Preliminary specification
Replaces datasheet 74AVC16834/74AVCH16834 dated 1998 Dec 11
1999 Jul 23
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
FEATURES
PIN CONFIGURATION
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7.
• CMOS low power consumption
NC
NC
1
2
56
GND
NC
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Y
3
A
0
0
• Input/output tolerant up to 3.6 V
GND
4
GND
• DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
Y
Y
5
A
A
V
A
A
A
1
2
1
6
2
V
7
CC
CC
3
• Low inductance multiple V and GND pins for minimum noise
Y
3
8
CC
and ground bounce
Y
Y
9
4
5
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
• Power off disables 74AVC16834 outputs, permitting Live Insertion
5
GND
GND
Y
Y
Y
Y
A
A
A
A
A
A
6
7
8
9
6
DESCRIPTION
7
The 74AVC16834 is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
8
9
Y
10
10
11
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
Y
11
GND
GND
To ensure the high-impedance state during power up or power
Y
Y
Y
A
A
A
V
A
A
12
13
14
12
13
14
CC
15
16
down, OE should be tied to V through a pullup resistor (Live
CC
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
V
CC
Y
15
16
Y
GND
GND
Y
A
17
17
OE
LE
CP
GND
SH00156
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t = t ≤ 2.0 ns; C = 30 pF.
amb
r
f
L
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
V
V
V
= 1.8 V
= 2.5 V
= 3.3 V
2.6
2.0
1.7
CC
CC
CC
Propagation delay
An to Yn
t
t
/t
ns
PHL PLH
Propagation delay
LE to Yn;
CP to Yn
V
CC
V
CC
V
CC
= 1.8 V
= 2.5 V
= 3.3 V
2.9
2.3
1.9
/t
ns
PHL PLH
C
C
Input capacitance
5.0
25
6
pF
pF
I
Outputs enabled
Output disabled
1
Power dissipation capacitance per buffer
V = GND to V
I CC
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW):
PD
D
2
2
P
= C × V
× f + S (C × V
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;
CC o i L
D
PD
CC
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V
o
× f ) = sum of outputs.
o
CC
L
CC
ORDERING INFORMATION
TEMPERATURE
RANGE
DRAWING
NUMBER
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
ORDER CODE
74AVC16834 DGG
–40°C to +85°C
SOT364-1
2
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
PIN DESCRIPTION
PIN NUMBER
1, 2, 55
LOGIC SYMBOL (IEEE/IEC)
SYMBOL NAME AND FUNCTION
27
30
28
NC
No connection
OE
CP
LE
EN1
2C3
3, 5, 6, 8, 9, 10, 12, 13,
14, 15, 16, 17, 19, 20,
21, 23, 24, 26
C3
G2
Y to Y
0
Data outputs
17
4, 11, 18, 25, 32, 39, 46,
53, 56
3
5
54
GND
Ground (0 V)
Y
Y
Y
Y
Y
Y
Y
Y
Y
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
52
51
49
48
47
45
44
43
42
7, 22, 35, 50
27
V
CC
Positive supply voltage
6
8
Output enable input
(active LOW)
1
1
3D
OE
9
10
12
13
14
Latch enable input
(active LOW)
28
30
LE
CP
Clock input
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
15
16
17
19
20
21
23
24
26
A to A
0
Data inputs
Y
A
A
A
A
A
A
A
A
A
17
9
9
41
40
38
37
36
34
33
31
Y
10
10
11
12
13
14
15
16
17
Y
11
12
13
14
15
16
17
LOGIC SYMBOL
Y
Y
Y
Y
Y
Y
OE
CP
SH00158
LE
FUNCTION TABLE
A
0
D
INPUTS
Y
0
OUTPUTS
LE
OE
H
L
LE
X
CP
X
X
X
↑
A
X
L
CP
Z
L
L
L
L
H
L
H
L
L
H
H
H
H
TO THE 17 OTHER CHANNELS
L
↑
H
X
X
H
1
L
H
L
Y
0
0
SH00157
2
L
Y
H
L
X
Z
↑
=
=
=
=
=
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
3
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
168-pin SDR SDRAM DIMM
BACK SIDE
FRONT SIDE
AVC16834
AVC16834
AVC16834
PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00407
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
1.65
2.3
3.0
1.95
2.7
3.6
DC supply voltage
(according to JEDEC Low Voltage Standards)
V
CC
V
DC supply voltage
(for low voltage applications)
1.2
3.6
V
DC Input voltage range
0
0
3.6
3.6
V
V
I
DC output voltage range; output 3-State
V
O
DC output voltage range;
output HIGH or LOW state
0
V
CC
T
amb
Operating free-air temperature range
–40
+85
°C
V
V
V
= 1.65 to 2.3 V
= 2.3 to 3.0 V
= 3.0 to 3.6 V
0
0
0
30
20
10
CC
CC
CC
t , t
r
Input rise and fall times
ns/V
f
4
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +4.6
–50
DC input diode current
DC input voltage
V t0
mA
V
I
1
V
I
For all inputs
–0.5 to 4.6
"50
I
DC output diode current
DC output voltage; output 3-State
V
O
uV or V t 0
mA
V
OK
CC
O
V
O
Note 1
–0.5 to 4.6
DC output voltage;
output HIGH or LOW state
V
O
Note 1
–0.5 to V +0.5
V
CC
I
DC output source or sink current
V
O
= 0 to V
CC
"50
"100
mA
mA
°C
O
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
–plastic thin-medium-shrink (TSSOP) above +55°C derate linearly with 8 mW/K
For temperature range: –40 to +125 °C
P
TOT
mW
600
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
–
MAX
V
V
V
V
V
V
V
V
V
= 1.2 V
V
CC
–
–
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 1.65 to 1.95 V
= 2.3 to 2.7 V
= 3.0 to 3.6 V
= 1.2 V
0.65V
0.9
1.2
1.5
–
CC
V
HIGH level Input voltage
V
V
IH
1.7
2.0
–
–
–
GND
= 1.65 to 1.95 V
= 2.3 to 2.7 V
= 3.0 to 3.6 V
–
0.9
1.2
1.5
0.35V
0.7
CC
V
LOW level Input voltage
HIGH level output voltage
IL
–
–
0.8
= 1.65 to 3.6V; V = V or V ;
= –100 µA
I
IH
IL
V
*0.20
V
CC
–
CC
I
O
V
V
V
V
= 1.65 V; V = V or V ; I = –4 mA
V
V
V
0.45
V
V
V
0.10
–
–
–
V
OH
V
*
*
*
*
CC
CC
CC
I
IH
IL
O
CC
CC
CC
CC
= 2.3 V; V = V or V ; I = –8 mA
0.55
0.70
0.28
0.32
*
*
I
IH
IL
O
CC
CC
= 3.0 V; V = V or V ; I = –12 mA
I
IH
IL
O
= 1.65 to 3.6 V; V = V or V ;
= 100 µA
CC
I
IH
IL
–
GND
0.20
I
O
V
V
V
V
= 1.65 V; V = V or V ; I = 4 mA
–
–
–
0.10
0.26
0.36
0.45
0.55
0.70
V
LOW level output voltage
Input leakage current
V
CC
CC
CC
I
IH
IL
O
OL
= 2.3 V; V = V or V ; I = 8 mA
I
IH
IL
O
= 3.0 V; V = V or V ; I = 12 mA
I
IH
IL
O
= 1.65 to 3.6 V;
CC
CC
I
–
0.1
2.5
µA
I
V = V or GND
I
I
3-State output OFF-state current
3-State output OFF-state current
V
V
= 0 V; V or V = 3.6 V
–
–
0.1
0.1
"10
µA
µA
OFF
CC
CC
CC
I
O
I
/I
= 1.65 to 3.6 V; V = V or GND
12.5
IHZ ILZ
I
CC
V
V
= 1.65 to 2.7 V; V = V or V ;
I IH IL
–
–
0.1
0.1
5
= V or GND
O
CC
I
3-State output OFF-state current
Quiescent supply current
µA
µA
OZ
V
V
= 3.0 to 3.6 V; V = V or V ;
I IH IL
CC
O
10
= V or GND
CC
V
= 1.65 to 2.7 V; V = V or GND; I = 0
–
–
0.1
0.2
20
40
CC
CC
I
CC
O
I
CC
V
= 3.0 to 3.6 V; V = V or GND; I = 0
I
CC
O
NOTES:
1. All typical values are at T
= 25°C.
amb
5
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
AC CHARACTERISTICS
GND = 0 V; t = t ≤ 2.0 ns; C = 30 pF
r
f
L
LIMITS
= 2.5 ± 0.2 V
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3 ± 0.3 V
V
CC
V
CC
= 1.8 ± 0.15 V
V
CC
= 1.2 V UNIT
1
1
1
MIN TYP
MAX MIN TYP
MAX MIN TYP
MAX
TYP
Propagation delay
An to Yn
1, 7
2, 7
3, 7
6, 7
6, 7
3, 7
0.7
0.7
0.7
1.0
1.0
1.0
1.7
1.9
1.7
2.3
2.3
–
2.5
2.9
2.5
4.0
3.5
–
0.8
0.8
0.8
1.0
1.0
1.2
2.0
2.3
2.0
2.5
2.2
–
3.0
3.5
3.0
4.5
4.0
–
1.0
1.0
1.0
1.5
1.5
2.0
2.6
2.9
2.6
3.0
3.5
–
4.5
5.2
Propagation delay
LE to Yn
t
/t
ns
5.3
4.5
6.5
6.5
–
5.8
5.2
5.5
5.5
–
PHL PLH
Propagation delay
CP to Yn
3-State output enable
time OE to Yn
t
t
/t
ns
ns
PZH PZL
3-State output disable
time OE to Yn
/t
PHZ PLZ
CP pulse width HIGH
or LOW
t
ns
ns
W
LE pulse width HIGH
Set-up time An to CP
Set-up time An to LE
Hold time An to CP
Hold time An to LE
2, 7
5, 7
4, 7
5, 7
4, 7
1.0
0.3
0.3
0.3
0.3
–
–
–
–
–
–
–
–
–
–
1.2
0.4
0.4
0.4
0.4
–
–
–
–
–
–
–
–
–
–
2.0
0.5
0.5
0.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
t
SU
t
ns
h
Maximum clock pulse
frequency
F
max
3, 7
500
–
–
400
–
–
250
–
–
MHz
NOTES:
1. All typical values are measured at T
= 25°C and at V = 1.8 V, 2.5 V, 3.3 V.
amb
CC
AC WAVEFORMS FOR V = 3.0 V TO 3.6 V RANGE
CC
V
V
V
V
= 0.5 V
M
X
Y
CC
= V + 0.300 V
V
I
OL
= V – 0.300 V
OH
V
V
M
M
LE INPUT
GND
and V are the typical output voltage drop that occur with the
OL
OH
output load.
V = V
t
W
I
CC
t
t
PLH
PHL
V
OH
AC WAVEFORMS FOR V = 2.3 V TO 2.7 V AND
CC
V
M
Yn OUTPUT
V
< 2.3 V RANGE
CC
V
V
= 0.5 V
OL
M
X
CC
V
V
V
= V + 0.15 V
NOTE: V = 0.5 V at V = 2.3 to 2.7 V
OL
M
CC
CC
= V – 0.15 V
SH00165
Y
OH
and V are the typical output voltage drop that occur with the
OL
OH
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
output load.
V = V
I
CC
V
I
A
n
V
M
INPUT
GND
t
t
PLH
PHL
V
Y
OH
n
V
M
OUTPUT
V
OL
NOTE: V = 0.5V at V = 2.3 to 2.7 V
M
CC
CC
SH00132
Waveform 1. Input (An) to output (Yn) propagation delay
1999 Jul 23
6
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
AC WAVEFORMS FOR V = 3.0 V TO 3.6 V RANGE
CC
(Continued)
V
V
V
V
= 0.5 V
M
X
Y
CC
V
I
= V + 0.300 V
OL
= V – 0.300 V
V
CP INPUT
M
OH
and V are the typical output voltage drop that occur with the
OL
OH
GND
output load.
V = V
t
su
I
CC
t
su
t
h
t
h
AC WAVEFORMS FOR V = 2.3 V TO 2.7 V AND
CC
V
I
V
< 2.3 V RANGE (Continued)
CC
An INPUT
V
V
V
V
= 0.5 V
M
X
Y
OL
CC
GND
= V + 0.15 V
OL
= V – 0.15 V
OH
V
OH
and V are the typical output voltage drop that occur with the
OH
V
output load.
V = V
M
Yn OUTPUT
I
CC
V
OL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
= 0.5V at V = 2.3 to 2.7 V
1/f
MAX
M
CC CC
SH00136
V
I
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
V
V
M
M
CP INPUT
GND
t
W
t
t
PLH
PHL
V
I
V
OH
V
Yn OUTPUT
M
V
nOE INPUT
GND
M
V
OL
NOTE: V = 0.5V at V = 2.3 to 2.7 V
M
CC
CC
SH00135
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
t
t
PZL
PLZ
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
I
V
X
An
INPUT
V
M
V
OL
GND
t
t
PZH
th
th
PHZ
t
t
SU
SU
V
OH
V
I
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
Y
LE
INPUT
V
M
V
M
GND
GND
outputs
enabled
outputs
disabled
outputs
enabled
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
= 0.5V at V = 2.3 to 2.7 V
M
CC CC
NOTE: V = 0.5V at V = 2.3 to 2.7 V
M
CC
CC
SH00166
SH00137
Waveform 6. 3-state enable and disable times
Waveform 4. Data set-up and hold times for the An input to the
LE input
7
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
TEST CIRCUIT
GRAPHS
S
0
–50
1
2 * V
V
CC
CC
Open
GND
1.8V
2.5V
–100
–150
–200
–250
–300
–350
R
R
L
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
R
T
C
L
3.3V
PMOS
Test Circuit for switching times
0
0.5
1.0
V
1.5
2.0
2.5
3.0
3.5
DEFINITIONS
(V) OUTPUT VOLTAGE
R
L
C
L
R
T
= Load resistor
OH
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z of pulse generators.
SH00161
OUT
SWITCH POSITION
–350
–300
–250
–200
–150
–100
–50
TEST
S
V
V
R
L
1
CC
I
t
t
Open
< 2.3 V
2.3–2.7 V
3.0 V
V
V
1000 Ω
500 Ω
500 Ω
PLH/ PHL
CC
CC
t
t
t
PLZ/ PZL
2 < V
CC
3.3V
t
GND
V
CC
PHZ/ PZH
SV01018
2.5V
Waveform 7. Load circuitry for switching times
1.8V
NMOS
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
(V) OUTPUT VOLTAGE
OH
SH00162
8
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
9
1999 Jul 23
Philips Semiconductors
Preliminary specification
18-bit registered driver with inverted register enable
(3-State)
74AVC16834
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 07-99
9397-750-06249
Document order number:
Philips
Semiconductors
相关型号：
74AVC16834ADGG
18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)
NXP
74AVC16834ADGG,118
74AVC16834A - 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs(TM) (3-State) TSSOP 56-Pin
NXP
74AVC16834ADGV
18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)
NXP
74AVC16834ADGV,112
74AVC16834A - 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs(TM) (3-State) TSSOP 56-Pin
NXP
74AVC16834ADGV,118
74AVC16834A - 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs(TM) (3-State) TSSOP 56-Pin
NXP
©2020 ICPDF网 联系我们和版权申明