74AVC16T245EV [NXP]
16-bit dual supply translating transceiver with configurable voltage translation; 3-state; 16位双电源转换收发器可配置电压转换;三态
| 型号： | 74AVC16T245EV |
| 厂家： | 
NXP |
| 描述： | 16-bit dual supply translating transceiver with configurable voltage translation; 3-state |
| 文件： | 总28页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVC16T245
16-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 3 — 9 June 2011
Product data sheet
1. General description
The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and
3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit
transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit
input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive
(nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation
between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH
on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission
from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance
OFF-state
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both nAn and nBn are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
200 Mbit/s ( 1.1 V to 3.3 V translation)
200 Mbit/s ( 1.1 V to 2.5 V translation)
200 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVC16T245DGG
74AVC16T245DGV
74AVC16T245EV
74AVC16T245BX
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
TSSOP48
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
TSSOP48[1] plastic thin shrink small outline package; 48 leads; SOT480-1
body width 4.4 mm; lead pitch 0.4 mm
VFBGA56
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5 7 0.65 mm
HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1
package; no leads; 60 terminals; UTLP based;
body 4 6 0.5 mm
[1] Also known as TVSOP48.
4. Functional diagram
1DIR
1A1
2DIR
1OE
1B1
2OE
2A1
2B1
V
V
V
V
CC(B)
CC(A)
CC(B)
CC(A)
to other seven channels
to other seven channels
001aak426
Fig 1. Logic diagram
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
2 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
V
V
CC(B)
CC(A)
1OE
1DIR
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
V
V
CC(B)
CC(A)
2OE
2DIR
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
001aak425
Fig 2. Logic symbol
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
3 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
74AVC16T245
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
3
4
5
6
7
V
V
CC(A)
CC(B)
8
1B5
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ball A1
index area
74AVC16T245
1
2 3 4 5 6
A
B
C
D
E
F
V
V
CC(A)
CC(B)
2B5
2A5
2A6
GND
2A7
2A8
2OE
2B6
GND
2B7
G
H
J
2B8
K
2DIR
001aak428
Transparent top view
001aak427
Fig 3. Pin configuration SOT362-1 and SOT480-1
(TSSOP48)
Fig 4. Pin configuration SOT702-1 (VFBGA56)
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
4 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
terminal 1
index area
D1
A32
D5
A31
A30
A29
A28
A27
D8
D4
B20
B19
B18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
B1
B2
B3
B4
B5
B6
B7
B17
B16
B15
B14
B13
B12
B11
74AVC16T245
(1)
GND
D6
B8
B9
B10
D7
D2
A11
A12
A13
A14
A15
A16
D3
001aak429
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 5. Pin configuration SOT1134-1 (HXQFN60U)
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
5 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SOT362-1 and
SOT480-1
SOT702-1
SOT1134-1
1DIR, 2DIR 1, 24
A1, K1
A30, A13
direction control
1B1 to 1B8 2, 3, 5, 6, 8, 9, 11, 12 B2, B1, C2, C1,
D2, D1, E2, E1
B20, A31, D5, D1,
A2, B2, B3, A5
data input or output
2B1 to 2B8 13, 14, 16, 17, 19, 20, F1, F2, G1, G2,
A6, B5, B6, A9, D2, data input or output
D6, A12, B8
22, 23
H1, H2, J1, J2
GND[1]
4, 10, 15, 21, 28, 34, B3, D3, G3, J3, J4, A32, A3, A8, A11,
ground (0 V)
39, 45
G4, D4, B4
A16, A19, A24, A27
VCC(B)
7, 18
C3, H3
A1, A10
supply voltage B (nBn inputs are
referenced to VCC(B)
)
1OE, 2OE
48, 25
A6, K6
A29, A14
output enable input (active LOW)
data input or output
1A1 to 1A8 47, 46, 44, 43, 41, 40, B5, B6, C5, C6,
38, 37 D5, D6, E5, E6
B18, A28, D8, D4,
A25, B16, B15, A22
2A1 to 2A8 36, 35, 33, 32, 30, 29, F6, F5, G6, G5,
A21, B13, B12, A18, data input or output
D3, D7, A15, B10
27, 26
H6, H5, J6, J5
VCC(A)
n.c.
31, 42
C4, H4
A17, A26
supply voltage A (nAn, nOE and nDIR
inputs are referenced to VCC(A)
)
-
A2, A3, A4, A5, K2, A4, A7, A20, A23,
not connected
K3, K4, K5
B1, B4, B7, B9, B11,
B14, B17, B19
[1] All GND pins must be connected to ground (0 V).
6. Functional description
Table 3.
Function table[1]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[3]
Input
nOE[2]
Input/output[3]
nAn[2]
nDIR[2]
nBn[2]
L
L
nAn = nBn
input
L
H
X
X
input
Z
nBn = nAn
H
X
Z
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B)
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
.
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
6 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
0.5
0.5
-
Max
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
+4.6
+4.6
V
VI < 0 V
-
mA
V
[1]
VI
+4.6
IOK
output clamping current
output voltage
VO < 0 V
-
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+4.6
50
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
V
[2]
IO
output current
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
100
65
-
storage temperature
total power dissipation
+150
Tamb = 40 C to +125 C;
TSSOP48 package
[4]
[5]
[5]
-
-
-
500
mW
mW
mW
VFBGA56 package
1000
1000
HXQFN60U package
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] CCO is the supply voltage associated with the output port.
V
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[5] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
supply voltage A
supply voltage B
input voltage
3.6
V
3.6
V
[1]
[2]
VO
output voltage
Active mode
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
40
-
+125
5
C
ns/V
t/V
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] CCI is the supply voltage associated with the input port.
V
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
7 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
9. Static characteristics
Table 6.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Typical static characteristics at Tamb = 25 C[1][2]
Symbol Parameter Conditions
VOH HIGH-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
LOW-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
Min
Typ
0.69
0.07
Max
Unit
V
-
-
-
VOL
-
-
V
II
input leakage current
nDIR, nOE input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
0.025 0.25 A
[3]
[3]
[3]
IOZ
OFF-state output current
A or B port; VO = 0 V or VCCO
VCC(A) = VCC(B) = 3.6 V
;
-
-
-
-
-
-
-
0.5
0.5
0.5
0.1
0.1
2.0
2.5
2.5
2.5
1
A
A
A
A
A
pF
pF
suspend mode A port; VO = 0 V or VCCO
CC(A) = 3.6 V; VCC(B) = 0 V
;
;
V
suspend mode B port; VO = 0 V or VCCO
VCC(A) = 0 V; VCC(B) = 3.6 V
IOFF
power-off leakage current A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
1
CI
input capacitance
nDIR, nOE input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
-
CI/O
input/output capacitance
A and B port; VO = 3.3 V or 0 V;
VCC(A) = VCC(B) = 3.3 V
4.5
-
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 7.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Static characteristics [1][2]
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 0.8 V
0.70VCCI
0.65VCCI
1.6
-
-
-
-
0.70VCCI
0.65VCCI
1.6
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
nDIR, nOE input
2
2
VCC(A) = 0.8 V
0.70VCC(A)
-
-
-
-
0.70VCC(A)
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
0.65VCC(A)
0.65VCC(A)
1.6
2
1.6
2
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
8 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIL
LOW-level
data input
input voltage
VCCI = 0.8 V
-
-
-
-
0.30VCCI
0.35VCCI
0.7
-
-
-
-
0.30VCCI
0.35VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
nDIR, nOE input
VCC(A) = 0.8 V
0.8
0.8
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
VI = VIH or VIL
0.8
0.8
VOH
HIGH-level
output voltage
IO = 100 A;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCCO 0.1
0.85
-
-
-
-
-
-
VCCO 0.1
0.85
-
-
-
-
-
-
V
V
V
V
V
V
IO = 3 mA;
VCC(A) = VCC(B) = 1.1 V
IO = 6 mA;
VCC(A) = VCC(B) = 1.4 V
1.05
1.05
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
1.2
1.2
IO = 9 mA;
VCC(A) = VCC(B) = 2.3 V
1.75
1.75
IO = 12 mA;
2.3
2.3
VCC(A) = VCC(B) = 3.0 V
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
-
0.1
-
0.1
V
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
-
-
-
0.25
0.35
0.45
-
-
-
0.25
0.35
0.45
V
V
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
-
-
0.55
0.7
-
-
0.55
0.7
V
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
II
input leakage nDIR, nOE input; VI = 0 V or 3.6 V;
-
-
-
1
5
5
-
-
-
5
A
A
A
current
VCC(A) = VCC(B) = 0.8 V to 3.6 V
[3]
[3]
IOZ
OFF-state
A or B port; VO = 0 V or VCCO
;
30
30
output current VCC(A) = VCC(B) = 3.6 V
suspend mode A port;
VO = 0 V or VCCO; VCC(A) = 3.6 V;
VCC(B) = 0 V
[3]
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
VCC(B) = 3.6 V
-
5
-
30
A
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
9 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
5
-
30
A
A
B port; VI or VO = 0 V to 3.6 V;
-
5
-
30
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
-
30
25
-
-
125
100
A
A
VCC(A) = 1.1 V to 3.6 V;
CC(B) = 1.1 V to 3.6 V
V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
B port; VI = 0 V or VCCI; IO = 0 A
-
25
-
-
100
-
A
A
5
20
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
-
30
25
-
-
125
100
A
A
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
V
CC(A) = 3.6 V; VCC(B) = 0 V
5
-
-
20
-
A
A
A
VCC(A) = 0 V; VCC(B) = 3.6 V
A plus B port (ICC(A) + ICC(B));
25
55
-
-
100
185
-
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
;
A plus B port (ICC(A) + ICC(B));
-
45
-
150
A
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
;
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 8.
VCC(A)
Typical total supply current (ICC(A) + ICC(B)
VCC(B)
)
Unit
0 V
0
0.8 V
0.1
0.1
0.1
0.1
0.1
0.3
1.6
1.2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.8
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
1.8 V
2.5 V
0.1
0.3
0.1
0.1
0.1
0.1
0.1
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
0 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
A
A
A
A
A
A
A
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
10 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 9.
Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) = VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
CPD
power dissipation A port: (direction nAn to
0.2
0.2
0.2
0.2
0.3
0.4
pF
pF
pF
pF
pF
pF
pF
pF
capacitance
nBn); output enabled
A port: (direction nAn to
nBn); output disabled
0.2
9
0.2
9.7
0.6
9.7
0.6
0.2
0.2
0.2
9.8
0.6
9.8
0.6
0.2
0.2
0.2
10.3
0.7
0.3
11.7
0.7
0.4
13.7
0.7
A port: (direction nBn to
nAn); output enabled
A port: (direction nBn to
nAn); output disabled
0.6
9
B port: (direction nAn to
nBn); output enabled
10.3
0.7
11.7
0.7
13.7
0.7
B port: (direction nAn to
nBn); output disabled
0.6
0.2
0.2
B port: (direction nBn to
nAn); output enabled
0.2
0.3
0.4
B port: (direction nBn to
nAn); output disabled
0.2
0.3
0.4
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = .
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
11 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(B)
1.5 V
Unit
0.8 V
14.4
14.4
16.2
17.6
21.9
22.2
1.2 V
7.0
1.8 V
6.0
2.5 V
5.9
3.3 V
6.0
tpd
tdis
ten
propagation delay nAn to nBn
nBn to nAn
6.2
12.1
16.2
9.0
ns
ns
ns
ns
ns
ns
12.4
16.2
10.0
21.9
11.1
11.9
16.2
9.1
11.8
16.2
8.7
11.8
16.2
9.3
disable time
nOE to nAn
nOE to nBn
nOE to nAn
nOE to nBn
enable time
21.9
9.8
21.9
9.4
21.9
9.4
21.9
9.6
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(A)
1.5 V
Unit
0.8 V
14.4
14.4
16.2
17.6
21.9
22.2
1.2 V
12.4
7.0
1.8 V
11.9
6.0
2.5 V
11.8
5.9
3.3 V
11.8
6.0
tpd
tdis
ten
propagation delay nAn to nBn
nBn to nAn
12.1
6.2
ns
ns
ns
ns
ns
ns
disable time
nOE to nAn
nOE to nBn
nOE to nAn
nOE to nBn
5.9
4.4
4.2
3.1
3.5
14.2
6.4
13.7
4.4
13.6
3.5
13.3
2.6
13.1
2.3
enable time
17.7
17.2
17.0
16.8
16.7
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
12 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation nAn to nBn
0.5
0.5
1.5
1.5
1.0
1.1
9.2
9.2
0.5
0.5
1.5
1.5
1.0
1.1
6.9
8.7
0.5
0.5
1.5
1.5
1.0
1.1
6.0
8.5
0.5
0.5
1.5
1.0
1.0
1.0
5.1
8.2
0.5
0.5
1.5
1.0
1.0
1.0
4.9 ns
8.0 ns
11.6 ns
8.9 ns
14.5 ns
7.7 ns
delay
nBn to nAn
disable time nOE to nAn
nOE to nBn
11.6
12.5
14.5
14.9
11.6
9.7
11.6
9.5
11.6
8.1
enable time nOE to nAn
nOE to nBn
14.5
11.0
14.5
9.6
14.5
8.1
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
1.5
1.5
1.0
1.0
8.7
6.9
0.5
0.5
1.5
1.5
1.0
1.0
6.2
6.2
0.5
0.5
1.5
1.5
1.0
0.5
5.2
5.9
0.5
0.5
1.5
1.0
1.0
0.5
4.1
5.6
0.5
0.5
1.5
1.0
1.0
0.5
3.7 ns
5.5 ns
9.1 ns
6.3 ns
10.1 ns
5.2 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
9.1
9.1
9.1
7.5
10.1
8.1
9.1
11.4
10.1
13.5
8.7
6.5
enable time nOE to nAn
nOE to nBn
10.1
10.1
10.1
5.9
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
1.5
1.5
1.0
1.0
8.5
6.0
0.5
0.5
1.5
1.5
1.0
1.0
5.9
5.2
7.7
8.4
7.8
9.2
0.5
0.5
1.5
1.5
1.0
0.5
4.8
4.8
7.7
7.1
7.8
7.4
0.5
0.5
1.5
1.0
1.0
0.5
3.7
4.5
7.7
5.9
7.8
5.3
0.5
0.5
1.5
1.0
1.0
0.5
3.3 ns
4.4 ns
7.7 ns
5.7 ns
7.8 ns
4.5 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
7.7
11.1
7.8
enable time nOE to nAn
nOE to nBn
13.0
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
1.0
1.0
0.5
0.5
8.2
5.1
0.5
0.5
1.0
1.0
0.5
0.5
5.6
4.1
6.1
7.9
5.3
9.4
0.5
0.5
1.0
1.0
0.5
0.5
4.6
3.7
6.1
6.6
5.3
7.3
0.5
0.5
1.0
1.0
0.5
0.5
3.3
3.4
6.1
6.1
5.3
5.1
0.5
0.5
1.0
1.0
0.5
0.5
2.8 ns
3.2 ns
6.1 ns
5.2 ns
5.3 ns
4.5 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
6.1
10.6
5.3
enable time nOE to nAn
nOE to nBn
12.5
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
0.5
1.0
0.5
0.5
8.0
4.9
0.5
0.5
0.5
1.0
0.5
0.5
5.5
3.7
5.0
7.7
4.3
9.3
0.5
0.5
0.5
1.0
0.5
0.5
4.4
3.3
5.0
6.5
4.2
7.2
0.5
0.5
0.5
1.0
0.5
0.5
3.2
2.9
5.0
5.2
4.1
4.9
0.5
0.5
0.5
0.5
0.5
0.5
2.7 ns
2.7 ns
5.0 ns
5.0 ns
4.0 ns
4.0 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
5.0
10.3
4.3
enable time nOE to nAn
nOE to nBn
12.4
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVC16T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
13 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation nAn to nBn
0.5
0.5
1.5
1.5
1.0
1.1
10.2
10.2
12.8
13.8
16.0
16.4
0.5
0.5
1.5
1.5
1.0
1.1
7.6
9.6
0.5
0.5
1.5
1.5
1.0
1.1
6.6
9.4
0.5
0.5
1.5
1.0
1.0
1.0
5.7
9.1
0.5
0.5
1.5
1.5
1.0
1.0
5.4 ns
8.8 ns
12.8 ns
9.8 ns
16.0 ns
8.5 ns
delay
nBn to nAn
disable time nOE to nAn
nOE to nBn
12.8
10.7
16.0
12.1
12.8
10.5
16.0
10.6
12.8
9.0
enable time nOE to nAn
nOE to nBn
16.0
9.0
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
1.5
1.5
1.0
1.0
9.6
7.6
0.5
0.5
1.5
1.5
1.0
1.0
6.9
6.9
0.5
0.5
1.5
1.5
1.0
0.5
5.8
6.5
0.5
0.5
1.5
1.0
1.0
0.5
4.6
6.2
0.5
0.5
1.5
1.0
1.0
0.5
4.1 ns
6.1 ns
10.1 ns
7.0 ns
11.2 ns
5.8 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
10.1
12.6
11.2
14.9
10.1
9.6
10.1
8.3
10.1
7.2
enable time nOE to nAn
nOE to nBn
11.2
11.2
11.2
9.0
11.2
6.5
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
1.5
1.5
1.0
1.0
9.4
6.6
0.5
0.5
1.5
1.5
1.0
1.0
6.5
5.8
0.5
0.5
1.5
1.5
1.0
0.5
5.3
5.3
8.5
7.9
8.6
8.2
0.5
0.5
1.5
1.0
1.0
0.5
4.1
5.0
8.5
6.5
8.6
5.9
0.5
0.5
1.5
1.0
1.0
0.5
3.7 ns
4.9 ns
8.5 ns
6.3 ns
8.6 ns
5.0 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
8.5
8.5
9.3
8.6
10.2
12.3
8.6
enable time nOE to nAn
nOE to nBn
14.3
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
1.0
1.0
0.5
0.5
9.1
5.7
0.5
0.5
1.0
1.0
0.5
0.5
6.2
4.6
0.5
0.5
1.0
1.0
0.5
0.5
5.1
4.1
6.8
7.3
5.9
8.1
0.5
0.5
1.0
1.0
0.5
0.5
3.7
3.8
6.8
6.8
5.9
5.7
0.5
0.5
1.0
1.0
0.5
0.5
3.1 ns
3.6 ns
6.8 ns
5.8 ns
5.9 ns
5.0 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
6.8
6.8
11.7
5.9
8.7
5.9
enable time nOE to nAn
nOE to nBn
13.8
10.4
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation nAn to nBn
delay
0.5
0.5
0.5
1.0
0.5
0.5
8.8
5.4
0.5
0.5
0.5
1.0
0.5
0.5
6.1
4.1
0.5
0.5
0.5
1.0
0.5
0.5
4.9
3.7
5.5
7.2
4.7
8.0
0.5
0.5
0.5
1.0
0.5
0.5
3.6
3.2
5.5
5.8
4.6
5.4
0.5
0.5
0.5
0.5
0.5
0.5
3.0 ns
3.0 ns
5.5 ns
5.5 ns
4.4 ns
4.4 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
5.5
5.5
11.4
4.8
8.5
4.8
enable time nOE to nAn
nOE to nBn
13.7
10.3
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
14 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
11. Waveforms
V
I
nAn, nBn input
GND
V
M
t
t
PLH
PHL
V
OH
nBn, nAn output
V
M
V
OL
001aak285
Measurement points are given in Table 14.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 6. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times
V
I
V
nOE input
M
GND
t
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aak286
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
Output[2]
VM
VM
VX
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVC16T245
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
15 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuit for switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[3]
t/V[2]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCCO
VCCI
VCCI
VCCI
1.0 ns/V
1.0 ns/V
1.0 ns/V
15 pF
15 pF
15 pF
2 k
2 k
2 k
open
GND
2VCCO
open
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns
[3]
VCCO is the supply voltage associated with the output port.
74AVC16T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 June 2011
16 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aai476
001aai477
24
21
(1)
(2)
(3)
(4)
(5)
(6)
t
pd
(ns)
t
pd
(1)
(ns)
20
17
16
12
8
13
(2)
(3)
(4)
(5)
(6)
4
9
0
20
40
60
0
20
40
60
C
L
(pF)
C (pF)
L
a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V
(1) VCC(B) = 0.8 V.
b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V
(1)
(2)
V
V
CC(A) = 0.8 V.
CC(A) = 1.2 V.
(2)
VCC(B) = 1.2 V.
(3) VCC(B) = 1.5 V.
(4) VCC(B) = 1.8 V.
(3) VCC(A) = 1.5 V.
(4) VCC(A) = 1.8 V.
(5)
V
CC(B) = 2.5 V.
(5)
VCC(A) = 2.5 V.
(6) VCC(B) = 3.3 V.
(6) VCC(A) = 3.3 V.
Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
17 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
001aai478
001aai491
7
7
(1)
t
t
PHL
PLH
(ns)
(ns)
(1)
(2)
(3)
5
3
1
5
3
1
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (nAn to nBn);
VCC(A) = 1.2 V
b. HIGH to LOW propagation delay (nAn to nBn);
VCC(A) = 1.2 V
001aai479
001aai480
7
7
(1)
t
t
PHL
PLH
(ns)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (nAn to nBn);
VCC(A) = 1.5 V
d. HIGH to LOW propagation delay (nAn to nBn);
CC(A) = 1.5 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
18 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
001aai481
001aai482
7
7
(1)
t
t
PHL
PLH
(ns)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (nAn to nBn);
VCC(A) = 1.8 V
b. HIGH to LOW propagation delay (nAn to nBn);
VCC(A) = 1.8 V
001aai483
001aai486
7
7
t
t
PHL
(ns)
PLH
(1)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (nAn to nBn);
VCC(A) = 2.5 V
d. HIGH to LOW propagation delay (nAn to nBn);
CC(A) = 2.5 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
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74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
001aai485
001aai484
7
7
t
t
PHL
(ns)
PLH
(1)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (nAn to nBn);
VCC(A) = 3.3 V
b. HIGH to LOW propagation delay (nAn to nBn);
VCC(A) = 3.3 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 C
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
20 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
13. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 13. Package outline SOT362-1 (TSSOP48)
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
21 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads;
body width 4.4 mm; lead pitch 0.4 mm
SOT480-1
E
A
D
X
c
y
H
E
v
M
A
Z
25
48
Q
(A )
3
A
A
2
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.85
0.23
0.13
0.20
0.09
9.8
9.6
4.5
4.3
6.6
6.2
0.7
0.5
0.4
0.3
0.4
0.1
mm
1.1
0.4
0.25
1
0.2
0.07
0.08
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT480-1
MO-153
Fig 14. Package outline SOT480-1 (TSSOP48)
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
22 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
∅ v M
∅ w M
C
C
A B
b
e
y
y
C
1
1/2 e
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2 e
X
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
A
A
A
b
e
y
UNIT
D
E
e
e
v
w
y
1
1
2
0
2.5
5 mm
1
2
max.
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
scale
mm
1
3.25 5.85
0.08
0.1
0.65
0.15 0.08
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
02-08-08
03-07-01
SOT702-1
MO-225
Fig 15. Package outline SOT702-1 (VFBGA56)
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
23 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads;
60 terminals; UTLP based; body 4 x 6 x 0.5 mm
SOT1134-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
2
e
1
1/2 e
b
C
e
v
C A
C
B
v
C A
C
B
y
y
w
w
C
1
L
1
D2
D6
A11
A16
D3
B8 B10
D7
A10
B7
A17
e
L
e
R
B11
E
h
e
3
e
4
1/2 e
B1
A1
B17
A26
terminal 1
index area
D5
D1
B20 B18
D8
X
A32
A27
D4
D
h
k
0
2.5
scale
5 mm
eR
Dimensions
Unit
A
A
b
D
D
h
E
E
h
e
e
1
e
2
e
3
e
4
k
L
L
v
w
y
y
1
1
1
max 0.50 0.05 0.35 4.1 1.90 6.1 3.90
0.25 0.35 0.125
mm nom 0.48 0.02 0.30 4.0 1.85 6.0 3.85 0.5
min 0.46 0.00 0.25 3.9 1.80 5.9 3.80
1
2.5
3
4.5 0.5 0.20 0.30 0.075 0.07 0.05 0.08 0.1
0.15 0.25 0.025
sot1134-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
08-12-17
09-01-22
SOT1134-1
Fig 16. Package outline SOT1134-1 (HXQFN60U)
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
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74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
14. Abbreviations
Table 16. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
15. Revision history
Table 17. Revision history
Document ID
Release date
20110609
Data sheet status
Change notice
Supersedes
74AVC16T245 v.3
Modifications:
Product data sheet
-
74AVC16T245 v.2
• 74AVC16T245BQ changed to 74AVC16T245BX for HXQFN60U (SOT1134-1) package.
20100330 Product data sheet 74AVC16T245 v.1
74AVC16T245 v.2
Modifications:
-
• 74AVC16T245BQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1)
package.
74AVC16T245 v.1
20091001
Product data sheet
-
-
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
25 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
16.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
26 of 28
74AVC16T245
NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AVC16T245
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Product data sheet
Rev. 3 — 9 June 2011
27 of 28
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NXP Semiconductors
16-bit dual supply translating transceiver; 3-state
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical propagation delay characteristics . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 June 2011
Document identifier: 74AVC16T245
相关型号：
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DIODES
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