74AVC4TD245GU_技术文档

74AVC4TD245

4-bit dual supply translating transceiver with configurable

voltage translation; 3-state

Rev. 1 — 3 May 2011

Product data sheet

1. General description

The 74AVC4TD245 is a 4-bit, dual supply transceiver that enables bidirectional level

translation. It features eight 1-bit input-output ports (An and Bn), four direction control

inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins

(V_CC(A)and V_CC(B)). Both V_CC(A)and V_CC(B)can be supplied at any voltage between 0.8 V

and 3.6 V making the device suitable for translating between any of the low voltage nodes

(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to

V

_CC(A)and pins Bn are referenced to V_CC(B). A HIGH on DIRn allows transmission from An

to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input

(OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V_CC(A)or V_CC(B)are at

GND level, both An and Bn are in the high-impedance OFF-state.

2. Features and benefits

Wide supply voltage range:

V_CC(A): 0.8 V to 3.6 V

V_CC(B): 0.8 V to 3.6 V

Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114E Class 3B exceeds 8000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Maximum data rates:

380 Mbit/s (≥ 1.8 V to 3.3 V translation)

200 Mbit/s (≥ 1.1 V to 3.3 V translation)

200 Mbit/s (≥ 1.1 V to 2.5 V translation)

200 Mbit/s (≥ 1.1 V to 1.8 V translation)

150 Mbit/s (≥ 1.1 V to 1.5 V translation)

100 Mbit/s (≥ 1.1 V to 1.2 V translation)

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Suspend mode

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

I_OFFcircuitry provides partial Power-down mode operation

Multiple package options

Specified from −40 °C to +85 °C and −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

Type number

Description

Version

74AVC4TD245PW −40 °C to +125 °C

TSSOP16

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

74AVC4TD245BQ −40 °C to +125 °C

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

74AVC4TD245GU −40 °C to +125 °C

XQFN16

plastic, extremely thin quad flat package; no leads; SOT1161-1

16 terminals; body 1.80 x 2.60 x 0.50 mm

4. Marking

Table 2.

Marking codes

Type number

Marking code

C4TD245

4TD245

74AVC4TD245PW

74AVC4TD245BQ

74AVC4TD245GU

BD4

5. Functional diagram

B1

B2

B3

B4

V

CC(B)

V

CC(A)

A1 DIR1

A2 DIR2

A3 DIR3

A4 DIR4

OE

001aao069

Fig 1. Logic symbol

74AVC4TD245

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Product data sheet

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2 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

OE

An

DIRn

Bn

V

CC(B)

CC(A)

to next transceiver

001aao070

Fig 2. Logic diagram (one 1-bit transceiver)

6. Pinning information

6.1 Pinning

74AVC4TD245

terminal 1

index area

74AVC4TD245

2

3

4

5

6

7

15

DIR1

A1

DIR2

B1

14

13

12

11

10

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC(B)

CC(A)

A2

B2

DIR1

DIR2

B1

A1

A2

A3

B3

B2

(1)

A4

B4

GND

A3

B3

DIR4

DIR3

A4

B4

DIR4

GND

DIR3

OE

001aao071

Transparent top view

001aao072

(1) This is not a supply pin, the substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad

however if it is soldered the solder land should remain

floating or be connected to GND.

Fig 3. Pin configuration SOT403-1 (TSSOP16)

Fig 4. Pin configuration SOT763-1 (DHVQFN16)

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

3 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

74AVC4TD245

terminal 1

index area

DIR2

1

2

3

4

12 DIR3

11 OE

V

CC(B)

10 GND

CC(A)

DIR1

9

DIR4

001aao073

Transparent top view

Fig 5. Pin configuration SOT1161-1 (XQFN16)

6.2 Pin description

Table 3.

Symbol

Pin description

Description

SOT403-1 and

SOT763-1

SOT1161-1

V_CC(A)

1

3

supply voltage A (An, OE and DIRn inputs are

referenced to V_CC(A)

)

DIR1, DIR2, DIR3, DIR4 2, 15, 10, 7

4, 1, 12, 9

direction control input

A1, A2, A3, A4

GND

3, 4, 5, 6

5, 6, 7, 8

data input or output

8

10

ground (0 V)

B1, B2, B3, B4

OE

14, 13, 12, 11

16, 15, 14, 13

data input or output

9

11

2

output enable input (active LOW)

supply voltage B (Bn pins are referenced to V_CC(B)

V_CC(B)

16

)

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

4 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

7. Functional description

Table 4.

Function table^[1][2]

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 3.6 V

GND^[3]

Input

Input/output

OE

L

DIR1

L

DIR2

X

DIR3

X

DIR4

X

An

Bn

A1 = B1

input A1

A2 = B2

input A2

A3 = B3

input A3

A4 = B4

input A4

Z

input B1

B1 = A1

input B2

B2 = A2

input B3

B3 = A3

input B4

B4 = A4

Z

L

H

X

L

X

L

X

L

X

H

X

L

X

L

X

L

X

H

X

L

X

L

X

H

X

Z

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

[2] The An, DIRn and OE input circuit is referenced to V_CC(A); The Bn input circuit is referenced to V_CC(B)

[3] If at least one of V_CC(A)or V_CC(B)is at GND level, the device goes into suspend mode.

.

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC(A)

V_CC(B)

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

-

Max

Unit

V

supply voltage A

supply voltage B

input clamping current

input voltage

+4.6

V

V_I< 0 V

-

mA

V

[1]

V_I

+4.6

I_OK

output clamping current

output voltage

V_O< 0 V

-

mA

V

[1][2][3]

[1]

V_O

Active mode

V_CCO+ 0.5

+4.6

±50

Suspend or 3-state mode

V_O= 0 V to V_CCO

I_CC(A)or I_CC(B)

V

[2]

I_O

output current

mA

°C

I_CC

I_GND

T_stg

supply current

-

100

ground current

storage temperature

−100

−65

-

+150

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Product data sheet

Rev. 1 — 3 May 2011

5 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Table 5.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

P_tot

total power dissipation

T_amb= −40 °C to +125 °C

TSSOP16 and DHVQFN16

XQFN16

[4]

-

500

250

mW

[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] V_CCOis the supply voltage associated with the output port.

[3] V_CCO+ 0.5 V should not exceed 4.6 V.

[4] For TSSOP16 package: above 60 °C the value of P_totderates linearly at 5.5 mW/K.

For DHVQFN16 package: above 60 °C the value of P_totderates linearly at 4.5 mW/K.

For XQFN16 package: above 133 °C the value of P_totderates linearly with 14.5 mW/K.

9. Recommended operating conditions

Table 6.

Symbol

V_CC(A)

V_CC(B)

V_I

Recommended operating conditions

Parameter

Conditions

Min

0.8

0

Max

3.6

Unit

V

supply voltage A

supply voltage B

input voltage

3.6

V

3.6

V

[1]

[2]

V_O

output voltage

Active mode

0

V_CCO

3.6

V

Suspend or 3-state mode

0

V

T_amb

ambient temperature

−40

-

+125

10

°C

ns/V

Δt/ΔV

input transition rise and fall rate

V_CCI=0.8 V to 3.6 V

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the input port.

10. Static characteristics

Table 7.

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Typical static characteristics at T_amb= 25 °C^[1][2]

Symbol Parameter Conditions

V_OHHIGH-level output voltage V_I= V_IHor V_IL

I_O= −1.5 mA; V_CC(A)= V_CC(B)= 0.8 V

LOW-level output voltage V_I= V_IHor V_IL

I_O= 1.5 mA; V_CC(A)= V_CC(B)= 0.8 V

Min

Typ

0.69

0.07

Max

Unit

-

V

V_OL

-

I_I

input leakage current

DIRn, OE input; V_I= 0 V or 3.6 V;

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

±0.025 ±0.25 μA

[3]

I_OZ

OFF-state output current

A or B port; V_O= 0 V or V_CCO

V_CC(A)= V_CC(B)= 3.6 V

;

-

±0.5

±2.5

μA

suspend mode A port; V_O= 0 V or V_CCO

V_CC(A)= 3.6 V; V_CC(B)= 0 V

;

suspend mode B port; V_O= 0 V or V_CCO

V_CC(A)= 0 V; V_CC(B)= 3.6 V

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

6 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Table 7.

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Typical static characteristics at T_amb= 25 °C^[1][2]…continued

Symbol Parameter Conditions

Min

Typ

Max

Unit

I_OFF

power-off leakage current A port; V_Ior V_O= 0 V to 3.6 V;

V_CC(A)= 0 V; V_CC(B)= 0.8 V to 3.6 V

-

±0.1

±1

μA

B port; V_Ior V_O= 0 V to 3.6 V;

-

±0.1

2.0

±1

-

μA

pF

V_CC(B)= 0 V; V_CC(A)= 0.8 V to 3.6 V

C_I

input capacitance

DIRn, OE input; V_I= 0 V or 3.3 V;

V_CC(A)= V_CC(B)= 3.3 V

C_I/O

input/output capacitance

A and B port; V_O= 3.3 V or 0 V;

V_CC(A)= V_CC(B)= 3.3 V

4.0

-

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the data input port.

[3] For I/O ports, the parameter I_OZincludes the input leakage current.

Table 8.

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Static characteristics ^[1][2]

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Max

Min

Max

V_IH

HIGH-level

data input

input voltage

V_CCI= 0.8 V

0.70V_CCI

0.65V_CCI

1.6

-

0.70V_CCI

0.65V_CCI

1.6

-

V

V_CCI= 1.1 V to 1.95 V

V_CCI= 2.3 V to 2.7 V

V_CCI= 3.0 V to 3.6 V

DIRn, OE input

V

2

V_CC(A)= 0.8 V

0.70V_CC(A)

-

0.70V_CC(A)

-

V

V_CC(A)= 1.1 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

data input

0.65V_CC(A)

1.6

2

1.6

2

V_IL

LOW-level

input voltage

V_CCI= 0.8 V

-

0.30V_CCI

0.35V_CCI

0.7

-

0.30V_CCI

0.35V_CCI

0.7

V

V_CCI= 1.1 V to 1.95 V

V_CCI= 2.3 V to 2.7 V

V_CCI= 3.0 V to 3.6 V

DIRn, OE input

0.8

V_CC(A)= 0.8 V

-

0.30V_CC(A)

0.35V_CC(A)

0.7

-

0.30V_CC(A)

0.35V_CC(A)

0.7

V

V_CC(A)= 1.1 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

0.8

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

7 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

[1][2]

Table 8.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Max

Min

Max

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= −100 μA;

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

V_CCO− 0.1

0.85

-

V_CCO− 0.1

0.85

-

V

I_O= −3 mA;

V

V_CC(A)= V_CC(B)= 1.1 V

I_O= −6 mA;

V_CC(A)= V_CC(B)= 1.4 V

1.05

I_O= −8 mA;

1.2

V

_CC(A)= V_CC(B)= 1.65 V

I_O= −9 mA;

_CC(A)= V_CC(B)= 2.3 V

1.75

V

I_O= −12 mA;

2.3

V_CC(A)= V_CC(B)= 3.0 V

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 100 μA;

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

-

0.1

0.25

0.35

0.45

0.55

0.7

-

0.1

0.25

0.35

0.45

0.55

0.7

V

I_O= 3 mA;

V_CC(A)= V_CC(B)= 1.1 V

V

I_O= 6 mA;

V_CC(A)= V_CC(B)= 1.4 V

V

I_O= 8 mA;

V_CC(A)= V_CC(B)= 1.65 V

V

I_O= 9 mA;

V_CC(A)= V_CC(B)= 2.3 V

V

I_O= 12 mA;

V_CC(A)= V_CC(B)= 3.0 V

V

I_I

input leakage DIRn, OE input; V_I= 0 V or 3.6 V;

current

±1

±5

μA

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

[3]

I_OZ

OFF-state

output current V_CC(A)= V_CC(B)= 3.6 V

A or B port; V_O= 0 V or V_CCO

;

±5

±30

suspend mode A port;

±5

V_O= 0 V or V_CCO; V_CC(A)= 3.6 V;

_CC(B)= 0 V

V

[3]

suspend mode B port;

V_O= 0 V or V_CCO; V_CC(A)= 0 V;

V_CC(B)= 3.6 V

-

±5

-

±30

μA

I_OFF

power-off

leakage

current

A port; V_Ior V_O= 0 V to 3.6 V;

V_CC(A)= 0 V;

V_CC(B)= 0.8 V to 3.6 V

B port; V_Ior V_O= 0 V to 3.6 V;

V_CC(B)= 0 V;

V_CC(A)= 0.8 V to 3.6 V

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

8 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

[1][2]

Table 8.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Max

Min

Max

I_CC

supply current A port; V_I= 0 V or V_CCI; I_O= 0 A

V_CC(A)= 0.8 V to 3.6 V;

V_CC(B)= 0.8 V to 3.6 V

-

10

8

-

55

50

μA

V_CC(A)= 1.1 V to 3.6 V;

μA

V_CC(B)= 1.1 V to 3.6 V

V_CC(A)= 3.6 V; V_CC(B)= 0 V

V_CC(A)= 0 V; V_CC(B)= 3.6 V

B port; V_I= 0 V or V_CCI; I_O= 0 A

-

8

-

50

-

μA

−2

−12

V_CC(A)= 0.8 V to 3.6 V;

V_CC(B)= 0.8 V to 3.6 V

-

10

8

-

55

50

μA

V_CC(A)= 1.1 V to 3.6 V;

V_CC(B)= 1.1 V to 3.6 V

V_CC(A)= 3.6 V; V_CC(B)= 0 V

V_CC(A)= 0 V; V_CC(B)= 3.6 V

A plus B port (I_CC(A)+ I_CC(B));

−2

-

−12

-

μA

8

-

50

70

-

20

I_O= 0 A; V_I= 0 V or V_CCI

V_CC(A)= 0.8 V to 3.6 V;

V_CC(B)= 0.8 V to 3.6 V

;

A plus B port (I_CC(A)+ I_CC(B));

-

16

-

65

μA

I_O= 0 A; V_I= 0 V or V_CCI

V_CC(A)= 1.1 V to 3.6 V;

V_CC(B)= 1.1 V to 3.6 V

;

ΔI_CC

additional

V_I= 3.0 V; V_CC(A)= V_CC(B)= 3.6 V

500

650

supply current

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the data input port.

[3] For I/O ports, the parameter I_OZincludes the input leakage current.

Table 9.

V_CC(A)

Typical total supply current (I_CC(A)+ I_CC(B)

V_CC(B)

)

Unit

0 V

0

0.8 V

0.1

0.3

1.6

1.2 V

0.1

0.8

1.5 V

0.1

0.4

1.8 V

0.1

0.2

2.5 V

0.1

0.3

0.1

3.3 V

0 V

0.1

1.6

0.8

0.4

0.2

0.1

μA

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.1

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

9 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

11. Dynamic characteristics

Table 10. Typical power dissipation capacitance at V_CC(A)= V_CC(B)and T_amb= 25 °C ^[1][2]

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

V_CC(A)= V_CC(B)

Unit

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

C_PD

power dissipation A port: (direction An to

0.2

0.3

0.4

pF

capacitance

Bn); output enabled

A port: (direction An to

Bn); output disabled

0.2

9.5

0.6

9.5

0.6

0.2

9.7

0.6

9.7

0.6

0.2

9.8

0.6

9.8

0.6

0.2

9.9

0.6

9.9

0.6

0.2

0.3

10.7

0.7

0.4

11.9

0.7

A port: (direction Bn to

An); output enabled

A port: (direction Bn to

An); output disabled

B port: (direction An to

Bn); output enabled

10.7

0.7

11.9

0.7

B port: (direction An to

Bn); output disabled

B port: (direction Bn to

An); output enabled

0.3

0.4

B port: (direction Bn to

An); output disabled

0.3

0.4

[1] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

[2] f_i= 10 MHz; V_I= GND to V_CC; t_r= t_f= 1 ns; C_L= 0 pF; R_L= ∞ Ω.

74AVC4TD245

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Product data sheet

Rev. 1 — 3 May 2011

10 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Table 11. Typical dynamic characteristics at V_CC(A)= 0.8 V and T_amb= 25 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7

Symbol Parameter

Conditions

V_CC(B)

1.5 V

Unit

0.8 V

14.5

14.3

17.0

18.2

19.2

1.2 V

7.3

1.8 V

6.2

2.5 V

5.9

3.3 V

6.0

t_pd

t_dis

t_en

propagation delay An to Bn

6.5

12.4

14.3

9.0

ns

Bn to An

OE to An

OE to Bn

OE to An

OE to Bn

12.7

14.3

9.9

12.3

14.3

9.4

12.1

14.3

9.0

12.0

14.3

9.7

disable time

enable time

18.2

10.7

18.2

9.8

18.2

9.6

18.2

9.7

18.2

10.2

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

Table 12. Typical dynamic characteristics at V_CC(B)= 0.8 V and T_amb= 25 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7

Symbol Parameter

Conditions

V_CC(A)

1.5 V

Unit

0.8 V

14.5

14.3

17.0

18.2

19.2

1.2 V

12.7

7.3

1.8 V

12.3

6.2

2.5 V

12.1

5.9

3.3 V

12.0

6.0

t_pd

t_dis

t_en

propagation delay An to Bn

12.4

6.5

ns

Bn to An

OE to An

OE to Bn

OE to An

OE to Bn

disable time

enable time

5.5

4.1

4.0

3.0

3.5

13.8

5.6

13.4

4.0

13.1

3.2

12.9

2.4

12.7

2.2

14.6

14.1

13.9

13.7

13.6

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

11 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Table 13. Dynamic characteristics for temperature range −40 °C to +85 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.

Symbol Parameter

Conditions

V_CC(B)

Unit

1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

V_CC(A)= 1.1 V to 1.3 V

t_pd

t_dis

t_en

propagation An to Bn

2.0

10.5

10.0

11.1

13.5

15.0

1.3

1.5

2.0

7.8

9.9

1.2

1.5

2.0

1.0

2.0

6.9

9.7

1.0

1.4

2.0

0.7

2.0

1.0

5.9

9.4

0.8

1.4

2.0

1.0

2.0

1.0

5.7 ns

9.3 ns

10.0 ns

8.0 ns

13.5 ns

7.4 ns

delay

Bn to An

disable time OE to An

OE to Bn

10.0

8.6

10.0

8.0

10.0

7.0

enable time OE to An

OE to Bn

13.5

11.0

13.5

9.4

13.5

7.8

V_CC(A)= 1.4 V to 1.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.5

1.3

1.0

2.0

1.0

2.0

9.9

7.8

1.0

1.5

1.0

1.4

7.1

6.0

7.5

7.9

1.0

0.9

1.0

0.9

1.0

1.3

6.0

6.9

6.0

7.2

7.5

7.7

0.5

0.8

1.0

0.4

1.0

1.1

4.8

6.6

6.0

6.2

7.5

6.4

0.5

0.6

1.0

0.4

1.0

1.1

4.3 ns

6.5 ns

6.0 ns

6.1 ns

7.5 ns

5.6 ns

Bn to An

disable time OE to An

OE to Bn

6.0

10.2

7.5

enable time OE to An

OE to Bn

14.4

V_CC(A)= 1.65 V to 1.95 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.5

1.2

0.5

2.0

1.0

1.5

9.7

6.9

0.9

1.0

0.5

1.5

1.0

1.2

6.9

6.0

5.7

7.0

6.7

7.2

0.8

0.5

0.8

1.0

1.2

5.7

6.9

6.7

6.9

0.5

0.2

1.0

0.8

4.5

5.5

5.7

5.8

6.7

5.4

0.3

0.5

0.2

1.0

0.6

4.0 ns

5.3 ns

5.7 ns

5.9 ns

6.7 ns

5.0 ns

Bn to An

disable time OE to An

OE to Bn

5.7

9.9

enable time OE to An

OE to Bn

6.7

13.9

V_CC(A)= 2.3 V to 2.7 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.4

1.0

0.2

2.0

0.6

1.5

9.4

5.9

0.8

0.5

0.2

1.5

0.6

1.0

6.6

4.8

4.0

6.7

4.5

6.8

0.5

0.2

0.7

0.6

1.0

5.5

4.5

4.0

6.3

4.5

6.0

0.4

0.2

0.6

0.8

4.2

4.0

5.0

4.5

4.6

0.2

0.3

0.2

0.6

3.7 ns

3.9 ns

4.0 ns

5.7 ns

4.5 ns

4.2 ns

Bn to An

disable time OE to An

OE to Bn

4.0

9.3

enable time OE to An

OE to Bn

4.5

13.6

V_CC(A)= 3.0 V to 3.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.4

0.8

0.2

2.0

0.5

1.5

9.3

5.7

0.6

0.5

0.2

1.5

0.5

1.0

6.5

4.3

4.5

6.4

4.0

6.7

0.5

0.3

0.2

0.7

0.5

1.0

5.3

4.0

4.5

6.1

4.0

5.9

0.3

0.2

0.5

0.7

3.9

3.7

4.5

4.8

4.0

4.4

0.2

0.5

3.5 ns

4.5 ns

5.6 ns

4.0 ns

Bn to An

disable time OE to An

OE to Bn

4.5

9.0

enable time OE to An

OE to Bn

4.0

13.4

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

12 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Table 14. Dynamic characteristics for temperature range −40 °C to +125 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7

Symbol Parameter

Conditions

V_CC(B)

Unit

1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

V_CC(A)= 1.1 V to 1.3 V

t_pd

t_dis

t_en

propagation An to Bn

2.0

12.1

11.5

12.8

15.6

17.3

1.3

1.5

2.0

9.0

11.4

11.5

9.9

1.2

1.5

2.0

1.0

2.0

8.0

11.2

11.5

9.2

1.0

1.4

2.0

0.7

2.0

1.0

6.8

10.9

11.5

8.1

0.8

1.4

2.0

1.0

2.0

1.0

6.6 ns

10.7 ns

11.5 ns

9.2 ns

15.6 ns

8.6 ns

delay

Bn to An

disable time OE to An

OE to Bn

enable time OE to An

OE to Bn

15.6

12.7

15.6

10.9

15.6

9.0

V_CC(A)= 1.4 V to 1.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.5

1.3

1.0

2.0

1.0

2.0

11.4

9.0

1.0

1.5

1.0

1.4

8.2

6.9

8.7

9.1

1.0

0.9

1.0

0.9

1.0

1.3

6.9

8.0

6.9

8.3

8.7

8.9

0.5

0.8

1.0

0.4

1.0

1.1

5.6

7.6

6.9

7.2

8.7

7.4

0.5

0.6

1.0

0.4

1.0

1.1

5.0 ns

7.5 ns

6.9 ns

7.1 ns

8.7 ns

6.5 ns

Bn to An

disable time OE to An

OE to Bn

6.9

11.8

8.7

enable time OE to An

OE to Bn

16.6

V_CC(A)= 1.65 V to 1.95 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.5

1.2

0.5

2.0

1.0

1.5

11.2

8.0

0.9

1.0

0.5

1.5

1.0

1.2

8.0

6.9

6.6

8.1

7.8

8.3

0.8

0.5

0.8

1.0

1.2

6.6

8.0

7.8

8.0

0.5

0.2

1.0

0.8

5.2

6.4

6.6

6.7

7.8

6.3

0.3

0.5

0.2

1.0

0.6

4.6 ns

6.1 ns

6.6 ns

6.8 ns

7.8 ns

5.8 ns

Bn to An

disable time OE to An

OE to Bn

6.6

11.4

7.8

enable time OE to An

OE to Bn

16.0

V_CC(A)= 2.3 V to 2.7 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.4

1.0

0.2

2.0

0.6

1.5

10.9

6.8

0.8

0.5

0.2

1.5

0.6

1.0

7.6

5.6

4.6

7.8

5.2

7.9

0.5

0.2

0.7

0.6

1.0

6.4

5.2

4.6

7.3

5.2

6.9

0.4

0.2

0.6

0.8

4.9

4.6

5.8

5.2

5.3

0.2

0.3

0.2

0.6

4.3 ns

4.5 ns

4.6 ns

6.6 ns

5.2 ns

4.9 ns

Bn to An

disable time OE to An

OE to Bn

4.6

10.7

5.2

enable time OE to An

OE to Bn

15.7

V_CC(A)= 3.0 V to 3.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

1.4

0.8

0.2

2.0

0.5

1.5

10.7

6.6

0.6

0.5

0.2

1.5

0.5

1.0

7.5

5.0

5.2

7.4

4.6

7.8

0.5

0.3

0.2

0.7

0.5

1.0

6.1

4.6

5.2

7.1

4.6

6.8

0.3

0.2

0.5

0.7

4.5

4.3

5.2

5.6

4.6

5.1

0.2

0.5

4.1 ns

5.2 ns

6.5 ns

4.6 ns

Bn to An

disable time OE to An

OE to Bn

5.2

10.4

4.6

enable time OE to An

OE to Bn

15.5

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

13 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

12. Waveforms

V

I

V

M

An, Bn input

GND

t

PLH

PHL

V

OH

V

Bn, An output

M

V

OL

001aao074

Measurement points are given in Table 15.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 6. The data input (An, Bn) to output (Bn, An) propagation delay times

V

I

V

OE input

M

GND

t

PLZ

PZL

V

CCO

output

LOW-to-OFF

OFF-to-LOW

V

M

V

OL

t

PZH

PHZ

V

OH

V

Y

output

V

HIGH-to-OFF

OFF-to-HIGH

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aao075

Measurement points are given in Table 15.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 7. Enable and disable times

Table 15. Measurement points

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

Input^[1]

Output^[2]

V_M

V_X

V_Y

0.5V_CCI

0.5V_CCO

V_OL+ 0.1 V

V_OH− 0.1 V

V_OH− 0.15 V

V_OH− 0.3 V

V_OL+ 0.15 V

V_OL+ 0.3 V

[1] V_CCIis the supply voltage associated with the data input port.

[2] V_CCOis the supply voltage associated with the output port.

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

14 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

r

t

f

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

C

R

L

T

L

001aae331

Test data is given in Table 16.

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance.

V_EXT= External voltage for measuring switching times.

Fig 8. Test circuit for measuring switching times

Table 16. Test data

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

Input

V_I^[1]

Load

C_L

V_EXT

[3]

Δt/ΔV^[2]

R_L

t_PLH, t_PHL

open

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

2V_CCO

V_CCI

≤ 1.0 ns/V

15 pF

2 kΩ

open

GND

2V_CCO

open

GND

2V_CCO

[1] V_CCIis the supply voltage associated with the data input port.

[2] dV/dt ≥ 1.0 V/ns

[3] V_CCOis the supply voltage associated with the output port.

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

15 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

13. Typical propagation delay characteristics

001aai476

001aai477

24

21

(1)

(2)

(3)

(4)

(5)

(6)

t

pd

(ns)

t

pd

(1)

(ns)

20

17

16

12

8

13

(2)

(3)

(4)

(5)

(6)

4

9

0

20

40

60

0

20

40

60

C

L

(pF)

C (pF)

L

a. Propagation delay (A to B); V_CC(A)= 0.8 V

b. Propagation delay (A to B); V_CC(B)= 0.8 V

(1) V_CC(B)= 0.8 V.

(2) V_CC(B)= 1.2 V.

(3) V_CC(B)= 1.5 V.

(4) V_CC(B)= 1.8 V.

(5) V_CC(B)= 2.5 V.

(6) V_CC(B)= 3.3 V.

(1) V_CC(A)= 0.8 V.

(2) V_CC(A)= 1.2 V.

(3) V_CC(A)= 1.5 V.

(4) V_CC(A)= 1.8 V.

(5) V_CC(A)= 2.5 V.

(6) V_CC(A)= 3.3 V.

Fig 9. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

16 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

001aai478

001aai491

7

(1)

t

PHL

PLH

(ns)

(1)

(2)

(3)

5

3

1

5

3

1

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

a. LOW to HIGH propagation delay (A to B);

V_CC(A)= 1.2 V

b. HIGH to LOW propagation delay (A to B);

V_CC(A)= 1.2 V

001aai479

001aai480

7

(1)

t

PHL

PLH

(ns)

(1)

5

3

1

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

c. LOW to HIGH propagation delay (A to B);

V_CC(A)= 1.5 V

d. HIGH to LOW propagation delay (A to B);

V_CC(A)= 1.5 V

(1) V_CC(B)= 1.2 V.

(2) V_CC(B)= 1.5 V.

(3) V_CC(B)= 1.8 V.

(4) V_CC(B)= 2.5 V.

(5) V_CC(B)= 3.3 V.

Fig 10. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

17 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

001aai481

001aai482

7

(1)

t

PHL

PLH

(ns)

(1)

5

3

1

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

a. LOW to HIGH propagation delay (A to B);

V_CC(A)= 1.8 V

b. HIGH to LOW propagation delay (A to B);

V_CC(A)= 1.8 V

001aai483

001aai486

7

t

PHL

(ns)

PLH

(1)

(ns)

(1)

5

3

1

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

c. LOW to HIGH propagation delay (A to B);

V_CC(A)= 2.5 V

d. HIGH to LOW propagation delay (A to B);

V_CC(A)= 2.5 V

(1) V_CC(B)= 1.2 V.

(2) V_CC(B)= 1.5 V.

(3) V_CC(B)= 1.8 V.

(4) V_CC(B)= 2.5 V.

(5) V_CC(B)= 3.3 V.

Fig 11. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

18 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

001aai485

001aai484

7

t

PHL

(ns)

PLH

(1)

(ns)

(1)

5

3

1

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

a. LOW to HIGH propagation delay (A to B);

V_CC(A)= 3.3 V

b. HIGH to LOW propagation delay (A to B);

V_CC(A)= 3.3 V

(1) V_CC(B)= 1.2 V.

(2) V_CC(B)= 1.5 V.

(3) V_CC(B)= 1.8 V.

(4) V_CC(B)= 2.5 V.

(5) V_CC(B)= 3.3 V.

Fig 12. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

19 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

14. Package outline

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 13. Package outline SOT403-1 (TSSOP16)

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

20 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

C

1

y

e

b

v

M

C

A

B

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig 14. Package outline SOT763-1 (DHVQFN16)

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

21 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

XQFN16: plastic, extremely thin quad flat package; no leads;

16 terminals; body 1.80 x 2.60 x 0.50 mm

SOT1161-1

X

D

B

A

E

terminal 1

index area

A

1

A

3

detail X

e

1

C

v

w

C

A

B

e

b

y

1

y

C

5

8

L

4

1

9

e

2

12

terminal 1

index area

16

13

L

1

0

1

2 mm

scale

Dimensions

(1)

Unit

A

1

A

3

b

D

E

e

1

e

2

L

1

v

w

y

1

max 0.5 0.05

mm nom

min

0.25 1.9 2.7

0.127 0.20 1.8 2.6 0.4 1.2 1.2 0.40 0.50 0.1 0.05 0.05 0.05

0.15 1.7 2.5 0.35 0.45

0.45 0.55

0.00

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1161-1_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

09-12-28

09-12-29

SOT1161-1

Fig 15. Package outline SOT1161-1 (XQFN16)

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

22 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

15. Abbreviations

Table 17. Abbreviations

Acronym

CDM

Description

Charged Device Model

Complementary Metal Oxide Semiconductor

Device Under Test

CMOS

DUT

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

16. Revision history

Table 18. Revision history

Document ID

Release date

20110503

Data sheet status

Change notice

Supersedes

74AVC4TD245 v.1

Product data sheet

-

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

23 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

17.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

24 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74AVC4TD245

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 May 2011

25 of 26

74AVC4TD245

NXP Semiconductors

4-bit dual supply translating transceiver; 3-state

19. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . 10

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Typical propagation delay characteristics . . 16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23

8

9

10

11

12

13

14

15

16

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 24

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 25

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 May 2011

Document identifier: 74AVC4TD245


型号：	74AVC4TD245GU
厂家：	NXP
描述：	AVC SERIES, 4-BIT DRIVER, TRUE OUTPUT, PQCC16, 1.80 X 2.60 MM, 0.50 MM HEIGHT, PLASTIC, SOT1161-1, XQFN-16 驱动输出元件
文件：	总26页 (文件大小：599K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AVC4TD245GU [NXP]

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