74AVCH16374DGG [NXP]
IC AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48, Bus Driver/Transceiver;
| 型号： | 74AVCH16374DGG |
| 厂家： | 
NXP |
| 描述： | IC AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AVC16374; 74AVCH16374
16-bit edge triggered D-type
flip-flop; 3-state
Objective specification
1998 Dec 11
File under Integrated Circuits, IC24
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
FEATURES
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.
• Wide supply voltage range of 1.2 V to
3.6 V
SYMBOL PARAMETER CONDITIONS
TYPICAL UNIT
• Complies with JEDEC standard
no. 8-1A/5/7
tPHL/ tPLH propagation delay VCC = 1.8 V
CP to Qn
1.9
1.4
1.2
320
400
500
5.0
ns
V
CC = 2.5 V
CC = 3.3 V
ns
• CMOS low power consumption
• Input/Output tolerant up to 3.6 V
V
ns
Fmax
maximum clock
frequency
VCC = 1.8 V(3)
CC = 2.5 V(3)
VCC = 3.3 V(3)
MHz
MHz
MHz
pF
• DCO (Dynamic Controlled Output)
Circuit dynamically changes output
impedance, resulting in noise
V
CI
input capacitance
reduction without speed degradation
CPD
power dissipation notes 1 and 2
capacitance per
• Low inductance multiple VCC and
GND pins for minimize noise and
ground bounce.
outputs enabled
22
5
pF
pF
buffer
output disabled
• All data inputs have bushold.
(only 74AVCH16374)
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
• Power off disables 74AVC16374;
74AVCH16374 outputs, permitting
Live Insertion.
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
f
C
V
o = output frequency in MHz;
L = output load capacitance in pF;
CC = supply voltage in V;
DESCRIPTION
∑ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
3. For type with bushold.
The 74AVC(H)16374 is a 16-bit edge
triggered flip-flop featuring separate D-type
inputs for each flip-flop and 3-State outputs
for bus oriented applications. Incorporates
bushold data inputs which eliminate the
need for external pull-up resistors to hold
unused inputs.
0
-50
1.8V
-100
-150
-200
-250
-300
-350
2.5V
This product is designed to have an
extremely fast propagation delay and a
minimum amount of power consumption.
3.3V
PMOS
To ensure the high-impedance output state
during power up or power down, OEn
should be tied to VCC through a pullup
resistor (Live insertion).
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
(V) OUTPUT VOLTAGE
OH
-350
-300
-250
-200
-150
-100
A Dynamic Controlled Output (DCO)
circuitry is implemented to support
termination line drive during transient. See
graphs at this page for typical curves.
3.3V
The 74AVCH16374 consist of 2 sections of
eight edge-triggered flip-flops. A clock (CP)
input and an output enable (OE) are
provided per 8-bit section
2.5V
1.8V
NMOS
-50
0
0
0.5
1.0
V
1.5
(V) OUTPUT VOLTAGE
2.0
2.5
3.0
3.5
OL
1998 Dec 11
2
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
FUNCTION TABLE
See Note 1.
INPUTS
OUTPUT
INTERNAL
FLIP-FLOPS
OPERATING MODES
OE
CP
Dn
nY
Load and read register
L
↑
L
L
L
(Hold mode)
L
↑
↑
h
I
H
L
H
Z
Load register and disable outputs
H
H
↑
h
H
Z
Note
1. H - HIGH voltage level;
h - HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L - LOW voltage level;
l - LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X- don’t care;
Z - high impedance OFF-state;
↑- LOW-to-HIGH CP transition
ORDERING AND PACKAGE INFORMATION
PACKAGES
OUTSIDE NORTH
AMERICA
NORTH
AMERICA
TEMPERATURE
RANGE
PINS
PACKAGE MATERIAL
CODE
74AVC16374DGG
74AVCH16374DGG
−40 to +85 °C
−40 to +85 °C
48
48
TSSOP
TSSOP
plastic
plastic
SOT362-1
SOT362-1
PINNING
PIN
SYMBOL
DESCRIPTION
1
1OE
Output enable input (active LOW)
3-state flip-flop outputs
Ground (0 V)
2, 3, 5, 6, 8, 9, 11 and 12
1Q0 to 1Q7
GND
4, 10, 15, 21, 28, 34, 39 and 45
7,18, 31 and 42
VCC
Positive supply voltage
3-state flip-flop outputs
Output enable input (active LOW)
Clock input
13, 14, 16, 17, 19, 20, 22 and 23
2Q0 to 2Q7
2OE
24
25
2CP
36, 35, 33, 32, 30, 29, 27 and 26
47, 46, 44, 43, 41, 40, 38 and 37
48
2D0 to 2D7
1D0 to 1D7
1CP
Data inputs
Data inputs
Clock input
1998 Dec 11
3
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
1
2
48
47
46
45
44
1CP
1OE
1
24
1Q
1D
0
0
1Q
1
GND
3
1D
1
GND
1D
2
1OE 2OE
4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1Q
5
2
3
1Q
3
6
43 1D
3
5
V
7
V
42
CC
CC
6
8
41
40
39
38
37
36
35
34
1Q
1D
4
4
5
9
8
1Q
5
GND
1D
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
1Q
6
1D
6
11
12
13
14
16
17
19
20
22
23
1Q
1D
7
7
16374
2Q
0
2D
0
2Q
2D
1
1
GND
GND
2Q
33 2D
32 2D
2
2
3
2Q
3
V
31
30
29
28
27
V
CC
CC
2Q
2D
2D
4
4
5
2Q
5
GND
GND
2Q
2D
6
6
1CP 2CP
48 25
2Q
7
2OE
26 2D
7
2CP
25
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1
1OE
1CP
1EN
C1
48
25
24
2OE
2CP
2EN
C2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
1D
1
nD0
D
Q
nQ0
5
LATCH
1
6
8
CP
9
11
12
13
14
16
17
19
20
22
23
nCP
nOE
2D
2
2D1
2D2
2D3
2D4
2D5
2D6
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2D7
2Q7
Fig.4 Logic Diagram.
Fig.3 IEEE/IEC logic symbol
1998 Dec 11
4
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
V
CC
data
To internal circuit
Input
Fig.5 Bushold circuit.
1998 Dec 11
5
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
According JEDEC Low Voltage Standards
1.65
2.3
3.0
1.2
0
1.95
2.7
3.6
3.6
3.6
3.6
VCC
V
V
V
V
V
V
V
VCC
VI
DC supply voltage (for low-voltage applications)
DC input voltage range
VO
VO
DC output voltage range; output 3-state
0
DC output voltage range; output High or Low
state
0
Tamb
tr, tf
operating ambient temperature range
input rise and fall times
in free air
VCC = 1.65 to 2.3 V
CC = 2.3 to 3.0 V
VCC = 3.0 to 3.6 V
−40
0
+85
30
°C
ns/V
ns/V
ns/V
V
0
20
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
−
MAX.
+4.6
UNIT
V
VCC
IIK
DC input diode current
DC input voltage
VI < 0
−50
mA
V
VI
for inputs; note 1
VO > VCC or VO < 0
note 1
−0.5
−
4.6
IOK
VO
DC output diode current
±50
mA
V
DC output voltage; output
High or Low state
−0.5
VCC + 0.5
VO
IO
DC output voltage; output
3-state
note 1
−0.5
4.6
V
DC output source or sink
current
VO = 0 to VCC
−
±50
mA
I
GND, ICC DC VCC or GND current
−
±100
mA
Tstg
Ptot
storage temperature range
power dissipation per package for temperature range: −40 to +125 °C
−65
+150
°C
plastic thin-medium-shrink
(TSSOP)
above +55 °C derate linearly with 8 mW/K
−
600
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Dec 11
6
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
DC CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
Tamb = −40 TO +85 °C
MIN. MAX.
TYP.(1)
VCC
0.65VCC 0.9
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
VCC (V)
1.2
VI (V)
OTHER
VIH
HIGH level input
voltage
−
−
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
1.7
2.0
−
1.2
1.5
−
−
−
VIL
LOW level input
voltage
GND
0.35VCC
0.7
0.8
−
−
0.9
1.2
1.5
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.65 to 3.6
1.65
−
−
VOH
HIGH level output
voltage
V
V
V
V
−
−
−
−
−
CC−0.20 VCC
VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = 100 µA
IO = 4 mA
CC−0.45 VCC−0.10
−
CC−0.55 VCC−0.28
−
2.3
CC−0.70 VCC−0.32
−
3.0
VOL
LOW level output
voltage
GND
0.10
0.26
0.36
0.1
0.20
0.45
0.55
0.70
2.5
1.65 to 3.6
1.65
VIH or VIL
2.3
IO = 8 mA
3.0
IO = 12 mA
II
input leakage
current per pin
1.65 to 3.6
VCC or GND
IOFF
IIHZ/IILZ
IOZ
power off leakage
current
−
−
0.1
0.1
±10
µA
µA
0
VI or
VO = 3.6
input current for
common I/O pins
12.5
1.65 to 3.6
VCC or GND
VIH or VIL
3-state output
OFF−state current
−
−
−
−
0.1
0.1
0.1
0.2
5
µA
µA
µA
µA
1.65 to 2.7
3.0 to 3.6
1.65 to 2.7
3.0 to 3.6
VO = VCC or
GND
10
20
40
ICC
quiescent supply
current
VCC or GND IO = 0
Note
1. All typical values are measured at Tamb = 25 °C.
OPTIONAL: BUSHOLD SPECIFICATION FOR 74AVCH16374 ONLY
DC CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
Tamb = −40 TO +85 °C
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
MIN.
25
TYP.(1)
MAX.
VCC (V)
VI (V)
OTHER
see note 2.
IBHL
bushold LOW sustaining
current
−
−
−
−
−
−
µA
µA
µA
1.65
2.3
0.35VCC
0.7 V
45
75
3.0
0.8 V
1998 Dec 11
7
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
T
amb = −40 TO +85 °C
TEST CONDITIONS
SYMBOL
PARAMETER
UNIT
MIN.
−25
TYP.(1)
MAX.
VCC (V)
1.65
VI (V)
OTHER
IBHH
bushold HIGH sustaining
current
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
µA
µA
µA
µA
µA
µA
µA
µA
µA
0.65VCC
1.7 V
see note 2.
−45
2.3
3.0
−75
2.0 V
IBHLO
bushold LOW overdrive
current
200
1.95
2.7
see note 2.
see note 2.
300
450
3.6
IBHHO
bushold HIGH overdrive
current
−200
−300
−450
1.95
2.7
3.6
Note
1. All typical values are measured at Tamb = 25 °C.
2. Valid for data inputs of bushold parts.
1998 Dec 11
8
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
AC CHARACTERISTICS 74AVC16374
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF.
T
amb = −40 to +85 °C
TEST CONDITIONS
SYMBOL
PARAMETER
propagation delay
UNIT
MIN. TYP.(1) MAX.
VCC (V)
WAVEFORMS
tPHL/tPLH
1.6
0.9
0.8
0.7
−
3.2
2.0(2)
1.4(2)
1.2(2)
5.5
4.0
2.5
2.2
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
nCP to nQn
see Fig.6, Fig.9
t
PZH/tPZL
3-state output enable time
nOEn to nQn
5.0
1.6
1.3
1.2
−
3.0(2)
2.1(2)
1.8(2)
5.5
4.5
4.0
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
see Fig.8, Fig.9
see Fig.8, Fig.9
see Fig.6, Fig.9
see Fig.7, Fig.9
see Fig.7, Fig.9
see Fig.6, Fig.9
t
PHZ/tPLZ
3-state output disable time
nOEn to nQn
5.0
2.2
1.1
1.2
3.3
2.0
1.6
1.4
0.5
0.3
0.2
0.1
0.5
0.3
0.2
0.1
3.5(2)
1.8(2)
1.8(2)
5.0
4.0
3.5
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
tW
nCP pulse width HIGH or LOW
Set-up time nDn to nCP
hold time nDn to nCP
−
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
−
−
−
−
tSU
−
−
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
−
−
−
−
th
−
−
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
−
−
−
−
Fmax
maximum clock pulse frequency 150
−
−
250
300
350
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
−
−
−
−
Note
1. All typical values are measured at Tamb = 25 °C.
2. Typical value is measured at VCC = 1.8 V,VCC = 2.5 V,VCC = 3.3 V.
1998 Dec 11
9
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
AC CHARACTERISTICS 74AVCH16374
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF.
T
amb = −40 to +85 °C
TEST CONDITIONS
SYMBOL
PARAMETER
propagation delay
UNIT
MIN. TYP.(1) MAX.
VCC (V)
WAVEFORMS
tPHL/tPLH
1.6
0.9
0.8
0.7
3.2
5.5
4.0
2.5
2.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
2.0(2)
1.4(2)
1.2(2)
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
nCP to nQn
see Fig.6, Fig.9
t
PZH/tPZL
3-state output enable time
nOEn to nQn
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
see Fig.8, Fig.9
see Fig.8, Fig.9
see Fig.6, Fig.9
see Fig.7, Fig.9
see Fig.7, Fig.9
see Fig.6, Fig.9
t
PHZ/tPLZ
3-state output disable time
nOEn to nQn
−
5.0
3.5(2)
1.8(2)
1.8(2)
−
5.0
4.0
3.5
−
2.2
1.1
1.2
3.3
2.0
1.6
1.4
0.5
0.3
0.2
0.1
0.5
0.3
0.2
0.1
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
tW
nCP pulse width HIGH
Set-up time nDn to nCP
hold time nDn to nCP
−
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
−
−
−
−
tSU
−
−
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
−
−
−
−
th
−
−
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
−
−
−
−
Fmax
maximum clock pulse frequency 150
−
−
250
300
350
−
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
−
−
−
−
Note
1. All typical values are measured at Tamb = 25 °C.
2. Typical value is measured at VCC = 1.8 V,VCC = 2.5 V,VCC = 3.3 V.
1998 Dec 11
10
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
AC WAVEFORMS
V
I
CP
INPUT
V
M
GND
1/f
max
t
t
SU
SU
V
i
t
t
h
h
(1)
t
CP INPUT
GND
V
M
t
V
I
Dn
INPUT
W
GND
t
PHL
PLH
(2)
V
OH
(1)
Q
OUTPUT
V
n
M
V
OH
(2)
OL
V
Qn
V
M
OUTPUT
V
OL
Fig.7 The data set-up time and hold times for the
Dn input to the CP input
Fig.6 The input (Dn) to output (Qn) propagation
delay.
V
I
OE INPUT
GND
V
M
t
t
PLZ
PZL
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
PZH
t
PHZ
V
OH
V
OUTPUT
Y
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
disabled
outputs
enabled
outputs
enabled
Fig.8 The 3-state enable and disable times.
1998 Dec 11
11
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
NOTES: VCC = 2.3 TO 2.7 V RANGE AND VCC < 2.3 V
1. VM = 0.5VCC
2. VX = VOL + 150 mV
3. VY = VOH - 150 mV
4. VI = VCC
5. VOL and VOH are typical output voltage drop that occur
with the output load.
NOTES: VCC = 3.0 TO 3.6 V RANGE
1. VM = 0.5VCC
2. VX = VOL + 300 mV
3. VY = VOH - 300 mV
4. VI = 2.7 V
TEST
PLH/tPHL Open
PLZ/tPZL 2VCC
SWITCH
VCC
VI
RLOAD
t
t
< 2.3 V
VCC
1000Ω
500Ω
2.3 - 2.7 V Vcc
5. VOL and VOH are typical output voltage drop that occur
with the output load.
tPHZ/tPZH GND
3.0 - 3.6 V 2.7 V 500Ω
Fig.9 Load circuitry for switching times.
1998 Dec 11
12
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
PACKAGE OUTLINE
1998 Dec 11
13
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Suitability of surface mount IC packages for wave and
reflow soldering methods
SOLDERING METHOD
REFLOW(1)
PACKAGE
WAVE
BGA, SQFP
not suitable
not suitable(2)
suitable
not recommended(3)(4)
not recommended(5)
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
Notes
1. All surface mount (SMD) packages are moisture
sensitive. Depending upon the moisture content, the
1998 Dec 11
14
Philips Semiconductors
Objective specification
16-bit edge triggered D-type flip-flop;
3-state
74AVC16374;
74AVCH16374
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external
package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details,
refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing
Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Dec 11
15
Philips Semiconductors – a worldwide company
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Tel. +90 212 279 2770, Fax. +90 212 282 6707
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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
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Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245112/00/01/pp16
Date of release: 1998 Dec 11
Document order number: 9397 750 04915
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