74AVCH2T45 [NXP]
Dual-bit, dual-supply voltage level translator/transceiver; 3-state; 双位双电源电压电平转换器/收发器;三态
| 型号： | 74AVCH2T45 |
| 厂家： | 
NXP |
| 描述： | Dual-bit, dual-supply voltage level translator/transceiver; 3-state |
| 文件： | 总29页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVCH2T45
Dual-bit, dual-supply voltage level translator/transceiver;
3-state
Rev. 01 — 3 July 2007
Product data sheet
1. General description
The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (nA and nB), a direction control input
(DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at
any voltage between 0.8 V and 3.6 V making the device suitable for translating between
any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR
are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows
transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
I Wide supply voltage range:
N VCC(A): 0.8 V to 3.6 V
N VCC(B): 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 500 Mbps (1.8 V to 3.3 V translation)
N 320 Mbps (< 1.8 V to 3.3 V translation)
N 320 Mbps (translate to 2.5 V or 1.8 V)
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
N 280 Mbps (translate to 1.5 V)
N 240 Mbps (translate to 1.2 V)
I Suspend mode
I Bus hold on data inputs
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I SOT765-1 and SOT833-1 package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVCH2T45DC
74AVCH2T45GT
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code
74AVCH2T45DC
74AVCH2T45GT
K45
K45
5. Functional diagram
5
DIR
DIR
1A
1B
2A
2B
2
1A
7
1B
3
2A
6
2B
V
V
CC(B)
CC(A)
V
V
CC(B)
CC(A)
001aag577
001aag578
Fig 1. Logic symbol
Fig 2. Logic diagram
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
2 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
6. Pinning information
6.1 Pinning
74AVCH2T45
V
1
2
3
4
8
7
6
5
V
CC(B)
CC(A)
1A
1B
74AVCH2T45
2A
2B
1
2
3
4
8
7
6
5
V
V
CC(B)
CC(A)
1A
1B
GND
DIR
2A
2B
GND
DIR
001aag584
Transparent top view
001aag583
Fig 3. Pin configuration SOT765-1 (VSSOP8)
Fig 4. Pin configuration SOT833-1 (XSON8)
6.2 Pin description
Table 3.
Symbol
VCC(A)
1A
Pin description
Pin
1
Description
supply voltage port A and DIR
data input or output
data input or output
ground (0 V)
2
2A
3
GND
DIR
4
5
direction control
2B
6
data input or output
data input or output
supply voltage port B
1B
7
VCC(B)
8
7. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[4]
Input
DIR[3]
Input/output[2]
nA
nB
L
nA = nB
input
Z
input
nB = nA
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] The DIR input circuit is referenced to VCC(A)
.
[4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
3 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
−0.5
−0.5
−50
−0.5
−50
−0.5
−0.5
-
Max
+4.6
+4.6
-
Unit
V
supply voltage port A
supply voltage port B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+4.6
±50
100
-
Suspend or 3-state mode
VO = 0 V to VCC
ICC(A) or ICC(B)
V
IO
output current
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
250
[4]
Tamb = −40 °C to +125 °C
[1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
supply voltage port A
supply voltage port B
input voltage
3.6
V
3.6
V
[1]
VO
output voltage
Active mode
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
−40
-
+125
5
°C
ns/V
∆t/∆V
input transition rise and fall rate
VCCI =0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
4 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device
must be held at VCCI or GND to ensure proper device operation.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VOH
HIGH-level output
VI = VIH
voltage
IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V
VI = VIL
-
0.69
0.07
-
-
V
VOL
LOW-level output
voltage
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
-
V
II
input leakage
current
DIR input; VI = GND to VCC(A)
;
±0.025 ±0.25
µA
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
IBHH
IBHLO
IBHHO
IOZ
bus hold LOW
current
VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
-
-
-
-
-
-
-
-
-
26
-
µA
µA
µA
µA
µA
µA
µA
pF
pF
bus hold HIGH
current
VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
−24
28
-
[1]
[1]
[2]
bus hold LOW
overdrive current
VI = GND to VCCI
;
-
V
CC(A) = VCC(B) = 1.2 V
bus hold HIGH
overdrive current
VI = GND to VCCI
;
−26
±0.5
±0.1
±0.1
1.0
-
V
CC(A) = VCC(B) = 1.2 V
A or B port; VO = GND or VCCO
CC(A) = VCC(B) = 0.8 V to 3.6 V
A port; VI or VO = 0 V to 3.6 V;
CC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
DIR input; VI = GND or 3.3 V;
CC(A) = VCC(B) = 3.3 V
OFF-state output
current
;
±2.5
±1.0
±1.0
-
V
IOFF
power-off leakage
current
V
V
CI
input capacitance
V
[2]
[1]
CI/O
input/output
capacitance
A and B port; suspend mode;
VO = VCCO or GND;
4.0
-
V
CC(A) = VCC(B) = 3.3 V
T
amb = −40 °C to +85 °C
VIH
HIGH-level input
voltage
data input
VCCI = 0.8 V
0.70 × VCCI
0.65 × VCCI
1.6
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
2.0
[1]
VCCI = 0.8 V
0.70 × VCC(A)
0.65 × VCC(A)
1.6
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
2.0
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
5 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device
must be held at VCCI or GND to ensure proper device operation.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
VIL
LOW-level input
data input
voltage
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCCI
0.35 × VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.9
[1]
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCC(A)
0.35 × VCC(A)
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VI = VIH
0.9
VOH
HIGH-level output
voltage
[2]
IO = −100 µA;
VCCO − 0.1
-
-
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = −3 mA; VCC(A) = VCC(B) = 1.1 V
IO = −6 mA; VCC(A) = VCC(B) = 1.4 V
IO = −8 mA; VCC(A) = VCC(B) = 1.65 V
IO = −9 mA; VCC(A) = VCC(B) = 2.3 V
IO = −12 mA; VCC(A) = VCC(B) = 3.0 V
0.85
1.05
1.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.75
2.3
VOL
LOW-level output
voltage
VI = VIL
IO = 100 µA;
CC(A) = VCC(B) = 0.8 V to 3.6 V
-
-
0.1
V
V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
IO = 8 mA; VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
IO = 12 mA; VCC(A) = VCC(B) = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
0.25
0.35
0.45
0.55
0.7
V
V
V
V
V
II
input leakage
current
DIR input; VI = GND to VCC(A)
;
±1.0
µA
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW
current
VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V
VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V
VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V
VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V
VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V
VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V
VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V
VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
µA
µA
25
45
100
−15
−25
−45
−100
IBHH
bus hold HIGH
current
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
6 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device
must be held at VCCI or GND to ensure proper device operation.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
[1]
[2]
IBHLO
bus hold LOW
overdrive current
VI = GND to VCCI
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
VI = GND to VCCI
125
200
300
500
-
-
-
-
-
-
-
-
µA
µA
µA
µA
IBHHO
bus hold HIGH
overdrive current
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port; VO = GND or VCCO
−125
−200
−300
−500
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
-
-
-
IOZ
OFF-state output
current
;
±5.0
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
A port; VI or VO = 0 V to 3.6 V;
CC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
IOFF
power-off leakage
current
-
-
-
-
±5.0
±5.0
µA
µA
V
V
[1]
[1]
ICC
supply current
A port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
8.0
8.0
-
µA
µA
µA
-
-
VCC(A) = 0 V; VCC(B) = 3.6 V
−2
0
B port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
8
µA
µA
µA
µA
−2
-
0
-
-
VCC(A) = 0 V; VCC(B) = 3.6 V
8
[1]
[1]
A plus B port (ICC(A) + ICC(B)); IO = 0 A;
-
-
16
VI = GND or VCCI
;
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
T
amb = −40 °C to +125 °C
VIH
HIGH-level input
voltage
data input
VCCI = 0.8 V
0.70 × VCCI
0.65 × VCCI
1.6
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
2.0
[1]
VCCI = 0.8 V
0.70 × VCC(A)
0.65 × VCC(A)
1.6
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
2.0
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
7 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device
must be held at VCCI or GND to ensure proper device operation.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
VIL
LOW-level input
data input
voltage
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCCI
0.35 × VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.9
[1]
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCC(A)
0.35 × VCC(A)
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VI = VIH
0.9
VOH
HIGH-level output
voltage
[2]
IO = −100 µA;
VCCO − 0.1
-
-
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = −3 mA; VCC(A) = VCC(B) = 1.1 V
IO = −6 mA; VCC(A) = VCC(B) = 1.4 V
IO = −8 mA; VCC(A) = VCC(B) = 1.65 V
IO = −9 mA; VCC(A) = VCC(B) = 2.3 V
IO = −12 mA; VCC(A) = VCC(B) = 3.0 V
0.85
1.05
1.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.75
2.3
VOL
LOW-level output
voltage
VI = VIL
IO = 100 µA;
CC(A) = VCC(B) = 0.8 V to 3.6 V
-
-
0.1
V
V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
IO = 8 mA; VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
IO = 12 mA; VCC(A) = VCC(B) = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
0.25
0.35
0.45
0.55
0.7
V
V
V
V
V
II
input leakage
current
DIR input; VI = GND to VCC(A)
;
±1.5
µA
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW
current
VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V
VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V
VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V
VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V
VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V
VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V
VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V
VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
µA
µA
25
45
90
IBHH
bus hold HIGH
current
−15
−25
−45
−100
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
8 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device
must be held at VCCI or GND to ensure proper device operation.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
[1]
[2]
IBHLO
bus hold LOW
overdrive current
VI = GND to VCCI
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
VI = GND to VCCI
125
200
300
500
-
-
-
-
-
-
-
-
µA
µA
µA
µA
IBHHO
bus hold HIGH
overdrive current
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port; VO = GND or VCCO
−125
−200
−300
−500
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
-
-
-
IOZ
OFF-state output
current
;
±7.5
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
A port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
IOFF
power-off leakage
current
-
-
-
-
±35
±35
µA
µA
V
V
[1]
[1]
[1]
ICC
supply current
A port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
11.5
11.5
-
µA
µA
µA
-
-
VCC(A) = 0 V; VCC(B) = 3.6 V
−8
0
B port; VI = GND or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
11.5
-
µA
µA
µA
µA
−8
-
0
-
VCC(A) = 0 V; VCC(B) = 3.6 V
11.5
23
A plus B port (ICC(A) + ICC(B)); IO = 0 A;
-
-
VI = GND or VCCI
;
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
9 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
VCC(A) = 0.8 V
[2]
[2]
[3]
[3]
tpd
propagation delay A to B; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
15.8
8.4
8.0
8.0
8.7
9.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
B to A; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
15.8
12.7
12.4
12.2
12.0
11.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
tdis
disable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
-
12.2
12.2
12.2
12.2
12.2
12.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
-
11.7
7.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
7.6
8.2
8.7
10.2
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
10 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[4][5]
ten
enable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
-
27.5
20.6
20.0
20.4
20.7
22.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
[4][5]
-
-
-
-
-
-
28.0
20.6
20.2
20.2
20.9
21.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
VCC(A) = 1.1 V to 1.3 V
[2]
tpd
propagation delay A to B; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
12.7
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
B to A; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
1.0
0.7
0.6
0.5
0.5
9.0
6.8
6.1
5.7
6.1
9.9
7.5
6.8
6.3
6.8
[2]
-
-
-
-
-
-
8.4
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
1.0
0.8
0.7
0.6
0.5
9.0
8.0
7.7
7.2
7.1
9.9
8.8
8.5
8.0
7.9
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
11 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[3]
[3]
tdis
disable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
4.9
-
-
-
-
-
-
ns
ns
VCC(B) = 1.1 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
2.2
8.8
9.7
-
-
-
-
-
-
9.2
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
2.2
1.8
2.0
1.7
2.4
8.4
6.7
6.9
6.2
7.2
9.2
7.4
7.6
6.9
8.0
[4][5]
ten
enable time
-
-
-
-
-
-
17.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
17.4
14.7
14.6
13.4
14.3
19.1
16.2
16.1
14.9
15.9
[4][5]
-
-
-
-
-
-
17.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
17.8
15.6
14.9
14.5
14.9
19.6
17.2
16.5
16.0
16.5
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
12 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
VCC(A) = 1.4 V to 1.6 V
[2]
tpd
propagation delay A to B; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
12.4
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
B to A; see Figure 5
-
-
-
-
-
1.0
0.7
0.6
0.5
0.5
8.0
5.4
4.6
3.7
3.5
8.8
6.0
5.1
4.1
3.9
[2]
VCC(B) = 0.8 V
-
-
-
-
-
-
8.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
1.0
0.8
0.7
0.6
0.5
6.8
5.4
5.1
4.7
4.5
7.5
6.0
5.7
5.2
5.0
[3]
[3]
tdis
disable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
3.8
-
-
-
-
-
-
ns
ns
VCC(B) = 1.1 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
1.6
6.3
7.0
-
-
-
-
-
-
9.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
2.0
1.8
1.6
1.2
1.7
7.6
5.9
6.0
4.8
5.5
8.3
6.5
6.6
5.3
6.1
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
13 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[4][5]
ten
enable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
-
17.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
14.4
11.3
11.1
9.5
15.8
12.5
12.3
10.5
11.1
10.0
[4][5]
-
-
-
-
-
-
16.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
14.3
11.7
10.9
10.0
9.8
15.8
13.0
12.7
11.1
10.9
VCC(A) = 1.65 V to 1.95 V
[2]
tpd
propagation delay A to B; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
12.2
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
B to A; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
1.0
0.6
0.5
0.5
0.5
7.7
5.1
4.3
3.4
3.1
8.5
5.7
4.8
3.8
3.5
[2]
-
-
-
-
-
-
8.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
1.0
0.7
0.5
0.5
0.5
6.1
4.6
4.4
3.9
3.7
6.8
5.1
4.9
4.3
4.1
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
14 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[3]
[3]
tdis
disable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
3.7
-
-
-
-
-
-
ns
ns
VCC(B) = 1.1 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
1.6
5.5
6.1
-
-
-
-
-
-
8.8
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
1.8
1.8
1.4
1.0
1.5
7.8
5.7
5.8
4.5
5.2
8.6
6.3
6.4
5.0
5.8
[4][5]
ten
enable time
-
-
-
-
-
-
16.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
13.9
10.3
10.2
8.4
15.4
11.4
11.3
9.3
8.9
9.9
[4][5]
-
-
-
-
-
-
15.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
13.2
10.6
9.8
14.6
11.8
10.9
9.9
8.9
8.6
9.6
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
15 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
VCC(A) = 2.3 V to 2.7 V
[2]
tpd
propagation delay A to B; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
12.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
B to A; see Figure 5
-
-
-
-
-
1.0
0.5
0.5
0.5
0.5
7.2
4.7
3.9
3.0
2.6
8.0
5.2
4.3
3.3
2.9
[2]
VCC(B) = 0.8 V
-
-
-
-
-
-
8.7
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
1.0
0.6
0.5
0.5
0.5
5.7
3.8
3.4
3.0
2.8
6.3
4.2
3.8
3.3
3.1
[3]
[3]
tdis
disable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
2.8
-
-
-
-
-
-
ns
ns
VCC(B) = 1.1 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
1.5
4.2
4.7
-
-
-
-
-
-
8.7
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
1.7
2.0
1.5
0.6
1.1
7.3
5.2
5.1
4.2
4.8
8.0
5.8
5.7
4.7
5.3
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
16 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[4][5]
ten
enable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
-
17.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
13.0
9.0
8.5
7.2
7.6
14.3
10.0
9.5
8.0
8.4
[4][5]
-
-
-
-
-
-
14.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
11.4
8.9
8.1
7.2
6.8
12.7
9.9
9.0
8.0
7.6
VCC(A) = 3.0 V to 3.6 V
[2]
tpd
propagation delay A to B; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
-
11.8
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
B to A; see Figure 5
VCC(B) = 0.8 V
-
-
-
-
-
1.0
0.5
0.5
0.5
0.5
7.1
4.5
3.7
2.8
2.4
7.9
5.0
4.1
3.1
2.7
[2]
-
-
-
-
-
-
9.5
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
1.0
0.6
0.5
0.5
0.5
6.1
3.6
3.1
2.6
2.4
6.8
4.0
3.5
2.9
2.7
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
17 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[3]
[3]
tdis
disable time
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
3.4
-
-
-
-
-
-
ns
ns
VCC(B) = 1.1 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
1.5
4.7
5.2
-
-
-
-
-
-
8.6
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to A; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
1.7
0.7
0.6
0.7
1.7
7.2
5.5
5.5
4.1
4.7
7.9
6.1
6.1
4.6
5.2
[4][5]
ten
enable time
-
-
-
-
-
-
18.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
DIR to B; see Figure 6
VCC(B) = 0.8 V
-
-
-
-
-
13.3
9.1
8.6
6.7
7.1
14.7
10.1
9.6
7.5
7.9
[4][5]
-
-
-
-
-
-
15.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC(B) = 1.1 V to 1.3 V
VCC(B) = 1.4 V to 1.6 V
VCC(B) = 1.65 V to 1.95 V
VCC(B) = 2.3 V to 2.7 V
VCC(B) = 3.0 V to 3.6 V
-
-
-
-
-
11.8
9.2
8.4
7.5
7.1
13.1
10.2
9.3
8.3
7.9
74AVCH2T45_1
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Product data sheet
Rev. 01 — 3 July 2007
18 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
Power dissipation capacitance
CPD power dissipation A port: (direction A to B);
[6][7]
capacitance
B port: (direction B to A)
VCC(A) = VCC(B) = 0.8 V
VCC(A) = VCC(B) = 1.2 V
VCC(A) = VCC(B) = 1.5 V
VCC(A) = VCC(B) = 1.8 V
VCC(A) = VCC(B) = 2.5 V
VCC(A) = VCC(B) = 3.3 V
-
-
-
-
-
-
1
2
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
[6][7]
A port: (direction B to A);
B port: (direction A to B)
VCC(A) = VCC(B) = 0.8V
VCC(A) = VCC(B) = 1.2 V
VCC(A) = VCC(B) = 1.5 V
VCC(A) = VCC(B) = 1.8 V
VCC(A) = VCC(B) = 2.5 V
VCC(A) = VCC(B) = 3.3 V
-
-
-
-
-
-
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
11
11
12
14
17
[1] All typical values are measured at nominal VCC(A) and VCC(B)
[2] tpd is the same as tPLH and tPHL
[3] tdis is the same as tPLZ and tPHZ
[4] ten is the same as tPZL and tPZH
.
.
.
.
[5] The enable time is a calculated value using the formula shown in Section 13.4 “Enable times”.
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[7] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
19 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
12. Waveforms
V
I
V
M
A, B input
GND
t
t
PLH
PHL
V
OH
B, A output
V
M
001aae967
V
OL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The data input (A, B) to output (B, A) propagation delay times
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
Table 9.
Measurement points
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
Output[2]
VM
VM
VX
VOL + 0.1 V
VY
0.5 × VCCI
0.5 × VCCI
0.5 × VCCI
0.5 × VCCO
0.5 × VCCO
0.5 × VCCO
V
V
V
OH − 0.1 V
VOL + 0.15 V
VOL + 0.3 V
OH − 0.15 V
OH − 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
20 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 10.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[3]
∆t/∆V[2]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCCO
2 × VCCO
2 × VCCO
VCCI
VCCI
VCCI
≤ 1.0 ns/V
≤ 1.0 ns/V
≤ 1.0 ns/V
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
open
GND
open
GND
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
21 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 8 is an example of the 74AVCH2T45 being used in an
unidirectional logic level-shifting application.
V
V
CC2
CC1
74AVCH2T45
V
V
CC(B)
V
V
V
V
CC(A)
1A
CC1
CC1
CC2
CC2
1
2
3
4
8
7
6
5
1B
2A
2B
GND
DIR
system-1
system-2
001aag585
Fig 8. Unidirectional logic level-shifting application
Table 11. Unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
1A
Function
VCC1
OUT1
OUT2
GND
DIR
Description
supply voltage of system-1 (0.8 V to 3.6 V)
output level depends on VCC1 voltage
output level depends on VCC1 voltage
device GND
2
3
2A
4
GND
DIR
5
the GND (LOW level) determines B port to A port direction
input threshold value depends on VCC2 voltage
input threshold value depends on VCC2 voltage
supply voltage of system-2 (0.8 V to 3.6 V)
6
2B
IN2
7
1B
IN1
8
VCC(B)
VCC2
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
22 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 9 shows the 74AVCH2T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable (OE) pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
V
V
V
V
CC2
CC1
CC1
CC2
74AVCH2T45
V
V
CC(B)
CC(A)
1A
I/O-1
I/O-2
1
2
3
4
8
7
6
5
1B
2A
2B
GND
DIR
DIR CTRL
DIR CTRL
system-1
system-2
001aag586
Fig 9. Bidirectional logic level-shifting application
Table 12 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 12. Bidirectional logic level-shifting application[1]
State DIR CTRL I/O-1
I/O-2
input
Z
Description
1
2
H
H
output
Z
system-1 data to system-2
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold.
input
output
system-2 data to system-1
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
74AVCH2T45_1
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Product data sheet
Rev. 01 — 3 July 2007
23 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 13. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
0.8 V
0.1
0.1
0.1
0.1
0.1
0.7
2.3
1.2 V
0.1
0.1
0.1
0.1
0.1
0.3
1.4
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.9
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.5
2.5 V
0.1
0.7
0.3
0.1
0.1
0.1
0.1
3.3 V
0.1
2.3
1.4
0.9
0.5
0.1
0.1
0 V
µA
µA
µA
µA
µA
µA
µA
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
13.4 Enable times
Calculate the enable times for the 74AVCH2T45 using the following formulas:
• ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA)
• ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB)
In a bidirectional application, these enable times provide the maximum delay from the time
the DIR bit is switched until an output is expected. For example, if the 74AVCH2T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presenting it with an input. After the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
24 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
14. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
25 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-22
04-11-09
SOT833-1
- - -
MO-252
Fig 11. Package outline SOT833-1 (XSON8)
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
26 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
15. Abbreviations
Table 14. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
16. Revision history
Table 15. Revision history
Document ID
Release date
20070703
Data sheet status
Change notice
Supersedes
74AVCH2T45_1
Product data sheet
-
-
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
27 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
17.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74AVCH2T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 3 July 2007
28 of 29
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
9
10
11
12
13
Application information. . . . . . . . . . . . . . . . . . 22
Unidirectional logic level-shifting application. . 22
Bidirectional logic level-shifting application. . . 23
Power-up considerations . . . . . . . . . . . . . . . . 24
Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 24
13.1
13.2
13.3
13.4
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 July 2007
Document identifier: 74AVCH2T45_1
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