74F113 [NXP]
Dual J-K negative edge-triggered flip-flops without reset; 双JK负边沿触发触发器复位不
| 型号： | 74F113 |
| 厂家： | 
NXP |
| 描述： | Dual J-K negative edge-triggered flip-flops without reset |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F113
Dual J-K negative edge-triggered
flip-flops without reset
Product specification
IC15 Data Handbook
1991 Feb 14
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops
without reset
74F113
FEATURE
PIN CONFIGURATION
• Industrial temperature range available (–40°C to +85°C)
CP0
K0
1
2
3
4
5
14
V
CC
13 CP1
12 K1
11 J1
DESCRIPTION
J0
The 74F113, dual negative edge-triggered JK-type flip-flop, features
individual J, K, clock (CP), set (SD) inputs, true and complementary
outputs. The asynchronous SD input, when low, forces the outputs
to the steady state levels as shown in the function table regardless
of the level at the other inputs.
SD0
Q0
10 SD1
Q0
6
7
9
8
Q1
Q1
GND
A high level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CP is high and flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the high-to-low
transition of the CP.
SF00140
TYPE
TYPICAL f
TYPICAL SUPPLY CURRENT (TOTAL)
max
74F113
100MHz
15mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
= 5V ±10%,
DESCRIPTION
PKG. DWG. #
V
CC
= 5V ±10%,
V
CC
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
14-pin plastic DIP
14-pin plastic SO
N74F113N
I74F113N
SOT27–1
N74F113D
I74F113D
SOT108–1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
J0, J1
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
LOAD VALUE HIGH/LOW
20µA/0.6mA
J inputs
K inputs
K0, K1
1.0/1.0
20µA/0.6mA
CP0, CP1
SD0, SD1
Q0, Q1, Q0, Q1
Clock inputs (active falling edge)
Set inputs (active low)
Data outputs
1.0/4.0
20µA/2.4mA
1.0/5.0
20µA/3.0mA
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
3
11
J1
2
12
3
1
2
4
1J
C1
5
6
J0
K0
K1
1K
1S
1
4
CP0
SD0
13
10
CP1
SD1
11
13
12
10
2J
9
8
Q1 Q1
Q0 Q0
C2
2K
2S
V
= Pin 14
9
8
5
6
CC
GND = Pin 7
SF00141
SF00142
2
1996 Mar 14
853–0339 16575
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops
without reset
74F113
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
L
CP
J
X
h
h
l
K
X
h
l
Q
H
q
Q
L
6, 8
5, 9
Q
Q
J
X
↓
↓
↓
↓
Asynchronous set
Toggle
H
q
4, 10
SD
2, 12
K
H
H
L
L
Load ”1” (set)
Load ”0” (reset)
Hold ’no change”
3, 11
H
h
l
H
q
1, 13
H
l
q
V
= Pin 14
CC
GND = Pin 7
CP
SF00143
NOTES:
H
h
=
=
High-voltage level
High-voltage level one setup time prior to high-to-low
clock transition
L
l
=
=
Low-voltage level
Low-voltage level one setup time prior to high-to-low clock
transition
q
=
Lower case indicate the state of the referenced output
prior to the high-to-low clock transition
Don’t care
X
↓
=
=
high-to-low clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
–0.5 to V
40
CC
I
mA
°C
°C
°C
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
amb
Operating free-air temperature range
Storage temperature range
T
stg
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
°C
IK
High-level output current
Low-level output current
OH
OL
20
Commercial range
Industrial range
0
+70
+85
T
amb
Operating free-air temperature range
–40
3
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops
without reset
74F113
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.5
TYP
MAX
V
V
V
±10%V
±5%V
CC
V
V
= MIN, V = MAX,
IL
CC
V
OH
High-level output voltage
I
= MAX
= MAX
OH
= MIN
IH
2.7
3.4
CC
0.30
0.30
0.50
±10%V
CC
CC
V
V
= MIN, V = MAX,
IL
CC
IH
V
V
Low-level output voltage
I
OL
OL
= MIN
0.50
–1.2
100
20
V
±5%V
Input clamp voltage
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73
V
IK
I
I
I
Input current at maximum input voltage
High-level input current
Jn, Kn
= MAX, V = 7.0V
µA
µA
mA
mA
mA
mA
mA
I
I
= MAX, V = 2.7V
IH
IL
I
–0.6
–2.4
–3.0
–150
21
I
Low-level input current
CPn
SDn
V
CC
= MAX, V = 0.5V
I
3
I
I
Short-circuit output current
V
V
= MAX
= MAX
-60
OS
CC
4
Supply current (total)
15
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
V
= +5.0V ± 10%
CC
CC
CC
T
amb
T
amb
T = –40°C to +85°C
amb
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
L
L
L
MIN TYP MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
85
100
80
80
ns
ns
max
t
t
Propagation delay
CPn to Qn or Qn
2.0
2.0
4.0
4.0
6.0
6.0
2.0
2.0
7.0
7.0
2.0
2.0
7.5
7.0
PLH
PHL
t
t
Propagation delay
SDn, to Qn or Qn
2.0
2.0
4.5
4.5
6.5
6.5
2.0
2.0
7.5
7.5
2.0
2.0
8.0
7.5
PLH
PHL
Waveform 2
ns
AC SETUP REQUIREMENTS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
V
= +5.0V ± 10%
CC
CC
CC
T
amb
T
amb
T = –40°C to +85°C
amb
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
L
L
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Jn, Kn to CPn
4.0
3.5
5.0
4.0
5.0
4.5
su
su
Waveform 1
Waveform 1
ns
ns
t (H)
Hold time, high or low
Jn, Kn to CPn
0.0
0.0
0.0
0.0
0.0
0.0
h
t (L)
h
t
t
(H)
(L)
CP pulse width,
high or low
4.5
4.5
5.0
5.0
5.0
5.0
w
w
Waveform 1
Waveform 2
Waveform 2
ns
ns
ns
t
t
(L)
SDn pulse width, low
4.5
5.0
5.0
w
Recovery time
SDn to CPn
4.5
5.0
5.0
rec
4
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops
without reset
74F113
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
Jn
Kn
Jn, Kn
V
V
V
V
M
M
M
M
Jn
Kn
t
(H)
t
(L)
t (L) = 0
h
t
(H) = 0
su
su
h
1/f
max
t
(L)
w
CPn
Qn
V
V
M
V
t
M
M
t
PLH
t
(H)
w
PHL
V
V
M
M
M
t
t
PHL
PLH
V
V
M
Qn
SF00144
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Width,
and Maximum Clock Frequency
Jn, Kn
t
(L)
w
V
SDn
CPn
Qn
M
t
V
M
rec
V
M
t
PLH
V
V
M
t
PHL
Qn
M
SF00145
Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock
5
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops
without reset
74F113
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
6
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
7
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
8
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
NOTES
9
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05072
Document order number:
Philips
Semiconductors
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