74F169 [NXP]
4-bit up/down binary synchronous counter; 4位向上/向下二进制同步计数器
| 型号： | 74F169 |
| 厂家： | 
NXP |
| 描述： | 4-bit up/down binary synchronous counter |
| 文件： | 总12页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F168*, 74F169
4-bit up/down binary synchronous counter
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification
IC15 Data Handbook
1996 Jan 05
Philips
Semiconductors
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
FEATURES
PIN CONFIGURATION
• Synchronous counting and loading
U/D
CP
1
2
3
4
5
16
V
CC
• Up/Down counting
15 TC
• Modulo 16 binary counter
14
13
12
11
D
0
Q
Q
Q
Q
0
1
2
3
• Two Count Enable inputs for n-bit cascading
• Positive edge-triggered clock
• Built-in carry look-ahead capability
• Presettable for programmable operation
D
1
D
2
6
7
8
D
3
CEP
GND
10 CET
PE
9
DESCRIPTION
SF00766
The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down
counter featuring an internal carry look-ahead for applications in
high-speed counting designs. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when instructed by the Count
Enable inputs and internal gating. This mode of operation eliminates
the output spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the flip-flops
on the Low-to-High transition of the clock.
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F169
115MHz
35mA
ORDERING INFORMATION
The counter is fully programmable; that is, the outputs may be
preset to either level.
ORDER CODE
PKG
DWG #
COMMERCIAL RANGE
DESCRIPTION
V
amb
= 5V ±10%,
= 0°C to +70°C
Presetting is synchronous with the clock and takes place regardless
of the levels of the Count Enable inputs. A Low level on the Parallel
Enable (PE) input disables the counter and causes the data at the
CC
T
16-pin plastic DIP
16-pin plastic SO
N74F169N
SOT38-4
D input to be loaded into the counter on the next Low-to-High
n
N74F169D
SOT109-1
transition of the clock.
The direction of counting is controlled by the Up/Down (U/D) input; a
High will cause the count to increase, a Low will cause the count to
decrease.
The carry look-ahead circuitry provides for n-bit synchronous
applications without additional gating. Instrumental in accomplishing
this function are two Count Enable inputs (CET, CEP) and a
Terminal Count (TC) output. Both Count Enable inputs must be Low
to count. The CET input is fed forward to enable the TC output. The
TC output thus enabled will produce a Low output pulse with a
duration approximately equal to the High level portion of the Q
output. The Low level TC pulse is used to enable successive
cascaded stages.
0
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
PINS
DESCRIPTION
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
D - D
0
Parallel data inputs
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
3
CEP
CET
CP
Count Enable parallel input (active Low)
Count Enable Trickle input (active Low)
Clock input (active rising edge)
Parallel Enable input (active Low)
Up/Down count control input
PE
U/D
Q - Q
0
Flip-flop outputs
3
TC
Terminal count output (active Low)
50/33
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
2
1996 Jan 05
853–0350 16190
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16
3
4
5
6
9
M1 [LOAD]
M2 [COUNT]
D
D
D
D
3
1
0
1
2
9
PE
M3 [UP]
M4 [DOWN]
10
1
2
7
U/D
CP
15
3, 5 CT=15
4, 5 CT=0
G5
G6
TC
15
7
2
CEP
CET
2, 3, 5, 6+/C7
2, 4, 5, 6–
10
Q
Q
Q
Q
3
0
1
2
3
14
13
12
1, 7D
[1]
[2]
[4]
[8]
14
13
12
11
4
5
6
V
= Pin 16
11
CC
GND = Pin 8
SF00786
SF00787
FUNCTIONAL DESCRIPTION
The 74F169 uses edge-triggered J-K-type flip-flops and have no
constraints on changing the control or data input signals in either
state of the clock. The only requirement is that the various inputs
attain the desired state at least a setup time before the rising edge
of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the
other operations, as indicated in the Mode Select Table. When PE is
when a counter reaches zero in the Count Down mode or reaches
15 in the Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. Since the TC signal is
derived by decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a clock
signal is not recommended (see logic equations below).
1) Count Enable = CEP CET PE
Low, the data on the D - D inputs enter the flip-flops on the next
0
3
rising edge of the Clock. In order for counting to occur, both CEP
and CET must be Low and PE must be High; the U/D input
determines the direction of counting. The Terminal Count (TC)
output is normally High and goes Low, provided that CET is Low,
2) Up: TC = Q Q (U/D) CET
0
3
3) Down: TC = Q Q Q Q (U/D) CET
0
1
2
3
MODE SELECT — FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
Parallel load (Dn→Qn)
CP
U/D
CEP
CET
PE
D
Q
TC
n
n
↑
↑
X
X
X
X
X
X
l
l
L
(1)
(1)
X
X
H
h
l
l
l
l
l
h
h
X
X
Count Up
(1)
(1)
Count Up (increment)
Count Down (decrement)
Hold (do nothing)
↑
↑
Count Down
X
X
h
X
X
h
h
X
X
q
n
(1)
H
↑
↑
X
q
n
H = High voltage level steady state
h
L
l
= High voltage level one setup time prior to the Low-to-High clock transition
= Low voltage level steady state
= Low voltage level one setup time prior to the Low-to-High clock transition
q
= Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
= Low-to-High clock transition
↑
(1)= The TC is Low when CET is Low and the counter is at Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).
3
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
MODE SELECT TABLE
STATE DIAGRAM
INPUTS
OPERATING MODE
0
1
2
3
4
5
6
7
PE
CEP
CET
U/D
L
X
L
L
H
X
X
L
L
X
H
X
H
L
X
X
Load(D →Q )
n n
15
14
13
H
H
H
H
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
H = High Voltage
= Low Voltage Level
L
X = Don’t care
12
11
10
9
8
COUNT DOWN
COUNT UP
SF00788
LOGIC DIAGRAM
3
D
Q
Q
D
0
14
Q
CP
0
4
D
Q
Q
D
D
D
1
2
3
13
Q
CP
1
D
Q
5
12
Q
CP Q
2
D
Q
6
9
11
Q
CP Q
3
PE
7
10
CEP
CET
2
1
CP
U/D
15
TC
V
= Pin 16
CC
GND = Pin 8
SF00789
4
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
APPLICATION
CP
U/D
PE
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
PE
PE
PE
U/D
CP
PE
U/D
CP
U/D
CP
U/D
CP
TC
TC
TC
TC
CEP
CET
CEP
CET
CEP
CET
CEP
CET
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2 3
LEAST SIGNIFICANT
4-BIT COUNTER
MOST SIGNIFICANT
4-BIT COUNTER
SF00790
Figure 1. Synchronous Multistage Counting Scheme
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
V
V
CC
IN
I
IN
mA
V
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
40
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
STG
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
Nom
UNIT
Min
Max
V
V
V
Supply voltage
4.5
2.0
5.0
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature range
OH
OL
20
T
amb
0
70
5
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
NO TAG
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
TYP
MIN
MAX
NO TAG
2.5
2.7
V
V
V
V
V
±10%V
±5%V
CC
V
V
= MIN, V = MAX,
IL
CC
IH
V
High-level output voltage
OH
= MIN, I = MAX
OH
3.4
0.35
0.35
–0.73
CC
0.50
0.50
–1.2
±10%V
CC
V
V
= MIN, V = MAX,
IL
CC
IH
V
V
Low-level output voltage
Input clamp voltage
OL
= MIN, I = MAX
OL
±5%V
CC
V
CC
V
CC
= MIN, I = I
I IK
IK
Input current at maximum input
voltage
I
I
= MAX, V = 7.0V
100
µA
I
I
High-level input current
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 2.7V
20
–1.2
–0.6
–150
52
µA
mA
mA
mA
mA
IH
IL
I
CET
= MAX, V = 0.5V
I
I
Low-level input current
Others
= MAX, V = 0.5V
I
NO TAG
I
I
Short-circuit output current
= MAX
= MAX
–60
OS
4
Supply current (total)
35
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. I is measured after applying a momentary 4.5V, then ground to the clock input with all other inputs grounded and all outputs open.
CC
6
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST CONDITIONS
V
CC
= +5V
V
CC
= +5V ± 10%
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Propagation delay
Waveform 1
Waveform 1
100
115
90
MHz
MAX
t
t
3.0
4.0
6.5
9.0
8.5
11.5
3.0
4.0
9.5
13.0
ns
ns
PLH
PHL
CP to Q (PE, High or Low)
n
t
t
Propagation delay
CP to TC
5.5
4.0
12.0
8.5
15.5
11.0
5.5
4.0
17.0
12.5
ns
ns
PLH
PHL
Waveform 1
Waveform 2
Waveform 3
t
t
Propagation delay
CET to TC
2.5
2.5
4.5
6.0
6.0
8.0
2.5
2.5
7.0
9.0
ns
ns
PLH
PHL
t
t
Propagation delay
U/D to TC
3.5
4.0
8.5
8.0
15.0
10.5
3.5
4.0
15.5
12.0
ns
ns
PLH
PHL
AC SETUP REQUIREMENTS
LIMITS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
D to CP
n
4.0
4.0
4.5
4.5
ns
ns
s
Waveform 4
Waveform 4
Waveform 5
Waveform 5
Waveform 4
Waveform 4
Waveform 6
Waveform 6
Waveform 1
t (H)
Hold time, High or Low
D to CP
n
3.0
3.0
3.5
3.5
ns
ns
h
t (L)
h
t (H)
Set-up time, High or Low
CEP or CET to CP
5.0
5.0
5.5
5.5
ns
ns
s
t (L)
s
t (H)
Hold time, High or Low
CEP or CET to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
Set-up time, High or Low
PE to CP
8.0
8.0
9.0
9.0
ns
ns
s
t (L)
s
t (H)
Hold time, High or Low
PE to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
Set-up time, High or Low
U/D to CP
11.0
7.0
12.5
8.0
ns
ns
s
t (L)
s
t (H)
Hold time, High or Low
U/D to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
CP or CP pulse width,
5.0
5.0
5.5
5.5
ns
ns
w
U
D
t (L)
w
High or Low
7
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
AC WAVEFORMS
For all waveforms, V = 1.5V
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CET
TC
V
V
M
M
CP
V
V
V
M
M
M
t
t
PLH
PHL
t
(H)
W
t (L)
W
t
t
t
t
PLH
PHL
V
V
M
M
V
V
V
M
M
M
M
SF00792
Q
n
PLH
PHL
Waveform 2. Propagation Delays CET Input to
Terminal Count Output
TC
V
SF00791A
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
D
n
V
V
h
M
M
t
t
s
PE
V
V
V
V
M
M
M
M
V
V
M
U/D
TC
M
t (L)
t
h
= 0
t (H)
s
t = 0
h
s
t
t
PLH
PHL
V
V
M
M
V
V
M
CPn
M
SF00793
SF00794
Waveform 3. Propagation Delay U/D Input to
Terminal Count Output
Waveform 4. Parallel Data and Parallel Enable
Setup and Hold Times
CET
CEP
U/D
V
V
V
V
M
M
M
M
V
V
V
V
M
M
M
M
t (L)
t (L)
h
t (H)
s
t (H)
h
s
t (L)
t (L)
h
t (H)
s
t (H)
h
s
V
V
M
CPn
M
V
V
CPn
M
M
Q
n
COUNT DOWN
COUNT UP
NO
CHANGE
Q
n
V
V
M
NO CHANGE
COUNT
M
SF00795
SF00796
Waveform 5. Count Enable Setup and Hold Times
Waveform 6. Up/Down Control Setup and Hold Times
8
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences)
PE
D
0
D
1
D
2
D
3
CP
U/D
CEP and CET
Q
0
Q
1
Q
2
Q
3
TC
SEQUENCE
7
8
9
0
1
2
2
2
1
0
9
8
7
COUNT UP
INHIBIT
COUNT DOWN
LOAD
SF00797
NOTES:
The operation of the 74F169 is similar to the Illustration above.
1. Load (preset) to BCD seven
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
TEST CIRCUIT AND WAVEFORM
t
AMP (V)
90%
V
w
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
9
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F168*, 74F169
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
10
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F168*, 74F169
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
11
1996 Jan 05
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F168*, 74F169
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
(print code)
Date of release: July 1994
9397-750-05087
Document order number:
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明