74F1763 [NXP]
Intelligent DRAM controller IDC; 智能DRAM控制器IDC
| 型号： | 74F1763 |
| 厂家： | 
NXP |
| 描述： | Intelligent DRAM controller IDC |
| 文件： | 总16页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F1763
Intelligent DRAM controller (IDC)
Product specification
1999 Jan 08
Supersedes data of 1989 Nov 17
IC15 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
FEATURES
• DRAM signal timing generator
ability to select the RAS precharge time and Row-Address Hold time
to fit the particular DRAMs being used. DTACK has been modified
from previous family parts to become a negative true, tri-stated
output. The options for latched or unlatched address are contained
on a single device by the addition of an Address Latch Enable (ALE)
input. Finally, a burst refresh monitor has been added to ensure
complete refreshing after length page-mode access cycles. With a
maximum clock frequency of 100 MHz, the F1763 is capable of
controlling DRAM arrays with access times down to 40 nsec.
• Automatic refresh circuitry
• Selectable row address hold and RAS precharge times
• Facilitates page mode accesses
• Controls 1 MBit DRAMs
• Intelligent burst-mode refresh after page-mode access cycles
TYPICAL SUPPLY CURRENT
TYPE
f
MAX
(TOTAL)
PRODUCT DESCRIPTION
The Philips Semiconductors Intelligent Dynamic RAM Controller is a
1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM
Controller. It contains automatic signal timing, address multiplexing
and refresh control required for interfacing with dynamic RAMs.
Additional features have been added to this device to take
advantage of technological advances in Dynamic RAMs. A
Page-Mode access pin allows the user to assert RAS for the entire
access cycle rather than the pre-defined four-clock-cycle pulse width
used for normal random access cycles. In addition, the user has the
74F1763
100 MHz
150 mA
ORDERING INFORMATION
COMMERCIAL RANGE
V
T
= 5V "10%;
PACKAGES
PKG DWG #
CC
= 0_C TO 70_C
A
48-pin Plastic DIP
N74F1763N
SOT240-1
NO TAG
INPUT AND OUTPUT LOADING FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/80
LOAD VALUE HIGH/LOW
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
35 mA/60 mA
35 mA/60 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
35 mA/60 mA
35 mA/60 mA
35 mA/60 mA
REQ
DRAM Request Input
Clock Input
CP
PAGE
Page Mode Select Input
PRECHRG RAS Precharge Select Input
HLDROW
DTACK
GNT
Row Hold Select Input
Data Transfer Ack. Output
Access Grant Output
50/80
RCP
Refresh Clock Input
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
NA
RA0–9
CA0–9
ALE
Row Address Inputs
Column Address Inputs
Address Latch Enable Input
Row Address Strobe Output
Column Address Strobe Output
DRAM Address Outputs
RAS
CAS
NA
MA0–9
NOTES:
NA
One (1.0) FAST Unit Load is defined as 20 mA in the HIGH state and 0.6 mA in the LOW state.
FAST Unit Loads do not correspond to DRAM Input Loads. See Functional Description for details.
2
1999 Jan 08
853–1406 20619
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
BLOCK DIAGRAM
RAS
CAS
PAGE
CP
PRECHRG
HLDROW
RAS, CAS, MUX, DTACK
TIMING
DTACK
REFRESH
ARBITRATION
REQ
GNT
BURST REFRESH MONITOR
REFRESH ADDRESS COUNTER
RCP
RA0–9
CA0–9
ROW ADDRESS LATCH
MULTIPLEXER
MA0–9
COLUMN ADDR. LATCH
ALE
SF01400
DIP PIN CONFIGURATION
PLCC PIN CONFIGURATION
GNT
REQ
1
2
48
47
HLDROW
PRECHRG
RAS
PAGE
3
46 CP
4
45
44
43
42
41
40
RCP
RA0
CA0
5
CAS
6
DTACK
MA0
6
5
4
3
2
1
44 43 42 41 40
7
RA1
CA1
8
7
8
39
38
37
36
35
CA0
RA1
CA1
MA1
MA0
MA1
MA2
MA3
GND
9
RA2
MA2
9
10
11
39 CA2
MA3
10
11
RA2
CA2
38
37
36
V
V
GND
CC
CC
GND 12
12
34
33
32
31
30
29
GND
V
CC
13
V
GND
CC
MA4 13
RA3
CA3
RA4
CA4
14
15
16
17
35 RA3
34
GND
MA4
MA5
MA6
MA5
MA6
14
15
16
17
CA3
33 RA4
MA7
MA8
32
CA4
RA5
MA7 18
MA8 19
31
30
29
28
27
26
25
RA5
CA5
18 19 20 21 22 23 24 25 26 27 28
20
RA6
CA6
MA9
21
22
23
24
ALE
CA9
RA9
CA8
RA7
CA7
RA8
SF01401
SF01402
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1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
PIN DESCRIPTION
PINS
SYMBOL
TYPE
NAME AND FUNCTION
DIP
Active Low Memory Access Request input, must be asserted for the entire DRAM access cycle.
REQ is sampled on the rising edge of the CP clock.
REQ
GNT
48
Input
Output
Input
Active High Grant output. When High indicates that a DRAM access (inactive during refresh)
cycle has begun. Asserted from the rising edge of the CP clock.
1
Active Low Page-Mode Access input. Forces the IDC to keep RAS asserted for as long as the
PAGE input is Low and REQ is asserted Low.
PAGE
47
Row Address Hold input. If Low will configure the IDC to maintain the row addresses for a full
CP clock cycle after RAS is asserted. If High will program the IDC to maintain row addresses for
a 1/2 CP clock cycle after RAS is asserted.
HLDROW
2
3
Input
Input
RAS Precharge input. A Low will program the IDC to guarantee a minimum of 4 CP clock cycles
of precharge. A High will guarantee 3 clock cycles of precharge.
PRECHRG
CP
46
45
Input
Input
Clock input. Used by the Controller for all timing and arbitration functions.
RCP
Refresh Clock input. Divided internally by 64 to produce an internal Refresh Request.
Active Low, 3-state Data Transfer Acknowledge output. Enabled by the REQ input and asserted
four clock cycles after the assertion of RAS, 3-stated when REQ goes High.
DTACK
6
Output
44, 42, 40,
35, 33, 31,
29, 27, 25,
23
RA0–9
Inputs
Row Address inputs.
43, 41, 39,
34, 32, 30,
28, 26, 24,
22
Column Address inputs. Propagated to the MA0–9 outputs 1 CP clock cycle after RAS is
asserted, if HLDROW = 0 or 1/2 clock cycle later if HLDROW is 1.
CA0–9
RAS
Inputs
Active Low Row Address Strobe. Asserted for four clock cycles during each refresh cycle
regardless of the PAGE input. Also asserted for four clock cycles during processor access if the
PAGE input is High. If PAGE is Low, RAS is negated upon negation of PAGE or REQ, whichever
occurs first.
4
5
Output
Active Low Column Address Strobe. Always asserted 1.5 CP clock cycles after the assertion of
RAS. Negated upon negation of REQ. HLDROW input pin does not affect RAS to CAS timing.
CAS
MA0–9
ALE
Output
Output
Input
7–10,
15–20
DRAM multiplexed address outputs. Row and column addresses asserted on these pins during
an access cycle. Refresh counter addresses presented on these outputs during refresh cycles.
Active Low Address Latch Enable input. A Low on this pin will cause the address latches to be
transparent. A High level will latch the RA0–9 and CA0–9 inputs.
21
V
36–38
11–14
+5V "10% Supply voltage.
CC
GND
Ground
4
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
FUNCTIONAL DESCRIPTION
RAS precharge timing
The 74F1763 1 Megabit Intelligent DRAM Controller (IDC) is a
synchronous device with most signal timing being a function of the
CP input clock.
In order to meet the RAS precharge requirement of dynamic RAMs,
the controller will hold-off a subsequent RAS signal assertion due to
a processor access request or a refresh cycle for four or three full
CP clock cycles from the previous negation of RAS, depending on
the state of the PRECHRG input. If the PRECHRG input is Low,
RAS remains High for at least 4 CP clock cycles. If the PRECHRG
input is High RAS remains High for at least 3 CP clock cycles.
Arbitration
Once the DRAM’s RAS precharge time has been satisfied, the REQ
input is sampled on each rising edge of the CP clock and an
internally generated refresh request is sampled on each falling edge
of the same clock. When only one of these requests is sampled as
active the appropriate memory cycle will begin immediately. For a
memory access cycle this will be indicated by GNT and RAS outputs
both being asserted and for a refresh cycle by multiplexing refresh
address to the MA0–9 outputs and subsequent assertion of RAS
after 1/2CP clock cycle. If both memory access and refresh requests
are active at a given time the request sampled first will begin
immediately and the other request (if still asserted) will be serviced
upon completion of the current cycle and it’s associated RAS
precharge time.
Refresh timing
The refresh address counter wakes-up in an all 1’s state and is an
up counter. The refresh clock (RCP) is internally divided down by 64
to produce an internal refresh request. This refresh request is
recognized either immediately or at the end of a running memory
access cycle. Due to the possibility that page mode access cycles
may be lengthy, the controller keeps track of how many refresh
requests have been missed by logging them internally (up to 128)
and servicing any pending refresh requests at the end of the
memory access cycle. The controller performs RAS-only refresh
cycles until all pending refresh requests are depleted.
Memory access
Page-mode access
The row (RA0–9) and column (CA0–9) address inputs are latched
when ALE input is High. When ALE is Low the input addresses
propagate directly to the outputs. When GNT and RAS are asserted,
after a REQ has been sampled the RA0–9 address inputs will have
already propagated to the MA0–9 outputs for the row address. One
or one-half CP clock cycles later (depending on the state of the
HLDROW input) the column address (CA0–9) inputs are propagated
to the MA0–9 outputs. CAS is always asserted one and one-half CP
clock cycles after RAS is asserted. If the PAGE input is High, RAS
will be negated approximately four CP clock cycles after its initial
assertion. At this time the DTACK output becomes valid indicating
the completion of a memory access cycle. The IDC will maintain the
state of all its outputs until the REQ input is negated ( see timing
waveforms).
Fast accesses to consecutive locations of DRAM can be realized by
asserting the PAGE input as shown in the timing waveforms. In this
mode, the controller does not automatically negate RAS after four
CP clock cycles, but keeps it asserted throughout the access cycle.
By using external gates, the CAS output can be gated on and off
while changing the column address inputs to the controller, which
will propagate to the MA –MA address outputs and provide a new
0
9
column address. This is only useful if the ALE input is Low, enabling
the user to charge addresses. This mode can be used with DRAMs
that support page or nibble mode addressing.
Output driving characteristics
Considering the transmission line characteristic of the DRAM arrays,
the outputs of the IDC have been designed to provide incident-edge
switching (in Dual-Inline-Packaged memory arrays), needed in high
performance systems. For more information on the driving
characteristics, please refer to Philips Semiconductors application
note AN218. The driving characteristics of the 74F1763 are the
same as those of the 74F765 shown in the application note.
Row address hold times
If the HLDROW input of the IDC is High the row address outputs will
remain valid 1/2 CP clock cycle after RAS is asserted. If the
HLDROW input is Low the row address outputs will remain valid one
CP clock cycle after RAS is asserted.
5
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted, these limits are over the
operating free-air temperature range.
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
Supply voltage
Input voltage
Input current
V
IN
V
I
IN
mA
V
V
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
120
CC
I
mA
_C
_C
OUT
T
A
0 to +70
T
STG
–65 to +150
RECOMMENDED OPERATION CONDITIONS
LIMITS
NOM
5.0
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
CC
Supply voltage
5.5
V
V
V
IH
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
2.0
V
0.8
–18
–15
24
V
IL
IK
I
mA
mA
mA
_C
1
I
OH
1
I
OL
Low-level output current
Operating free-air temperature range
T
A
0
70
NOTE:
1. Transient currents will exceed these values in actual operation.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.5
2.7
2.4
TYP
MAX
"10% V
"5% V
V
V
CC
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
I
= –15 mA
OH
V
OH
High-level output voltage
3.4
CC
CC
IH
3
I
= –35 mA "5% V
V
OH2
"10% V
"5% V
0.35
0.35
0.50
0.50
0.80
–1.2
100
V
CC
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
I
= 24 mA
OL
V
Low-level output voltage
V
OL
CC
CC
IH
4
I
= 60 mA
"5% V
0.35
V
OL2
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73
V
IK
I
I
Input current at maximum input voltage
High-level input current
= 0.0V, V = 7.0V
mA
mA
mA
mA
mA
I
I
I
IH
= MAX, V = 2.7V
20
I
I
Low-level input current
= MAX, V = 0.5V
–0.6
–225
220
IL
I
5
I
I
Output current
= MAX, V = 2.25V
–100
OS
CC
O
Supply current (total)
= MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25_C.
CC
A
3. I
4. I
is transient current necessary to guarantee a Low to High transition in a 70W transmission line.
is transient current necessary to guarantee a High to Low transition in a 70W transmission line.
OH2
OL2
5. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In
any sequence of parameter tests, I tests should be performed last.
OS
6
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
AC ELECTRICAL CHARACTERISTICS
LIMITS
MAX
T
= 25_C
T
V
= 0_C to +70_C
= +5.0V "10%
CC
A
A
V
= +5.0V "10%
TEST
CONDITIONS
CC
NO
PARAMETER
UNIT
C = 300pF
C = 300pF
L
L
R = 70W
RL = 70W
L
MIN
10
5
TYP
MIN
MAX
1
2
3
4
5
6
7
8
9
CP clock period (tcp)
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CP clock low time
5
CP clock high time
5
5
RCP clock period
100
10
10
4
100
RCP clock low time
10
RCP clock high time
Setup time REQ(#) to CP(")
REQ High hold time after CP(")
10
2
4
1
0
0
2
REQ High pulse width
1/2tcp + 5
8.5
1/2tcp + 5
11
1/2tcp + 5
13.5
1/2tcp + 5
8.5
1/2tcp + 5
15.5
10 Propagation delay CP(") to GNT
High
11
Propagation delay REQ(") to GNT
8.5
10.5
13
8.5
14
ns
Low
12 ALE pulse width Low
4
2
1
0
4
2
ns
ns
13 RA0–9, CA0–9 High or Low setup to
ALE(")
14 ALE(") to RA0–9, CA0–9 High or
1
4
0
1
4
ns
ns
Low hold
15 Propagation delay RA0–9, CA0–9
ALE Low
7.5
11
14
3
High or Low to MA0–9
16 Propagation delay ALE(#) to MA0–9
17 Propagation delay CP(") to RAS(#)
5.5
8.5
8.5
13
5.5
8.5
15
14
ns
ns
ns
10.5
12.5
18 RAS(#) to MA0–9 (column address)
HLDROW = 1
HLDROW = 0
PAGE = 1
1/2tcp – 2
1/2tcp + 2 1/2tcp + 5.5 1/2tcp – 2.5 1/2tcp + 7
skew
19 RAS(#) to MA0–9 (column address)
1tcp – 2
1tcp + 2
1tcp + 5.5
1tcp – 2.5
1tcp + 7
ns
skew
20 RAS(#) to RAS(") skew
4tcp + 1.5
12
4tcp + 3.5
14
4tcp + 6
16.5
4tcp + 1
12
4tcp + 6.5
18.5
ns
ns
ns
21 Propagation delay CP(") to RAS(")
22 Propagation delay REQ(") to
14.5
17.5
20
14
24
4
RAS(")
23 Propagation delay CP(#) to CAS(#)
24 Propagation delay PAGE(") to
6
8
10
15
6
11
17
ns
ns
10
12.5
10
4
RAS(")
25 RAS(#) to CAS(#) skew
1.5tcp–4.5 1.5tcp–2.5 1.5tcp–0.5
1.5tcp–5.5
10
1.5tcp
17
ns
ns
ns
26 Propagation delay REQ(") to CAS(")
10
12
15
27 MA0–9 (column address) to CAS(#)
1tcp – 8
1tcp – 4
1tcp – 0.5
1tcp – 9
1tcp – 0.5
skew
28 MA0–9 (column address) to CAS(#)
HLDROW = 0
1/2tcp – 8
2
1/2tcp – 4 1/2tcp – 0.5 1/2tcp – 9 1/2tcp – 0.5
ns
ns
skew
29 Set-up time PAGE(#) to CP(")
2
7
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
AC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
T
= 25_C
T
V
= 0_C TO +70_C
= +5.0V "10%
CC
A
A
V
CC
= +5.0V "10%
TEST
CONDITIONS
NO
PARAMETER
UNIT
C = 300pF
R = 70W
L
C = 300pF
RL = 70W
L
L
MIN
TYP
MAX
MIN
MAX
30 Propagation delay REQ(#) to
DTACK(")
6
8
11.5
6
12
ns
ns
ns
ns
ns
ns
ns
31 Propagation delay CP(") to
DTACK(#)
7.5
9
9.5
12
12
13
7.5
9
13
32 Propagation delay REQ(") to
15.5
DTACK (3-state)
33 MA0–9 (refresh address) to
1/2tcp – 5
1tcp – 2
4tcp – 6
3tcp – 6
1/2tcp – 6.5
1tcp – 2.5
4tcp – 6.5
3tcp + 1
RAS(#) skew
34 RAS(#) to MA0–9 (refresh
address) skew
35 RAS(") to RAS(#) skew
PRECHRG = 0
PRECHRG = 1
4tcp – 3.5
3tcp – 3.5
4tcp – 1.5
3tcp – 1.5
4tcp – 6.5
3tcp – 6.5
(precharge)
36 RAS(") to RAS(#) skew
(precharge)
NOTES:
1. REQ High hold means that, if REQ is High at the rising clock edge, it is guaranteed that the REQ input was not sampled as Low.
2. A 50% duty cycle clock is recommended. If the duty cycle of the clock is not 50%, REQ should be held high for enough time such that a
falling CP clock edge samples REQ as High. This is to ensure that refresh cycles don’t get locked-up.
3. When ALE is Low, the address input latches are in the transparent mode and therefore any changes in the address inputs will be propagated
to the MA0–9 outputs. Figure 2 illustrates RA0–9 inputs propagating to the MA0–9 outputs, but later in the cycle, if ALE is still Low when the
CA0–9 inputs are multiplexed to the MA0–9 outputs the CA0–9 inputs will be in the transparent mode.
4. If PAGE is High and REQ is Low, RAS is automatically negated after approximately 4 CP clock cycles. If PAGE is Low and REQ is also Low,
RAS will be negated when PAGE goes High. RAS will always be negated when REQ goes High regardless of the state of PAGE input.
TIMING DIAGRAMS
1
3
CP
2
4
6
RCP
5
SF01403
Figure 1. Clock cycle timing
8
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TIMING DIAGRAMS (Continued)
CP
8
9
7
REQ
11
10
GNT
ALE
12
14
13
VALID
ADDRESS
NOTE 1
RA0–9,
CA0–9
15
HLDROW = 0
16
HLDROW = 1
VALID ROW ADDRESS
NOTE 2
VALID COLUMN ADDRESS
21
MA0–9
RAS
18
17
22
19
20
23
24
26
PAGE = 1
25
CAS
28
27
29
NOTE 3
PAGE
31
30
32
3-STATE
DTACK
3-STATE
NOTE 1: If the RA0–9 and CA0–9 address inputs are not latched, RA0–9 inputs should remain valid until row address hold time is met and CA0–9 inputs should remain valid until column
address hold time is met.
NOTE 2: MA0–9 outputs will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.
NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low.
SF01404
Figure 2. Memory access cycle timing
9
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TIMING DIAGRAMS (Continued)
CP
REQ
GNT
ALE
NOTE 1
NOTE 2
NOTE 3
RA0–9,
CA0–9
PRECHRG = 1
PRECHRG = 0
REFRESH
ADDR.
REFRESH
ADDR.
MA0–9
NEXT REFRESH ADDRESS
NOTE 4
33
33
34
34
35
20
36
20
RAS
PRECHRG = 1
PRECHRG = 0
PRECHRG = 1
PRECHRG = 0
CAS
DTACK
3-STATE
NOTE 1: REQ input is a don’t care during a memory refresh cycle. If REQ is asserted during a refresh cycle, it will be recognized at the first rising CP clock edge, following the refresh
cycle and its associated RAS precharge time (see Figure 4).
NOTE 2: RA0–9 and CA0–9 address inputs may be latched at anytime during a memory refresh cycle. However, a memory access cycle will not begin until after the completion of the
refresh cycle.
NOTE 3: RA0–9 and CA0–9 if in the transparent mode do not propogate to the MA0–9 outputs during a refresh cycle.
NOTE 4: MA0–9 output will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.
SF01405
Figure 3. Refresh cycle timing following a memory access cycle
10
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TIMING DIAGRAMS (Continued)
CP
8
9
7
REQ
GNT
11
10
ALE
12
14
13
VALID
ADDRESS
NOTE 1
RA0–9,
CA0–9
15
HLDROW = 0
16
HLDROW = 1
REFRESH
ADDRESS
REFRESH
ADDRESS
VALID ROW ADDRESS
NOTE 2
VALID COLUMN ADDRESS
MA0–9
RAS
18
PRECHRG = 0
PRECHRG = 1
17
22
21
19
20
23
36
24
26
PAGE = 1
35
25
CAS
28
27
29
NOTE 3
PAGE
31
30
32
3-STATE
DTACK
3-STATE
NOTE 1: If the RA0–9 and CA0–9 address inputs are not latched, RA0–9 inputs should remain valid until row address hold time is met and CA0–9 inputs should remain valid until column
address hold time is met.
NOTE 2: MA0–9 outputs will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.
NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low.
SF01406
Figure 4. Memory access cycle timing following a refresh cycle
11
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
PU
1, 7, 9, 10
F160A
Q0
33.34 MHz
CP
Q2
16.67 MHz
CPU CLOCK
CP
RCP
PU
D
C
Q
D
C
PRECHRG
RAS
CAS
RAS
Q
HLROW
74F1763
DRAM
CONTROLLER
REQ
MEMORY
SELECT
(FROM ADDRESS DECODER
PAGE
AS
ALE
A3
A2
CA9
RA9
MA0–MA9
MA0–MA9
A4–A12
RA0–8
CA0–8
A13–A21
CAS0
CAS1
A0
A1
PLD
10
CAS2
CAS3
SIZ0
SIZ1
STERM
D
C
Q
Q
DS
CP
Q3
F164
MR
CBACK
CBREQ
DSACK0
D
Q
DSACK1
C
SF01407
Figure 5. 16.67 MHz 68030 interface with 74F1763 for cache burst mode support using 4Mbytes of 100nsec. nibble-mode DRAMs
(Four 32 bit words read to or written from cache in only clock cycles
12
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
R
L
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
L
t
t )
T
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit Simulating RAM Boards
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
C
=
=
Load resistor; see AC CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
L
L
Family
V
Rep. Rate
t
t
t
Amplitude
M
R
T
=
Termination resistance should be equal to Z
pulse generators.
of
w
TLH
THL
OUT
2.5ns 2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF01408
13
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
14
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
NOTES
15
1999 Jan 08
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 02-99
Document order number:
9397-750-05195
Philips
Semiconductors
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