74F199 [NXP]
8-bit parallel-access shift register; 8位并行存取移位寄存器
| 型号： | 74F199 |
| 厂家： | 
NXP |
| 描述： | 8-bit parallel-access shift register |
| 文件： | 总8页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
FEATURES
PIN CONFIGURATION
• Buffered clock and control inputs
1
24
23
22
21
20
19
18
17
16
15
14
13
V
K
CC
• Shift right and parallel load capability
• Fully synchronous data transfers
• J-K(D) inputs to first stage
2
3
J
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CE
PE
D7
Q7
D6
Q6
D5
Q5
4
5
• Clock enable for hold (do nothing) mode
• Asynchronous Master Reset
6
7
8
9
DESCRIPTION
D4
Q4
The 74F199 is an 8-bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. The device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial-to-parallel,
or parallel–to-serial data transfers at very high speeds.
10
11
MR
CP
GND 12
SF00152
The 74F199 operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0→Q1→Q2 following each Low-to-High clock transition.
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F199
95MHz
70mA
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
ORDERING INFORMATION
COMMERCIAL RANGE
The device appears as eight common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D7) is transferred to the respective Q0–Q7
outputs.
DESCRIPTION
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
24-pin plastic slim DIP
(300mil)
N74F199N
N74F199D
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F199 utilizes
edge-triggered, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the setup and
hold time requirements.
24-pin plastic SOL
A Low on the Master Reset (MR) input overrides all other inputs and
clears the register asynchronously forcing all bit positions to a Low
state.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0–D7
J, K
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
LOAD VALUE HIGH/LOW
20µA/0.6mA
Parallel data inputs
J and K inputs
1.0/1.0
20µA/0.6mA
PE
Parallel Enable input
Clock Enable input
1.0/1.0
20µA/0.6mA
CE
1.0/1.0
20µA/0.6mA
DP
Clock Pulse inputs (Active rising edge)
Master Reset input (Active Low)
Data outputs
1.0/1.0
20µA/0.6mA
MR
1.0/1.0
20µA/0.6mA
Q0–Q7
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1
June 15, 1988
853–0082 93568
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
LOGIC SYMBOL
IEEE/IEC SYMBOL
SRG8
C2/→
3
5
7
9
16 18 20 22
11
13
1
1
&
23
14
C3
R
D0 D1 D2 D3 D4 D5 D6 D7
23
2
PE
J
1
K
2
1
2J
4
13
11
14
CP
CE
MR
2K
3
2, 3D
2, 3D
5
6
8
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
9
10
15
17
19
21
16
18
20
22
4
6
8
10 15 17 19 21
V
= Pin 24
CC
GND = Pin 12
SF00153
SF00154
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODES
Reset (clear
MR
L
CP
X
↑
CE
PE
X
h
J
X
h
l
K
X
h
l
Dn
X
Q0
L
Q1
L
…
…
…
…
…
…
…
…
Q6
L
Q7
L
X
l
H
X
H
q0
q0
q0
q0
d1
q1
q5
q5
q5
q5
d6
q6
q6
q6
q6
q6
d7
q7
Shift, set First stage
Shift, reset First stage
Shift, toggle First stage
Shift, retain First stage
Parallel load
H
↑
l
h
X
L
H
↑
l
h
h
l
l
X
q0
q0
d0
q0
H
↑
l
h
h
X
X
X
H
↑
l
l
X
X
dn
X
H
↑
h
X
Hold (do nothing)
H
h
L
l
X
↑
=
=
=
=
=
=
High voltage level
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup time prior t the Low-to-High clock transition
Don’t care
Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition
2
June 15, 1988
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
LOGIC DIAGRAM
11
CE
13
CP
23
PE
2
J
1
K
R
CP
S
4
Q0
Q
Q
14
MR
RD
3
D0
5
D1
R
CP
S
S
S
S
S
S
S
6
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q
Q
Q
Q
Q
Q
Q
RD
7
D2
R
CP
8
RD
9
D3
R
CP
10
15
17
19
21
RD
16
D4
R
CP
RD
18
D5
R
CP
RD
20
D6
R
CP
RD
22
D7
R
CP
RD
SF00155
3
June 15, 1988
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
TYPICAL TIMING DIAGRAM
CP
CE
MR
J
SERIAL
INPUTS
K
PE
D0
D1
D2
H
L
H
L
PARALLEL
DATA
INPUTS
D3
D4
H
L
D5
D6
D7
H
H
Q0
Q1
Q2
Q3
OUTPUTS
Q4
Q5
Q6
Q7
L
L
L
H
H
H
H
H
INHIBIT
LOAD
SERIAL SHIFT
SERIAL SHIFT
CLEAR
Typical Load, Serial-Shift, Inhibit and Clear Sequences
SF00156
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
40
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
5.0
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
Supply voltage
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
+70
4
June 15, 1988
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
2
MIN
2.5
TYP
V
V
V
V
V
V
V
V
V
= MIN, V = MAX ±10%V
CC
IL
CC
V
OH
High-level output voltage
V
= MIN, I = MAX
±5%V
2.7
3.4
0.35
0.35
–0.73
IH
OH
CC
= MIN, V = MAX ±10%V
0.50
V
0.50
CC
IL
CC
CC
V
V
Low-level output voltage
OL
= MIN, I = MAX
±5%V
IH
OL
Input clamp voltage
= MIN, I = I
IK
–1.2
100
20
V
IK
CC
CC
CC
CC
CC
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
µA
µA
mA
mA
I
I
= MAX, V = 2.7V
IH
IL
I
Low-level input current
= MAX, V = 0.5V
–0.6
–150
90
I
3
Short-circuit output current
= MAX
–60
OS
I
65
75
CCH
I
Supply current (total)
V
CC
= MAX
mA
CC
I
105
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
5
June 15, 1988
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
80
95
70
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
5.5
6.5
8.0
9.5
11.0
12.5
4.5
3.5
12.0
13.5
PLH
PHL
Propagation delay
MR to Qn
t
Waveform 2
5.5
8.0
10.5
5.0
12.0
ns
PHL
AC SETUP REQUIREMENTS
LIMITS
V
= +5.0V
= +25°C
V
T
= +5.0V ± 10%
= 0°C to +70°C
amb
CC
CC
TEST
CONDITION
SYMBOL
PARAMETER
T
amb
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
S
Setup time, High or Low
Dn to CP
0.0
1.5
0.0
2.5
S
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
ns
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
2.0
4.5
2.5
5.5
h
t (L)
h
t (H)
Setup time, High or Low
J, K to CP
0.0
2.5
0.0
3.0
s
t (L)
s
t (H)
Hold time, High or Low
J, K to CP
0.0
3.5
0.0
4.0
h
t (L)
h
t (H)
Setup time, High or Low
CE to CP
0.0
2.5
0.0
3.0
s
t (L)
s
t (H)
Hold time, High or Low
CE to CP
0.0
4.5
0.0
5.5
h
t (L)
h
t (H)
Setup time, High or Low
PE to CP
8.0
8.0
9.0
9.0
s
t (L)
s
t (H)
Hold time, High or Low
PE to CP
0.0
0.0
0.0
0.0
h
t (L)
h
t (H)
CP pulse width, High
MR pulse width, Low
Waveform 1
Waveform 2
4.5
4.0
5.5
4.5
ns
ns
w
t (L)
w
Recovery time
MR to CP
t
Waveform 2
5.5
6.5
ns
rec
6
June 15, 1988
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
MR
CP
1/f
MAX
V
V
t
M
M
t
(L)
CP
Qn
w
REC
V
V
M
t
M
t
V
(H)
M
w
PLH
t
PHL
t
PHL
V
M
Qn
V
M
SF00157
SF00158
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Widths, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
CE
V
V
V
M
M
M
t (H)
t = 0
h
s
t (L)
s
t
h
PE
Dn
V
V
M
M
t (L)
t
= 0
t (L)
t = 0
h
s
h
s
STABLE
V
V
M
M
t
t
h
s
J, K
CP
STABLE
V
V
V
M
M
M
t
h
t
s
V
V
M
M
SF00159
Waveform 3. Setup Time and Hold Time
7
June 15, 1988
Philips Semiconductors FAST Products
Product specification
8-bit parallel-access shift register
74F199
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
74F
V
M
rep. rate
t
t
t
amplitude
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
8
June 15, 1988
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