74F20 [NXP]

Dual 4-input NAND gate; 两个4输入与非门
74F20
型号: 74F20
厂家: NXP    NXP
描述:

Dual 4-input NAND gate
两个4输入与非门

文件: 总8页 (文件大小:72K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
74F20  
Dual 4-input NAND gate  
Product specification  
IC15 Data Handbook  
1989 Mar 03  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
PIN CONFIGURATION  
TYPE  
TYPICAL  
PROPAGATION  
DELAY  
TYPICAL  
SUPPLY CURRENT  
(TOTAL)  
D0a  
D0b  
NC  
1
2
3
4
5
14  
V
CC  
13 D1d  
12 D1c  
11 NC  
10 D1b  
74F20  
3.5ns  
2.2mA  
D0c  
D0d  
ORDERING INFORMATION  
COMMERCIAL RANGE  
= 5V ±10%,  
V
amb  
DESCRIPTION  
PKG DWG #  
Q0  
6
7
9
8
D1a  
Q1  
CC  
T
= 0°C to +70°C  
GND  
14-pin plastic DIP  
14-pin plastic SO  
N74F20N  
SOT27-1  
SF00065  
N74F20D  
SOT108-1  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
PINS  
Dna, Dnb, Dnc, Dnd  
Q0, Q1  
DESCRIPTION  
74F (U.L.) HIGH/LOW  
LOAD VALUE HIGH/LOW  
20µA/0.6mA  
Data inputs  
1.0/1.0  
50/33  
Data outputs  
1.0mA/20mA  
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.  
LOGIC DIAGRAM  
FUNCTION TABLE  
INPUTS  
Dnb  
OUTPUT  
1
2
D0a  
Dna  
L
Dnc  
X
Dnd  
X
Qn  
H
D0b  
D0c  
D0d  
6
X
L
Q0  
4
5
X
X
X
H
X
X
X
H
L
X
H
X
X
L
H
9
D1a  
D1b  
H
H
H
L
10  
8
NOTES:  
Q1  
12  
13  
H
L
X
= High voltage level  
= Low voltage level  
= Don’t care  
D1c  
D1d  
V
= Pin 14  
CC  
GND = Pin 7  
SF00066  
LOGIC SYMBOL  
IEC/IEEE SYMBOL  
1
2
4
5
9
10 12 13  
1
&
2
4
6
D0a D0b D0c D0d D1a D1b D1c D1d  
5
Q0 Q1  
V
= Pin 14  
CC  
9
GND = Pin 7  
6
8
SF00067  
10  
12  
8
13  
SF00068  
2
March 3, 1989  
853–0332 95935  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
ABSOLUTE MAXIMUM RATINGS  
(Operation beyond the limits set forth in this table may impair the useful life of the device.  
Unless otherwise noted these limits are over the operating free-air temperature range.)  
SYMBOL  
PARAMETER  
RATING  
–0.5 to +7.0  
–0.5 to +7.0  
–30 to +5  
UNIT  
V
V
Supply voltage  
Input voltage  
Input current  
CC  
IN  
V
V
I
mA  
V
IN  
V
Voltage applied to output in High output state  
Current applied to output in Low output state  
Operating free-air temperature range  
Storage temperature range  
–0.5 to V  
40  
OUT  
OUT  
CC  
I
mA  
°C  
°C  
T
amb  
0 to +70  
T
stg  
–65 to +150  
RECOMMENDED OPERATING CONDITIONS  
LIMITS  
SYMBOL  
PARAMETER  
UNIT  
MIN  
4.5  
NOM  
MAX  
V
Supply voltage  
5.0  
5.5  
V
V
CC  
IH  
IL  
V
V
High-level input voltage  
Low-level input voltage  
Input clamp current  
2.0  
0.8  
–18  
–1  
V
I
I
I
mA  
mA  
mA  
°C  
IK  
High-level output current  
Low-level output current  
OH  
OL  
20  
T
amb  
Operating free-air temperature range  
0
+70  
DC ELECTRICAL CHARACTERISTICS  
(Over recommended operating free-air temperature range unless otherwise noted.)  
LIMITS  
1
SYMBOL  
PARAMETER  
TEST CONDITIONS  
UNIT  
V
2
MIN  
2.5  
TYP  
MAX  
V
V
V
V
V
V
= MIN, V = MAX  
±10%V  
CC  
IL  
CC  
V
OH  
High-level output voltage  
= MIN, I = MAX  
±5%V  
2.7  
3.4  
IH  
OH  
CC  
= MIN, V = MAX  
±10%V  
0.30  
0.30  
0.50  
0.50  
–1.2  
100  
CC  
IL  
CC  
CC  
V
V
Low-level output voltage  
V
OL  
= MIN, I = MAX  
±5%V  
IH  
OL  
Input clamp voltage  
= MIN, I = I  
IK  
–0.73  
V
IK  
CC  
CC  
I
I
I
I
I
Input current at maximum input voltage  
= MAX, V = 7.0V  
µA  
I
I
High-level input current  
Low-level input current  
V
CC  
V
CC  
V
CC  
= MAX, V = 2.7V  
20  
–0.6  
–150  
1.4  
µA  
mA  
mA  
IH  
IL  
I
= MAX, V = 0.5V  
I
3
Short-circuit output current  
= MAX  
–60  
OS  
I
V
= GND  
= 4.5V  
IN  
0.9  
3.4  
CCH  
IN  
I
Supply current (total)  
V
CC  
= MAX  
mA  
CC  
I
V
5.1  
CCL  
NOTES:  
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.  
2. All typical values are at V = 5V, T = 25°C.  
CC  
amb  
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold  
OS  
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting  
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any  
sequence of parameter tests, I tests should be performed last.  
OS  
3
March 3, 1989  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
AC ELECTRICAL CHARACTERISTICS  
LIMITS  
V
= +5.0V  
= +25°C  
V
= +5.0V ± 10%  
= 0°C to +70°C  
CC  
CC  
TEST  
CONDITION  
SYMBOL  
PARAMETER  
T
amb  
T
amb  
UNIT  
C
= 50pF, R = 500Ω  
C = 50pF, R = 500Ω  
L L  
L
L
MIN  
TYP  
MAX  
MIN  
MAX  
t
t
Propagation delay  
Dna, Dnb, Dnc, Dnd to Qn  
2.4  
2.0  
3.7  
3.2  
5.0  
4.3  
2.4  
2.0  
6.0  
5.3  
PLH  
PHL  
Waveform 1  
ns  
AC WAVEFORMS  
Dna, Dnb, Dnc, Dnd  
V
V
M
M
t
t
PHL  
PLH  
V
V
M
M
Qn  
SF00069  
Waveform 1. Propagation Delay for Inverting Outputs  
NOTE:  
For all waveforms, V = 1.5V.  
M
TEST CIRCUIT AND WAVEFORMS  
t
w
AMP (V)  
V
CC  
90%  
90%  
NEGATIVE  
PULSE  
V
V
M
M
10%  
10%  
V
V
OUT  
IN  
0V  
PULSE  
GENERATOR  
D.U.T.  
t
t )  
t
t )  
THL ( f  
TLH ( r  
R
C
R
L
t
t )  
T
L
t
t )  
TLH ( r  
THL ( f  
AMP (V)  
0V  
90%  
M
90%  
POSITIVE  
PULSE  
V
V
M
10%  
10%  
Test Circuit for Totem-Pole Outputs  
DEFINITIONS:  
t
w
Input Pulse Definition  
INPUT PULSE REQUIREMENTS  
R
L
C
L
R
T
=
=
=
Load resistor;  
see AC ELECTRICAL CHARACTERISTICS for value.  
Load capacitance includes jig and probe capacitance;  
see AC ELECTRICAL CHARACTERISTICS for value.  
family  
74F  
V
rep. rate  
t
w
t
t
THL  
amplitude  
M
TLH  
Termination resistance should be equal to Z  
pulse generators.  
of  
OUT  
2.5ns 2.5ns  
3.0V  
1.5V  
1MHz  
500ns  
SF00006  
4
March 3, 1989  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
DIP14: plastic dual in-line package; 14 leads (300 mil)  
SOT27-1  
5
1989 Mar 03  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
SO14: plastic small outline package; 14 leads; body width 3.9 mm  
SOT108-1  
6
1989 Mar 03  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
NOTES  
7
1989 Mar 03  
Philips Semiconductors  
Product specification  
Dual 4-input NAND gate  
74F20  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
print code  
Date of release: 10-98  
9397-750-05058  
Document order number:  
Philips  
Semiconductors  

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