74F842 [NXP]
Bus interface latches; 总线接口锁存器型号: | 74F842 |
厂家: | NXP |
描述: | Bus interface latches |
文件: | 总18页 (文件大小:210K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F841/842/843/845/846
Bus interface latches
Product specification
1999 Jun 23
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
IC15 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State)
74F843 9-bit bus interface latch, non-inverting (3-State)
74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEATURES
• High speed parallel latches
DESCRIPTION
The 74F841–74F846 bus interface latch series are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
• Extra data width for wide address/data paths or buses carrying
parity
The 74F841–74F846 series are funcitonally an pin compatible to the
AMD AM29841–AM29846 series.
• High impedance NPN base input structure minimizes bus loading
• IIL is 20µA vs 1000A for AM29841 series
The 74F841 consists of ten D-type latches with 3-State outputs. The
flip-flops appear transparent to the data when Latch Enable (LE) is
High. This allows asynchronous operation, as the output transition
follows the data in transition. On the LE High-to-Low transition, the
data that meets the setup and hold time is latched.
• Buffered control inputs to reduce AC effects
• Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• 48mA sink current
The 74F842 is the inverted output version of the 74F841.
The 74F843 consists of nine D-type latches with 3-State outputs. In
addition to the LE and OE pins, the 74F843 has a Master Reset
(MR) pin and Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When MR is Low, the
outputs are Low if OE is Low. When MR is High, data can be
entered into the latch. When PRE is Low, the outputs are High, if OE
is Low, PRE overrides MR.
• Slim dual in-line 300 mil package
• Broadside pinout
• Pin-for-pin and function compatible with AMD AM29841-846
series
The 74F845 consists of eight D-type latches with 3-State outputs. In
addition to the LE, OE, MR and PRE pins, the 74F845 has two
addtitional OE pins making a total of three Output Enables (OE0,
OE1, OE2) pins.
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
74F841, 74F842
74F843, 74F845
74F846
5.5ns
5.5ns
6.2ns
60mA
75mA
60mA
The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user
control of the interface, e.g., CS, DMA, and RD/WR.
The 74F846 is the inverted output version of the 74F845.
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V±10%; T = 0°C to +70°C
PACKAGE DRAWING
NUMBER
PACKAGES
V
CC
amb
24-pin plastic Slim DIP (300 mil)
24-pin plastic SOL
N74F841N, N74F842N, N74F843N, N74F845N, N74F846N
N74F841D, N74F842D, N74F843D, N74F845D, N74F846D
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
Dn
LE
Data inputs
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1200/80
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
24mA/48mA
24mA/48mA
Latch Enable input
OE, OEn
MR
Output Enable input (active Low)
Master Reset input (active Low)
Preset input (active Low)
Data outputs
PRE
Qn
Qn
Data outputs
1200/80
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
2
1999 Jun 23
853–1208 21851
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
PIN CONFIGURATION for 74F841
PIN CONFIGURATION for 74F842
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
1
24 V
CC
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
CC
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
3
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q0
Q1
Q2
Q3
Q4
Q5
Q6
3
4
4
5
5
6
6
7
7
8
8
9
9
Q7
Q8
Q7
Q8
10
11
10
11
Q9
LE
Q9
LE
GND 12
GND 12
SF01279
SF01282
LOGIC SYMBOL for 74F841
LOGIC SYMBOL for 74F842
2
3
4
5
6
7
8
9
10 11
2
3
4
5
6
7
8
9
10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
1
LE
13
1
LE
OE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
V
= Pin 24
V
= Pin 24
CC
CC
GND = Pin 12
GND = Pin 12
SF01280
SF01283
LOGIC SYMBOL (IEEE/IEC) for 74F841
LOGIC SYMBOL (IEEE/IEC) for 74F842
1
1
EN
EN
13
13
C1
C1
2
3
23
22
21
20
19
18
17
16
15
14
2
3
23
22
21
20
19
18
17
16
15
14
1 D
1 D
4
4
5
5
6
6
7
7
8
8
9
9
10
11
10
11
SF01281
SF01284
3
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
PIN CONFIGURATION for 74F843
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
3
4
5
6
7
8
9
Q7
Q8
10
11
PRE
LE
GND 12
SF01285
LOGIC SYMBOL for 74F843
2
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7 D8
13
14
11
1
LE
PRE
MR
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23 22 21 20 19 18 17 16 15
V
= Pin 24
CC
GND = Pin 12
SF01286
LOGIC SYMBOL (IEEE/IEC) for 74F843
1
EN
11
R
14
S2
13
C1
2
3
23
22
21
20
19
18
17
16
15
1 D
4
5
6
7
8
9
10
SF01287
4
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
PIN CONFIGURATION for 74F845
PIN CONFIGURATION for 74F846
1
24 V
CC
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
OE0
OE1
D0
OE0
OE1
D0
2
3
23
22
21
20
19
18
17
16
15
14
13
OE2
Q0
Q1
Q2
Q3
Q4
Q5
OE2
Q0
Q1
Q2
Q3
Q4
Q5
3
4
4
D1
D1
5
5
D2
D2
6
6
D3
D3
7
7
D4
D4
8
8
D5
D5
9
9
D6
D6
Q6
Q7
Q6
Q7
10
11
10
11
D7
D7
MR
PRE
LE
MR
PRE
LE
GND 12
GND 12
SF01291
SF01294
LOGIC SYMBOL for 74F845
LOGIC SYMBOL for 74F846
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
13
14
11
1
LE
13
14
11
1
LE
PRE
MR
PRE
MR
OE0
OE1
OE2
OE0
OE1
OE2
2
2
23
23
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16 15
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16 15
V
= Pin 24
V
= Pin 24
CC
CC
GND = Pin 12
GND = Pin 12
SF01292
SF01295
LOGIC SYMBOL (IEEE/IEC) for 74F845
LOGIC SYMBOL (IEEE/IEC) for 74F846
1
1
&
&
2
2
EN
EN
23
23
14
S2
14
S2
11
R
11
R
13
C1
13
C1
3
4
22
21
20
19
18
17
16
15
3
4
22
21
20
19
18
17
16
15
1 D
1 D
5
5
6
6
7
7
8
8
9
9
10
10
SF01293A
SF01296A
5
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
LOGIC DIAGRAM for 74F841
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
D9
11
2
3
4
5
6
7
8
9
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
D
Q
Q
Q
Q
Q
Q
Q
Q
L
Q
L
Q
C
13
LE
1
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SF01297
V
= Pin 24
CC
GND = Pin 12
LOGIC DIAGRAM for 74F842
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
D9
11
2
3
4
5
6
7
8
9
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
C
13
LE
1
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SF01298
V
= Pin 24
CC
GND = Pin 12
FUNCTION TABLE for 74F841 and 74F842
OUTPUTS
INPUTS
74F841
74F842
OPERATING MODE
OE
L
LE
H
H
↓
Dn
L
Qn
L
Qn
H
Transparent
Latched
L
H
l
H
L
L
L
H
L
↓
h
H
L
H
L
X
L
X
X
Z
Z
High Impedance
Hold
NC
NC
H = High voltage level
L
h
l
↓
X
=
=
=
=
=
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
NC= No change
High impedance “off” state
Z
=
6
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
LOGIC DIAGRAM for 74F843
D0
2
D1
D2
D3
D4
D5
D6
D7
D8
10
3
4
5
6
7
8
9
14
PRE
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
Q
Q
Q
Q
Q
Q
Q
Q
Q
11
13
MR
LE
1
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
V
= Pin 24
CC
GND = Pin 12
SF01299
FUNCTION TABLE for 74F843
OUTPUTS
INPUTS
74F843
OPERATING MODE
OE
L
PRE
L
MR
X
LE
X
X
H
H
↓
Dn
X
X
L
Qn
H
Preset
Clear
L
H
L
L
L
H
H
H
H
H
X
L
Transparent
Latched
L
H
H
l
H
L
H
L
L
H
↓
h
H
H
L
X
X
L
X
X
Z
High Impedance
Hold
H
H
NC
H = High voltage level
L
h
l
↓
X
=
=
=
=
=
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
NC= No change
High impedance “off” state
Z
=
7
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
LOGIC DIAGRAM for 74F845
D0
3
D1
D2
D3
D4
D5
D6
D7
10
4
5
6
7
8
9
14
PRE
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
Q
Q
Q
Q
Q
Q
Q
Q
11
13
MR
LE
1
OE0
OE1
2
23
OE2
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF01301
V
= Pin 24
CC
GND = Pin 12
LOGIC DIAGRAM for 74F846
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
10
14
PRE
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
D
L
P
C
Q
Q
Q
Q
Q
Q
Q
Q
11
MR
13
LE
1
OE0
2
OE1
23
OE2
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
V
= Pin 24
CC
GND = Pin 12
SF01302
FUNCTION TABLE for 74F845 and 74F846
OUTPUTS
INPUTS
74F845
74F846
OPERATING MODE
OE
L
PRE
L
MR
X
LE
X
X
H
H
↓
Dn
X
X
L
Qn
H
Qn
H
Preset
Clear
L
H
L
L
L
L
H
H
H
H
H
X
L
H
Transparent
Latched
L
H
H
l
H
L
L
H
L
H
L
H
↓
h
H
L
H
L
X
X
L
X
X
Z
Z
High Impedance
Hold
H
H
NC
NC
H = High voltage level
L
h
l
↓
X
=
=
=
=
=
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
NC= No change
High impedance “off” state
Z
=
8
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
84
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–24
48
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
T
amb
Operating free-air temperature range
0
+70
9
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
1
SYMBOL
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
UNIT
2
MIN
2.2
2.2
2.0
2.0
TYP
MAX
±10%V
V
V
CC
I
= –15mA
= –24mA
OH
OH
±5%V
3.3
CC
V
= MIN,
CC
V
OH
V
V
= MAX, V = MIN
IL
IH
±10%V
V
CC
CC
I
±5%V
V
I
I
= 32mA ±10%V
0.38
0.38
0.55
0.55
–1.2
100
20
V
OL
CC
CC
V
CC
= MIN,
V
V
OL
= MAX, V = MIN
IL
IH
= 48mA
±5%V
V
OL
Input clamp voltage
V
CC
= MIN, I = I
IK
–0.73
V
IK
I
I
I
I
Input current at maximum input voltage
High-level input current
V
= 0.0V, V = 7.0V
µA
µA
µA
I
CC
CC
CC
I
V
V
= MAX, V = 2.7V
I
IH
IL
Low-level input current
= MAX, V = 0.5V
–20
I
Off-state output current,
High-level voltage applied
I
V
= MAX, V = 2.7V
50
µA
µA
OZH
CC
CC
O
Off-state output current,
Low-level voltage applied
I
I
V
= MAX, V = 0.5V
–50
OZL
O
3
Short-circuit output current
V
= MAX
= MAX
–100
–225
65
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OS
CC
I
50
60
70
40
65
60
65
75
85
50
70
70
CCH
I
80
74F841
74F842
V
CC
CCL
CCZ
CCH
I
92
I
60
I
90
V
CC
V
CC
V
CC
= MAX
= MAX
= MAX
CCL
CCZ
CCH
I
90
Supply current
(total)
I
CC
I
90
74F843
74F845
I
100
115
70
CCL
CCZ
CCH
I
I
I
95
74F846
CCL
I
95
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, I tests should be performed last.
OS
10
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC ELECTRICAL CHARACTERISTICS for 74F841/74F842
LIMITS
T
= +25°C
T
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
2.0
2.5
4.0
4.5
7.5
7.5
2.0
2.5
8.0
8.0
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
ns
ns
ns
ns
ns
ns
74F841
74F842
t
t
Propagation delay
LE to Qn
4.5
4.0
6.5
6.0
9.5
9.0
4.0
3.5
10.0
9.5
PLH
PHL
t
t
Propagation delay
Dn to Qn
3.5
3.0
5.5
5.0
8.5
8.0
4.5
4.0
9.0
8.5
PLH
PHL
t
t
Propagation delay
LE to Qn
5.0
4.5
7.0
6.5
10.0
9.0
3.0
3.0
10.5
9.5
PLH
PHL
t
t
Output enable time
High or Low-level OEn to Qn or Qn
Waveform 5
Waveform 6
2.5
4.0
4.5
6.0
8.0
9.5
2.0
3.0
8.5
10.5
PZH
PZL
t
t
Output disable time
High or Low-level OEn to Qn or Qn
Waveform 5
Waveform 6
1.0
1.0
4.5
5.0
8.0
8.0
1.0
1.0
8.5
8.5
PHZ
PLZ
AC SETUP REQUIREMENTS for 74F841/74F842
LIMITS
T
T
= +25°C
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to LE
0.0
0.0
1.0
1.0
s
Waveform 4
ns
t (H)
t (L)
h
Hold time, High or Low
Dn to LE
2.5
3.0
3.0
4.0
h
Waveform 4
Waveform 4
Waveform 4
Waveform 4
ns
ns
ns
ns
74F841
74F842
t (H)
w
LE pulse width, High
3.5
4.0
t (H)
Hold time, High or Low
Dn to LE
3.0
3.5
3.5
4.5
h
t (L)
h
t (H)
w
LE pulse width, High
3.0
3.0
11
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC ELECTRICAL CHARACTERISTICS for 74F843/74F845
LIMITS
T
= +25°C
T
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
2.0
2.5
4.5
4.5
7.5
8.0
2.0
2.5
8.5
8.5
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 3
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
LE to Qn
4.5
4.0
6.5
6.0
9.5
8.5
4.5
4.0
10.0
8.5
PLH
PHL
Propagation delay
PRE to Qn
t
t
3.5
2.0
5.5
4.5
8.5
7.5
3.0
2.0
9.0
8.0
PLH
Propagation delay
MR to Qn
Waveform 3
PHL
t
t
Output enable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
2.5
4.0
4.5
6.0
7.5
9.5
2.0
3.0
8.0
10.5
PZH
PZL
t
t
Output disable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
1.0
1.0
4.5
5.0
8.0
8.0
1.0
1.0
8.5
8.5
PHZ
PLZ
AC SETUP REQUIREMENTS for 74F843/74F845
LIMITS
T
T
= +25°C
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to LE
1.0
1.0
0.0
0.0
s
Waveform 4
Waveform 4
ns
ns
t (H)
Hold time, High or Low
Dn to LE
3.0
4.0
3.0
4.0
h
t (L)
h
t (H)
LE pulse width, High
PRE pulse width, Low
MR pulse width, Low
PRE recovery time
MR recovery time
Waveform 4
Waveform 3
Waveform 3
Waveform 3
Waveform 3
3.0
4.0
4.0
0.0
3.5
3.0
5.0
5.0
0.0
4.5
ns
ns
ns
ns
ns
w
t (L)
w
t (H)
w
t
t
REC
REC
12
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC ELECTRICAL CHARACTERISTICS for 74F846
LIMITS
T
= +25°C
T
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
3.5
3.0
5.5
5.0
8.5
8.0
3.0
3.0
9.5
8.5
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 3
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
LE to Qn
5.0
4.5
7.0
6.5
10.0
9.0
5.0
4.5
10.5
9.5
PLH
PHL
Propagation delay
PRE to Qn
t
t
3.5
5.0
5.5
7.0
8.5
3.0
4.5
9.5
PLH
Propagation delay
MR to Qn
Waveform 3
10.0
10.5
PHL
t
t
Output enable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
2.5
4.0
5.0
6.0
7.5
9.5
2.0
3.0
8.0
10.5
PZH
PZL
t
t
Output disable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
1.0
1.0
4.5
5.0
8.0
8.0
1.0
1.0
8.5
8.5
PHZ
PLZ
AC SETUP REQUIREMENTS for 74F846
LIMITS
T
T
= +25°C
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to LE
0.0
0.0
0.0
0.0
s
Waveform 4
Waveform 4
ns
ns
t (H)
Hold time, High or Low
Dn to LE
3.0
4.0
3.0
4.0
h
t (L)
h
t (H)
LE pulse width, High
PRE pulse width, Low
MR pulse width, Low
PRE recovery time
MR recovery time
Waveform 4
Waveform 3
Waveform 3
Waveform 3
Waveform 3
3.0
4.0
4.0
0.0
3.5
3.0
5.0
5.0
0.0
4.5
ns
ns
ns
ns
ns
w
t (L)
w
t (H)
w
t
t
REC
REC
13
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn, LE
V
V
M
M
Dn, LE
V
V
M
M
t
t
PHL
PLH
t
t
PLH
PHL
Qn
V
V
M
M
Qn
V
V
M
M
SF01303
SF01304
Waveform 1. Propagation Delay, Non-Inverting Path
Waveform 2. Propagation Delay, Inverting Path
t
(L)
w
PRE,
MR
Dn
LE
V
V
V
V
V
V
M
M
M
M
M
M
t (H)
t
(H)
t (L)
t (L)
h
s
h
s
t
REC
LE
Qn, Qn
Qn, Qn
V
M
V
V
V
M
M
M
t
(H)
w
SF01306
t
t
PLH
V
V
Waveform 4. Data Setup and Hold Times
M
M
PHL
SF01305
Waveform 3. Master Reset and Preset Pulse Width,
Master Reset and Preset to Output Delay,
and Master Reset and Preset to Latch Enable Recovery Time
OEn
OEn
V
V
M
V
t
V
M
M
M
V
-0.3V
0V
OH
t
t
PHZ
t
PZH
PZL
PLZ
3.5V
Qn, Qn
V
V
M
M
Qn, Qn
V
+0.3V
OL
SF00509
SF00510
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable time from Low Level
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
14
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
0V
7.0V
90%
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00777
15
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
16
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
17
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-99
Document order number:
9397 750 06143
Philips
Semiconductors
相关型号:
74F843DC
IC F/FAST SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24, Bus Driver/Transceiver
NSC
74F843PC
IC F/FAST SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24, Bus Driver/Transceiver
NSC
74F843QC
Bus Driver, F/FAST Series, 1-Func, 9-Bit, True Output, TTL, PQCC28, PLASTIC, CC-28
FAIRCHILD
74F843SCQR
Bus Driver, F/FAST Series, 1-Func, 9-Bit, True Output, TTL, PDSO24, 0.150 INCH, SOIC-24
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明