74HC165BQ-Q100 [NXP]
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC16, 2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT763-1, DHVQFN-16;
| 型号： | 74HC165BQ-Q100 |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC16, 2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT763-1, DHVQFN-16 输出元件 |
| 文件： | 总21页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Rev. 1 — 17 July 2012
Product data sheet
1. General description
The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC165-Q100; 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers
with complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Parallel-to-serial data conversion
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC165D-Q100
40 C to +125 C
40 C to +125 C
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width SOT109-1
3.9 mm
74HCT165D-Q100
74HC165PW-Q100
74HCT165PW-Q100
74HC165BQ-Q100
74HCT165BQ-Q100
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
5. Functional diagram
SRG8
1
C2[LOAD]
G1[SHIFT]
15
≥ 1
10
C3/
1
2
DS
11
D0
10
11
12
13
14
3
3D
2D
2D
12
D1
13
D2
14
D3
3
D4
4
D5
5
9
7
D6
D7
PL
Q7
Q7
4
6
1
5
9
7
CP CE
15
6
2
mna985
mna986
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
2 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1
PL
10 DS
Q7
Q7
9
7
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
2
CP
15 CE
mna992
Fig 3. Functional diagram
6. Pinning information
6.1 Pinning
74HC165-Q100
74HCT165-Q100
74HC165-Q100
74HCT165-Q100
terminal 1
index area
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PL
CP
V
CC
CE
D3
D2
D1
D0
DS
Q7
2
15
14
13
12
11
10
CP
CE
D3
D2
D1
D0
DS
D4
3
4
5
6
7
D4
D5
D6
D7
Q7
D5
D6
(1)
GND
D7
Q7
aaa-003156
GND
Transparent top view
aaa-003155
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration SO16 and TSSOP16
Fig 5. Pin configuration DHVQFN16
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
3 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
6.2 Pin description
Table 2.
Symbol
PL
Pin description
Pin
Description
1
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
CP
2
Q7
7
GND
Q7
8
9
serial output from the last stage
serial data input
DS
10
D0 to D7
CE
11, 12, 13, 14, 3, 4, 5, 6
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
15
16
VCC
7. Functional description
Table 3.
Function table[1]
Operating modes Inputs
PL
Qn registers
D0 to D7 Q0
Outputs
CE
X
X
L
CP
X
X
DS
X
X
l
Q1 to Q6 Q7
Q7
H
parallel load
L
L
L
L to L
L
L
H
X
X
X
X
X
X
H
L
H to H
H
L
serial shift
H
H
H
H
H
H
q0 to q5 q6
q0 to q5 q6
q0 to q5 q6
q0 to q5 q6
q1 to q6 q7
q1 to q6 q7
q6
q6
q6
q6
q7
q7
L
h
H
L
L
l
L
h
H
q0
q0
hold “do nothing”
H
X
X
H
X
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
4 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
serial shift
mna993
load
Fig 6. Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
5 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC165-Q100
74HCT165-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
-
40
-
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
74HC165-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
1.2
-
1.5
-
-
-
1.5
-
-
-
V
V
V
V
V
V
3.15 2.4
-
3.15
3.15
4.2
3.2
0.8
2.1
2.8
-
4.2
4.2
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
-
-
-
0.5
1.35
1.8
1.35
1.8
VOH
HIGH-level
output voltage
IO = 20 A; VCC = 2.0 V 1.9
IO = 20 A; VCC = 4.5 V 4.4
IO = 20 A; VCC = 6.0 V 5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
4.4
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
0.1
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
6 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT165-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
±1
V
0.16 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
additional
supply current VI = VCC 2.1 V;
other inputs at VCC or GND;
per input pin;
VCC = 4.5 V to 5.5 V
Dn and DS inputs
-
-
-
35
65
3.5
126
234
-
-
-
-
157.5
292.5
-
-
-
-
171.5
318.5
-
A
A
pF
CP CE, and PL inputs
CI
input
capacitance
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
7 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
74HC165-Q100
[1]
tpd
propagation
delay
CP or CE to Q7, Q7;
see Figure 7
VCC = 2.0 V
-
-
-
-
52
19
15
16
165
33
28
-
-
-
-
-
205
-
-
-
-
250
ns
ns
ns
ns
VCC = 4.5 V
41
35
-
50
43
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Figure 8
VCC = 2.0 V
-
-
-
-
50
18
14
15
165
33
28
-
-
-
-
-
205
41
35
-
-
-
-
-
250
50
43
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Figure 9
VCC = 2.0 V
-
-
-
-
36
13
10
11
120
24
20
-
-
-
-
-
150
30
26
-
-
-
-
-
180
36
31
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
Q7, Q7 output; see Figure 7
VCC = 2.0 V
[2]
tt
transition
time
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
PL input LOW; see Figure 8
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
trec
recovery time PL to CP, CE; see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100 22
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
20
17
8
6
21
26
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
8 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
tsu
set-up time
DS to CP, CE; see Figure 10
VCC = 2.0 V
80
16
14
11
4
-
-
-
100
-
-
-
120
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
24
20
VCC = 6.0 V
3
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
Dn to PL; see Figure 11
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
5
5
5
6
2
2
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
5
5
5
17
6
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
5
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
6
17
51
61
56
35
-
-
-
-
-
5
-
-
-
-
-
4
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
30
35
-
24
28
-
20
24
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
-
-
dissipation
capacitance
VI = GND to VCC
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
9 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
74HCT165-Q100
[1]
tpd
propagation
delay
CE, CP to Q7, Q7;
see Figure 7
VCC = 4.5 V
-
-
17
14
34
-
-
-
43
-
-
51
ns
ns
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Figure 8
VCC = 4.5 V
-
-
-
-
20
17
40
-
-
-
50
-
-
-
60
-
ns
ns
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Figure 9
VCC = 4.5 V
-
-
14
11
28
-
-
-
35
-
-
-
42
-
ns
ns
VCC = 5.0 V; CL = 15 pF
Q7, Q7 output; see Figure 7
VCC = 4.5 V
[2]
tt
transition
time
-
7
6
9
8
2
15
-
-
19
-
-
22
-
ns
ns
ns
ns
ns
tW
pulse width
CP input; see Figure 7
VCC = 4.5 V
16
20
20
20
20
25
25
25
24
30
30
30
PL input; see Figure 8
VCC = 4.5 V
-
-
-
trec
recovery time PL to CP, CE; see Figure 8
VCC = 4.5 V
-
-
-
tsu
set-up time
DS to CP, CE; see Figure 10
VCC = 4.5 V
-
-
-
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V
20
20
7
-
-
25
25
-
-
30
30
-
-
ns
ns
Dn to PL; see Figure 11
VCC = 4.5 V
10
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
VCC = 4.5 V
7
0
1
7
-
-
9
0
-
-
11
0
-
-
ns
ns
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 4.5 V
26
-
44
48
-
-
21
-
-
-
17
-
-
-
MHz
MHz
VCC = 5.0 V; CL = 15 pF
74HC_HCT165_Q100
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Product data sheet
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74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
[3]
CPD
power
per package;
-
35
-
-
-
-
-
pF
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
1/f
max
V
I
CP or CE input
V
M
t
GND
t
W
t
PHL
PLH
V
OH
90 %
90 %
V
M
Q7 or Q7 output
10 %
10 %
TLH
V
OL
t
t
THL
mna987
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width, maximum
clock frequency and output transition times
74HC_HCT165_Q100
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Product data sheet
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74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
V
I
V
M
PL input
GND
t
t
rec
W
V
I
CE, CP input
V
M
GND
t
PHL
V
OH
V
Q7 or Q7 output
M
V
OL
mna988
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 8. Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock
(CP) and clock enable (CE) recovery time
V
I
V
D7 input
M
GND
t
t
t
t
PLH
PHL
PHL
PLH
V
OH
V
V
Q7 output
Q7 output
M
M
V
OL
V
OH
V
OL
mna989
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 9. Data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
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74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
(1)
V
I
V
M
CP, CE input
GND
t
t
h
h
t
t
su
su
V
I
V
DS input
M
GND
t
su
t
V
I
W
V
CP, CE input
M
GND
mna990
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
(1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1.
Fig 10. Waveforms showing set-up and hold times
V
I
V
V
M
Dn input
GND
M
t
t
t
t
h
su
h
su
V
I
PL input
GND
V
V
M
M
mna991
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8.
Type
Measurement points
Input
Output
VM
VI
VM
74HC165-Q100
74HCT165-Q100
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT165_Q100
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Product data sheet
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NXP Semiconductors
8-bit parallel-in/serial out shift register
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC165-Q100
74HCT165-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
14 of 21
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NXP Semiconductors
8-bit parallel-in/serial out shift register
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 13. Package outline SOT109-1 (SO16)
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
15 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
16 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 15. Package outline SOT763-1 (DHVQFN16)
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
17 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
TTL
Transistor-Transistor Logic
Military
MIL
15. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT165_Q100 v.1 20120717
Product data sheet
-
-
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
18 of 21
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NXP Semiconductors
8-bit parallel-in/serial out shift register
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
16.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
19 of 21
74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT165_Q100
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Product data sheet
Rev. 1 — 17 July 2012
20 of 21
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NXP Semiconductors
8-bit parallel-in/serial out shift register
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 July 2012
Document identifier: 74HC_HCT165_Q100
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