74HC165PW [NXP]
8-bit parallel-in/serial-out shift register; 8位并行输入/串行输出移位寄存器型号: | 74HC165PW |
厂家: | NXP |
描述: | 8-bit parallel-in/serial-out shift register |
文件: | 总10页 (文件大小:77K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT165
8-bit parallel-in/serial-out shift
register
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
When PL is HIGH, data enters the register serially at the
Ds input and shifts one place to the right
(Q0 → Q1 → Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q7 output to the DS input of the
succeeding stage.
FEATURES
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• ICC category: MSI
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q7 and
Q7) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D0 to
APPLICATIONS
D7 inputs are loaded into the register asynchronously.
• Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
CP to Q7, Q7
PL to Q7, Q7
D7 to Q7, Q7
16
15
11
14
17
11
ns
ns
ns
fmax
CI
maximum clock frequency
input capacitance
56
3.5
35
48
3.5
35
MHz
pF
CPD
power dissipation capacitance per
package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
PL
asynchronous parallel load input (active LOW)
complementary output from the last stage
serial output from the last stage
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
7
Q7
9
Q7
2
CP
8
GND
Ds
10
serial data input
11, 12, 13, 14, 3, 4, 5, 6
D0 to D7
CE
parallel data inputs
15
16
clock enable input (active LOW)
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES
INPUTS
CP
Qn REGISTERS
OUTPUTS
Q7 Q7
PL
CE
DS
D0-D7
Q0
Q1-Q6
parallel load
serial shift
L
L
X
X
X
X
X
X
L
H
L
H
L - L
H - H
L
H
H
L
H
H
L
L
↑
↑
l
h
X
X
L
H
q0-q5
q0-q5
q6
q6
q6
q6
hold “do nothing”
H
H
X
X
X
q0
q1-q6
q7
q7
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CE, CP to Q7, Q7
52
19
15
165
33
28
205
41
35
250
50
43
ns
2.0
4.5
6.0
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
t
t
t
PHL/ tPLH propagation delay
PL to Q7, Q7
50
18
14
165
33
28
205
41
35
250
50
43
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
PHL/ tPLH propagation delay
D7 to Q7, Q7
36
13
10
120
24
20
150
30
26
180
36
31
2.0
4.5
6.0
THL/ tTLH output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0
4.5
6.0
tW
parallel load pulse
width; LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0
4.5
6.0
trem
tsu
tsu
tsu
removal time
PL to CP, CE
100 22
125
25
21
150
30
26
2.0
4.5
6.0
20
17
8
6
set-up time
Ds to CP, CE
80
16
14
11
4
3
100
20
17
120
24
20
2.0
4.5
6.0
set-up time
CE to CP;
CP to CE
80
16
14
17
6
5
100
20
17
120
24
20
2.0
4.5
6.0
set-up time
Dn to PL
80
16
14
22
8
6
100
20
17
120
24
20
2.0
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
th
hold time
Ds to CP, CE
Dn to PL
5
5
5
6
2
2
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.6
Fig.6
Fig.6
th
hold time
CE to CP
CP to CE
5
5
5
−17
−6
−5
5
5
5
5
5
5
ns
2.0
4.5
6.0
fmax
maximum clock
pulse frequency
6
30
35
17
51
61
5
24
28
4
20
24
MHz
2.0
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
Ds
CP
CE
PL
0.35
0.35
0.65
0.65
0.65
December 1990
7
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CE, CP to Q7, Q7
17
20
14
7
34
40
28
15
43
50
35
19
51
60
42
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
t
PHL/ tPLH propagation delay
PL to Q7, Q7
t
PHL/ tPLH propagation delay
D7 to Q7, Q7
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
16
20
20
20
20
20
7
6
20
25
25
25
25
25
9
24
30
30
30
30
30
11
0
tW
parallel load pulse
width; LOW
9
trem
tsu
tsu
tsu
th
removal time
PL to CP, CE
8
set-up time
Ds to CP, CE
2
set-up time
CE to CP; CP to CE
7
set-up time
Dn to PL
10
−1
−7
44
hold time
Ds to CP, CE; Dn to PL
th
hold time
0
0
CE to CP, CP to CE
fmax
maximum clock pulse
frequency
26
21
17
MHz 4.5 Fig.6
December 1990
8
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
AC WAVEFORMS
The changing to output assumes internal Q6
opposite state from Q7.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Q7 or Q7) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
The changing to output assumes internal Q6
opposite state from Q7.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation
delays, the parallel load to clock (CP) and clock enable (CE) removal time.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW.
December 1990
9
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
CE may change only from HIGH-to-LOW while CP
is LOW.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds) to the clock (CP) and clock
enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP)
to the clock enable input (CE).
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the set-up and hold times from the data inputs (Dn) to the parallel load input (PL).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
10
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