74HC193NB [NXP]
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16;
| 型号： | 74HC193NB |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16 计数器 |
| 文件： | 总30页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 4 — 24 June 2013
Product data sheet
1. General description
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time to guarantee predictable behaviour. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added
for each stage that is added. The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input will disable the parallel load gates, override both clock inputs
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC
.
2. Features and benefits
Input levels:
For 74HC193: CMOS level
For 74HCT193: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74HC193D
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT338-1
74HC193DB
40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74HC193N
40 C to +125 C DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HC193PW
40 C to +125 C TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT193D
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT338-1
74HCT193DB
40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74HCT193N
40 C to +125 C DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT193PW
40 C to +125 C TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Functional diagram
15
D0
1
10
D2
9
D1
D3
PL
TCU
TCD
11
5
PL
11
D0
15
D1
1
D2
10
D3
9
12
13
CPU
CPD
COUNTER
4
CPU
CPD
5
4
12
13
TCU
TCD
MR
14
FLIP-FLOPS
Q0 Q1 Q2
14
3
2
6
7
Q3
MR Q0
Q1
Q2
Q3 001aag409
3
2
6
7
001aag405
Fig 1. Functional diagram
Fig 2. Logic symbol
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
2 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
CTR4
11
5
C3
2+
G1
1−
4
G2
14
R
15
1
3
2
6
7
3D
10
9
13
2CT = 0
12
1CT = 15
001aag410
Fig 3. IEC logic symbol
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
3 of 30
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
D0
D1
D2
D3
PL
CPU
TCU
SD
SD
SD
SD
Q
Q
Q
Q
T
FF1
T
FF2
T
FF3
T
FF4
Q
Q
Q
Q
RD
RD
RD
RD
TCD
CPD
MR
Q0
Q1
Q2
Q3
001aag412
Fig 4. Logic diagram
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
74HC193
74HCT193
74HC193
74HCT193
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
Q1
V
CC
D1
Q1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
74HC193
74HCT193
D0
D0
Q0
MR
TCD
TCU
PL
Q0
MR
TCD
TCU
PL
1
2
3
4
5
6
7
8
16
15
14
13
D1
Q1
V
CC
CPD
CPU
Q2
D0
CPD
CPU
Q2
Q0
MR
TCD
CPD
CPU
Q2
12 TCU
11
10
9
PL
D2
D3
Q3
D2
Q3
D2
Q3
GND
D3
GND
D3
GND
001aaf408
001aag406
001aag407
Fig 5. Pin configuration SO16
Fig 6. Pin configuration TSSOP16
and SSOP16
Fig 7. Pin configuration DIP16
5.2 Pin description
Table 2.
Symbol
D0
Pin description
Pin
Description
15
1
data input 0
D1
data input 1
D2
10
9
data input 2
D3
data input 3
Q0
3
flip-flop output 0
flip-flop output 1
flip-flop output 2
flip-flop output 3
count down clock input[1]
count up clock input[1]
ground (0 V)
Q1
2
Q2
6
Q3
7
CPD
CPU
GND
PL
4
5
8
11
12
13
14
16
asynchronous parallel load input (active LOW)
terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)
asynchronous master reset input (active HIGH)
supply voltage
TCU
TCD
MR
VCC
[1] LOW-to-HIGH, edge triggered.
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
5 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
6. Functional description
Table 3.
Function table[1]
Operating mode
Inputs
Outputs
MR PL
CPU CPD D0
D1
X
X
L
D2
X
X
L
D3
X
X
L
Q0
L
Q1
L
Q2
L
Q3
L
TCU TCD
Reset (clear)
H
H
L
L
L
L
L
L
X
X
L
X
X
X
X
L
L
X
X
L
H
L
H
L
L
L
L
L
H
H
L
Parallel load
L
L
L
L
H
L
H
X
X
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H[3]
L
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
H
H
H
H
H
H
L
L
H
H
H
H[2]
Count up
H
H
count up
Count down
count down
H
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH clock transition.
[2] TCU = CPU at terminal count up (HHHH)
[3] TCD = CPD at terminal count down (LLLL).
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
6 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
(1)
MR
PL
D0
D1
D2
D3
(2)
CPU
(2)
CPD
Q0
Q1
Q2
Q3
TCU
TCD
0
CLEAR PRESET
(1) Clear overrides load, data and count inputs.
13
14
15
0
1
2
1
0
15
14
13
COUNT UP
COUNT DOWN
001aag411
(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input
(CPU) must be HIGH.
Sequence
Clear (reset outputs to zero);
load (preset) to binary thirteen;
count up to fourteen, fifteen, terminal count up, zero, one and two;
count down to one, zero, terminal count down, fifteen, fourteen and thirteen.
Fig 8. Typical clear, load and count sequence
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
7 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
20
20
25
50
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to VCC + 0.5 V
-
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
50
+150
750
500
500
500
storage temperature
total power dissipation
65
[2]
[2]
[2]
[2]
DIP16 package
SO16 package
-
-
-
-
mW
mW
mW
mW
SSOP16 package
TSSOP16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 packages: above 70 C the value of Ptot derates linearly at 12 mW/K.
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
74HC193
Conditions
Min Typ Max Unit
VCC
VI
supply voltage
input voltage
2.0
5.0
6.0
V
V
V
0
-
-
VCC
VCC
VO
output voltage
ambient temperature
0
Tamb
t/V
40
+25 +125 C
input transition rise and
fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
625
ns/V
ns/V
ns/V
1.67 139
-
83
74HCT193
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
V
V
input voltage
-
-
VCC
VCC
VO
output voltage
0
Tamb
t/V
ambient temperature
40
-
+25 +125 C
input transition rise and
fall rate
VCC = 4.5 V
1.67 139
ns/V
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
8 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
9. Static characteristics
Table 6.
Static characteristics type 74HC193
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 C
VIH
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
3.15
4.2
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
V
V
V
V
V
V
-
-
VIL
LOW-level input voltage
0.5
-
1.35
-
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
-
-
-
-
-
-
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
V
V
V
V
V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VIH or VIL
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
0.26
0.1
8.0
V
0.16
V
II
input leakage current
supply current
-
-
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
Ci
input capacitance
-
3.5
-
pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
3.15
-
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
4.4
5.9
3.84
5.34
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
9 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 6.
Static characteristics type 74HC193 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
0.1
V
0.33
0.33
1.0
80
V
V
II
input leakage current
supply current
A
A
ICC
VCC = 6.0 V
Tamb = 40 C to +125 C
VIH HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
3.15
-
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VIH or VIL
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
160
V
V
V
V
V
II
input leakage current
supply current
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
Table 7.
Static characteristics type 74HCT193
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 C
VIH
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
V
V
VIL
0.8
VOH
HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
V
V
IO = 4.0 mA
3.98
4.32
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
10 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 7.
Static characteristics type 74HCT193 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
-
0
0.1
V
IO = 4.0 mA
0.15
0.26
0.1
8.0
V
II
input leakage current
supply current
VI = VCC or GND; VCC = 5.5 V
-
-
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
additional supply current
per input pin; VI = VCC 2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
-
-
-
35
126
504
234
378
-
A
A
A
A
pF
pins CPU, CPD
pin PL
140
65
pin MR
105
3.5
Ci
input capacitance
Tamb = 40 C to +85 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
VOH
HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
-
-
-
-
V
V
IO = 4.0 mA
3.84
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
-
-
-
-
-
0.1
V
IO = 4.0 mA
0.33
1.0
80
V
II
input leakage current
supply current
VI = VCC or GND; VCC = 5.5 V
A
A
ICC
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
additional supply current
per input pin; VI = VCC 2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
-
-
-
-
-
-
157.5
630
A
A
A
A
pins CPU, CPD
pin PL
292.5
472.5
pin MR
Tamb = 40 C to +125 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
VOH
HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
3.7
-
-
-
-
V
V
IO = 4.0 mA
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
-
0.1
0.4
V
V
IO = 4.0 mA
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
11 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 7.
Static characteristics type 74HCT193 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
1.0
160
Unit
A
II
input leakage current
supply current
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
ICC
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
A
ICC
additional supply current
per input pin; VI = VCC 2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
-
-
-
-
-
-
171.5
686
A
A
A
A
pins CPU, CPD
pin PL
318.5
514.5
pin MR
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
12 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristics
Table 8.
Dynamic characteristics type 74HC193
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
[1]
tpd
propagation
delay
CPU, CPD to Qn;
see Figure 9
-
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
63
23
18
215
43
-
-
-
270
54
-
-
-
325
65
ns
ns
ns
37
46
55
CPU to TCU; see
Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
39
14
11
125
25
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
21
26
32
CPD to TCD; see
Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
39
14
11
125
25
-
-
-
155
31
-
-
-
190
38
ns
ns
ns
21
26
32
PL to Qn; see
Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
69
25
20
220
44
-
-
-
275
55
-
-
-
330
66
ns
ns
ns
37
47
56
MR to Qn; see
Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
58
21
17
200
40
-
-
250
50
-
-
-
300
60
ns
ns
ns
34
43
51
Dn to Qn; see
Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
69
25
20
210
42
-
-
-
265
53
-
-
-
315
63
ns
ns
ns
36
45
54
PL to TCU, PL to
TCD; see Figure 14
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
80
29
23
290
58
-
-
-
365
73
-
-
-
435
87
ns
ns
ns
49
62
74
MR to TCU, MR to
TCD; see Figure 14
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
74
27
22
285
57
-
-
-
355
71
-
-
-
430
86
ns
ns
ns
48
60
73
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
13 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 8.
Dynamic characteristics type 74HC193 …continued
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
tpd
propagation
delay
Dn to TCU, Dn to
TCD; see Figure 14
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
80
29
23
290
58
-
-
-
365
73
-
-
-
435
87
ns
ns
ns
49
62
74
tTHL
tTLH
tW
HIGH to LOW
output transition
time
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
6
19
LOW to HIGH
output transition
time
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
6
19
pulse width
CPU, CPD (HIGH
or LOW); see
Figure 9
VCC = 2.0 V
VCC = 4.5 V
100
20
22
8
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 6.0 V
17
6
21
26
MR (HIGH); see
Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
25
9
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
17
7
21
26
PL (LOW); see
Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
19
7
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
17
6
21
26
trec
recovery time
PL to CPU, CPD;
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
8
3
2
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
MR to CPU, CPD;
see Figure 12
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
50
10
9
0
0
0
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
14 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 8.
Dynamic characteristics type 74HC193 …continued
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
tsu
set-up time
Dn to PL; see
Figure 13; note:
CPU = CPD =
HIGH
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
th
hold time
Dn to PL; see
Figure 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
14
5
-
-
-
0
0
0
-
-
0
0
0
-
-
-
ns
ns
ns
4
CPU to CPD,
CPD to CPU; see
Figure 15
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
8
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
fmax
maximum
frequency
CPU, CPD; see
Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
4.0
20
24
-
13.5
41
-
-
-
-
3.2
16
19
-
-
-
-
-
2.6
13
15
-
-
-
-
-
MHz
MHz
MHz
pF
49
[2]
CPD
power
VI = GND to VCC
VCC = 5 V;
;
24
dissipation
capacitance
fi = 1 MHz
[1] tpd is the same as tPHL and tPLH
.
[2]
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
15 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 9.
Dynamic characteristics type 74HCT193
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
43
27
27
46
40
46
55
55
Min
Max
54
34
34
58
50
58
69
69
Min
Max
65
41
41
69
60
69
83
83
[1]
tpd
propagation
delay
CPU, CPD to Qn;
see Figure 9
VCC = 4.5 V
-
-
-
-
-
-
-
-
23
15
15
26
22
27
31
29
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CPU to TCU; see
Figure 10
VCC = 4.5 V
CPD to TCD; see
Figure 10
VCC = 4.5 V
PL to Qn; see
Figure 11
VCC = 4.5 V
MR to Qn; see
Figure 12
VCC = 4.5 V
Dn to Qn; see
Figure 11
VCC = 4.5 V
PL to TCU, PL to
TCD; see Figure 14
VCC = 4.5 V
MR to TCU, MR to
TCD; see Figure 14
VCC = 4.5 V
Dn to TCU, Dn to
TCD; see Figure 14
VCC = 4.5 V
see Figure 12
VCC = 4.5 V
-
-
32
7
58
15
-
-
73
19
-
-
87
22
ns
ns
tTHL
tTLH
tW
HIGH to LOW
output transition
time
LOW to HIGH
output transition
time
see Figure 12
VCC = 4.5 V
-
7
15
-
19
-
22
ns
pulse width
CPU, CPD (HIGH
or LOW); see
Figure 9
VCC = 4.5 V
25
20
20
11
7
-
-
-
31
25
25
-
-
-
38
30
30
-
-
-
ns
ns
ns
MR (HIGH); see
Figure 12
VCC = 4.5 V
PL (LOW); see
Figure 11
VCC = 4.5 V
8
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
16 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 9.
Dynamic characteristics type 74HCT193 …continued
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
10
Typ
Max
Min
Max
Min
Max
trec
recovery time
PL to CPU, CPD;
see Figure 11
VCC = 4.5 V
2
0
-
-
13
-
-
15
-
-
ns
ns
MR to CPU, CPD;
see Figure 12
VCC = 4.5 V
10
13
15
tsu
set-up time
hold time
Dn to PL; see
Figure 13; note:
CPU = CPD =
HIGH
VCC = 4.5 V
16
0
8
-
-
20
0
-
-
24
0
-
-
ns
ns
th
Dn to PL; see
Figure 13
VCC = 4.5 V
6
CPU to CPD,
CPD to CPU; see
Figure 15
VCC = 4.5 V
16
7
-
20
-
24
-
ns
fmax
maximum
frequency
CPU, CPD; see
Figure 9
VCC = 4.5 V
20
-
43
26
-
-
16
-
-
-
13
-
-
-
MHz
pF
[2]
CPD
power
VI = GND to VCC
1.5 V; VCC = 5 V;
fi = 1 MHz
dissipation
capacitance
[1] tpd is the same as tPHL and tPLH
.
[2] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT193
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Product data sheet
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17 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
11. Waveforms
1/f
max
V
I
CPU, CPD
input
V
t
M
GND
t
W
t
PHL
PLH
V
OH
V
Qn output
M
001aag413
V
OL
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
V
I
CPU, CPD
input
V
M
GND
t
t
PHL
PLH
V
OH
TCU, TCD
output
V
M
V
001aag414
OL
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
18 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
V
I
Dn input
V
V
M
GND
V
I
PL input
GND
M
t
rec
t
W
V
I
CPU, CPD
input
V
M
GND
t
t
PHL
PLH
V
OH
Qn output
V
M
V
OL
001aag415
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
V
I
MR input
V
M
GND
t
t
rec
W
V
I
CPU, CPD
input
V
M
GND
t
PHL
V
OH
90 %
V
M
Qn output
10 %
V
OL
t
t
THL
TLH
001aag416
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and
output transition times
74HC_HCT193
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
19 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
V
I
V
Dn input
PL input
M
GND
t
t
su
su
t
t
h
h
V
I
V
M
GND
V
OH
Qn output
V
OL
001aag417
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 10.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times
V
I
PL, MR, Dn
input
V
M
GND
t
t
PLH
PHL
V
OH
TCU, TCD
output
V
M
V
OL
001aag418
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd
.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU, TCD) propagation delays
V
I
CPU or CPD
input
V
M
GND
t
h
V
I
CPD or CPU
input
V
M
GND
001aag419
Measurement points are given in Table 10.
Fig 15. The CPU to CPD or CPD to CPU hold times
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
20 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 10. Measurement points
Type
Input
VM
Output
VM
VI
GND to VCC
GND to 3 V
74HC193
0.5 VCC
1.3 V
0.5 VCC
74HCT193
1.3 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 16. Load circuitry for measuring switching times
Table 11. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC193
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT193
open
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
21 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
12. Application information
data input
D0 D1 D2 D3
CPU TCU
CPD IC1 TCD
PL MR
Q0 Q1 Q2 Q3
D0 D1 D2 D3
CPU TCU
CPD IC2 TCD
PL MR
Q0 Q1 Q2 Q3
up clock
carry
down clock
borrow
asynchronous
parallel load
reset
data output
001aag420
Fig 17. Application for cascaded up/down counter with parallel load
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
22 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 18. Package outline SOT109-1 (SO16)
74HC_HCT193
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Product data sheet
Rev. 4 — 24 June 2013
23 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 19. Package outline SOT338-1 (SSOP16)
74HC_HCT193
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
24 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 20. Package outline SOT38-4 (DIP16)
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
25 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 21. Package outline SOT403-1 (TSSOP16)
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
26 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
14. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 13. Revision history
Document ID
Release date
20130624
Data sheet status
Change notice
Supersedes
74HC_HCT193 v.4
Modifications:
Product data sheet
-
74HC_HCT193 v.3
• General description updated.
20070523 Product data sheet
74HC_HCT193 v.3
Modifications:
-
74HC_HCT193_CNV v.2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Family specification included
74HC_HCT193_CNV v.2 19970828
Product specification
-
-
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
27 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
28 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
29 of 30
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information. . . . . . . . . . . . . . . . . . 22
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 29
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 June 2013
Document identifier: 74HC_HCT193
相关型号：
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74HC(T)193-Q100 - Presettable synchronous 4-bit binary up/down counter TSSOP 16-Pin
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IC HC/UH SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, MINI, PLASTIC, SO-16, Shift Register
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