74HC194D-T [NXP]

IC HC/UH SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, MINI, PLASTIC, SO-16, Shift Register;


型号：	74HC194D-T
厂家：	NXP
描述：	IC HC/UH SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, MINI, PLASTIC, SO-16, Shift Register
文件：	总10页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT194

4-bit bidirectional universal shift

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

and shifted from left to right (Q₀→ Q₁→ Q₂, etc.) or, right

to left (Q₃→ Q₂→ Q₁, etc.) or parallel data can be

entered, loading all 4 bits of the register simultaneously.

When both S₀and S₁are LOW, existing data is retained in

a hold (“do nothing”) mode. The first and last stages

provide D-type serial data inputs (D_SR, D_SL) to allow

multistage shift right or shift left data transfers without

interfering with parallel load operation.

FEATURES

• Shift-left and shift-right capability

• Synchronous parallel and serial data transfer

• Easily expanded for both serial and parallel operation

• Asynchronous master reset

• Hold (“do nothing”) mode

• Output capability: standard

Mode select and data inputs are edge-triggered,

responding only to the LOW-to-HIGH transition of the

clock (CP). Therefore, the only timing restriction is that the

mode control and selected data inputs must be stable one

set-up time prior to the positive transition of the clock

pulse.

• I_CCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT194 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The four parallel data inputs (D₀to D₃) are D-type inputs.

Data appearing on the D₀to D₃inputs, when S₀and S₁are

HIGH, is transferred to the Q₀to Q₃outputs respectively,

following the next LOW-to-HIGH transition of the clock.

When LOW, the asynchronous master reset (MR)

overrides all other input conditions and forces the Q

outputs LOW.

The functional characteristics of the 74HC/HCT194 4-bit

bidirectional universal shift registers are indicated in the

logic diagram and function table. The registers are fully

synchronous.

The “194” design has special features which increase the

range of application. The synchronous operation of the

device is determined by the mode select inputs (S₀, S₁).

As shown in the mode select table, data can be entered

The “194” is similar in operation to the “195” universal shift

connections and hold (“do nothing”) modes of operation.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

_PHL/ t_PLH

PARAMETER

CONDITIONS

UNIT

HCT

propagation delay

C_L= 15 pF; V_CC= 5 V

CP to Q_n

t_PHL

f_max

C_I

MR to Q_n

3.5

maximum clock frequency

input capacitance

102

3.5

MHz

C_PD

power dissipation capacitance per package

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ = (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC; for HCT the condition is V_I= GND to V_CC− 1.5 V

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

asynchronous master reset input (active LOW)

serial data input (shift right)

parallel data inputs

D_SR

3, 4, 5, 6

D₀to D₃

D_SL

serial data input (shift left)

ground (0 V)

GND

S₀, S₁

9, 10

mode control inputs

clock input (LOW-to-HIGH edge-triggered)

parallel outputs

15, 14, 13, 12

Q₀to Q₃

V_CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODES

S₁

S₀

D_SR

D_SL

D_n

Q₀

Q₁

Q₂

Q₃

reset (clear)

hold (“do nothing”)

q₀

q₁

q₂

q₃

↑

q₁

q₂

q₃

shift left

↑

q₀

q₁

q₂

shift right

parallel load

↑

d_n

d₀

d₁

d₂

d₃

Notes

1. H = HIGH voltage level

= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition

= LOW voltage level

= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition

q,d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the

LOW-to-HIGH CP transition

= don’t care

↑

= LOW-to-HIGH CP transition

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

Fig.5 Logic diagram.

Fig.6 Typical clear, clear-load, shift-right, shift-left, inhibit and clear timing sequences.

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85

−40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CP to Q_n

145

180

220

MHz

2.0

4.5

6.0

Fig.7

Fig.8

Fig.7

Fig.8

Fig.9

Fig.10

t_PHL

propagation delay

MR to Q_n

140

175

210

2.0

4.5

6.0

_THL/ t_TLHoutput transition time

110

2.0

4.5

6.0

t_W

t_rem

t_su

t_h

clock pulse width

HIGH or LOW

100

120

2.0

4.5

6.0

master reset pulse

width; LOW

100

120

2.0

4.5

6.0

removal time

MR to CP

2.0

4.5

6.0

set-up time

D_nto CP

105

2.0

4.5

6.0

set-up time

S₀, S₁to CP

100

120

2.0

4.5

6.0

set-up time

D_SR, D_SLto CP

105

2.0

4.5

6.0

hold time

D_nto CP

−14

−5

−4

2.0

4.5

6.0

Fig.9

t_h

hold time

−11

−4

−3

2.0

4.5

6.0

Fig.10

S₀, S₁to CP

t_h

hold time

−17

−6

−5

2.0

4.5

6.0

D_SR, D_SLto CP

f_max

maximum clock pulse 6.0

111

4.8

4.0

2.0

4.5

6.0

Fig.7

frequency

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

D_SR, D_SL

S_n

0.15

0.50

0.45

0.90

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85

−40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

CP to Q_n

4.5

Fig.7

Fig.8

Fig.7

Fig.8

Fig.9

Fig.10

Fig.9

Fig.10

Fig.9

Fig.7

t_PHL

propagation delay

MR to Q_n

_THL/ t_TLHoutput transition time

t_W

t_rem

t_su

t_h

clock pulse width

HIGH or LOW

master reset pulse

width; LOW

removal time

MR to CP

set-up time

D_nto CP

set-up time

S₀, S₁to CP

set-up time

_SR, D_SLto CP

hold time

D_nto CP

−7

−5

−7

t_h

hold time

S₀, S₁to CP

t_h

hold time

D_SR, D_SLto CP

f_max

maximum clock pulse 30

frequency

MHz 4.5

December 1990

Philips Semiconductors

Product speciﬁcation

4-bit bidirectional universal shift register

74HC/HCT194

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the master reset (MR)

pulse width, the master reset to output (Q_n)

propagation delays and the master reset to

clock (CP) removal time.

Fig.7 Waveforms showing the clock (CP) to

output (Q_n) propagation delays, the clock

pulse width, the output transition times and

the maximum clock frequency.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.10 Waveforms showing the set-up and hold

times from the mode control inputs (S_n) to

the clock input (CP).

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

Fig.9 Waveforms showing the set-up and hold

times from the data inputs (D_n, D_SRand

D_SL) to the clock (CP).

December 1990

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