74HC253PW-T [NXP]
IC HC/UH SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, Multiplexer/Demultiplexer;
| 型号： | 74HC253PW-T |
| 厂家： | 
NXP |
| 描述： | IC HC/UH SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, Multiplexer/Demultiplexer 复用器 |
| 文件： | 总7页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT253
Dual 4-input multiplexer; 3-state
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual 4-input multiplexer; 3-state
74HC/HCT253
The 74HC/HCT253 have two identical 4-input multiplexers
with 3-state outputs which select two bits from four sources
selected by common data select inputs (S0, S1).
When the individual output enable (1OE, 2OE) inputs of
the 4-input multiplexers are HIGH, the outputs are forced
to the high impedance OFF-state. The “253” is the logic
implementation of a 2-pole, 4-position switch, where the
position of the switch is determined by the logic levels
applied to S0 and S1.
FEATURES
• Non-inverting data path
• 3-state outputs for bus interface
• and multiplex expansion
• Common select inputs
• Separate output enable inputs
• Output capability: bus driver
• ICC category: MSI
The logic equations for the outputs are:
1Y = 1OE(1l0.S1.S0+1I1.S1.S0+1I2.S1.S0+1I3.S1.S0)
2Y = 2OE(2l0.S1.S0+2I1.S1.S0+2I2.S1.S0+2I3.S1.S0)
GENERAL DESCRIPTION
The 74HC/HCT253 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
APPLICATIONS
• Data selectors
• Data multiplexers
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
1In, 2In to nY;
Sn to nY
CL = 15 pF; VCC = 5 V
17
18
17
ns
19
3.5
55
ns
pF
pF
CI
input capacitance
3.5
55
CPD
power dissipation capacitance per multiplexer
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual 4-input multiplexer; 3-state
74HC/HCT253
PIN DESCRIPTION
PIN NO.
1, 15
14, 2
7, 9
SYMBOL
1OE, 2OE
S0, S1
NAME AND FUNCTION
output enable inputs (active LOW)
common data select inputs
3-state multiplexer outputs
ground (0 V)
1Y, 2Y
8
GND
6, 5, 4, 3
1I0 to 1I3
data inputs from source 1
data inputs from source 2
positive supply voltage
10, 11, 12, 13 2I0 to 2I3
16
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-input multiplexer; 3-state
74HC/HCT253
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
SELECT INPUTS
DATA INPUTS
OUTPUT ENABLE OUTPUT
S0
S1
nI0
nI1
nI2
nI3
nOE
nY
X
X
X
X
X
X
H
Z
L
L
H
H
L
L
L
L
L
H
X
X
X
X
L
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
H
H
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
L
L
L
L
L
H
L
H
H
NOTES
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
December 1990
4
Philips Semiconductors
Product specification
Dual 4-input multiplexer; 3-state
74HC/HCT253
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
+25
−40 to +85
−40
to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
1In to nY;
55
20
16
175
35
30
220
44
37
265 ns
53
45
2.0
4.5
6.0
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
2In to nY
t
t
t
t
PHL/ tPLH propagation delay
Sn to nY
58
21
17
175
35
30
220
44
37
265 ns
53
45
2.0
4.5
6.0
PZH/ tPZL 3-state output enable time
nOE to nY
30
11
9
100
20
17
125
25
21
150 ns
30
26
2.0
4.5
6.0
PHZ/ tPLZ 3-state output disable time
nOE to nY
41
15
12
150
30
26
190
38
33
225 ns
45
38
2.0
4.5
6.0
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Dual 4-input multiplexer; 3-state
74HC/HCT253
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
1In
2In
nOE
S0
0.40
0.40
1.10
1.10
1.10
S1
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
1In to nY;
20
38
48
57
ns
4.5 Fig.6
2In to nY
t
t
t
PHL/ tPLH propagation delay
Sn to nY
22
14
13
5
40
30
30
12
50
38
38
15
60
45
45
18
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Fig.6
PZH/ tPZL 3-state output enable time
nOE to nY
PHZ/ tPLZ 3-state output disable time
nOE to nY
tTHL/ tTLH output transition time
December 1990
6
Philips Semiconductors
Product specification
Dual 4-input multiplexer; 3-state
74HC/HCT253
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (1In, 2In) to output (1Y, 2Y) propagation delays and the output transition
times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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