74HC3G07DC-Q100,125 [NXP]
Buffer, HC/UH Series, 3-Func, 1-Input, CMOS, PDSO8;
| 型号： | 74HC3G07DC-Q100,125 |
| 厂家： | 
NXP |
| 描述： | Buffer, HC/UH Series, 3-Func, 1-Input, CMOS, PDSO8 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC3G07-Q100;
74HCT3G07-Q100
Triple buffer with open-drain outputs
Rev. 2 — 11 December 2013
Product data sheet
1. General description
The 74HC3G07-Q100; 74HCT3G07-Q100 is a triple buffer with open-drain outputs. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC3G07-Q100: CMOS level
For 74HCT3G07-Q100: TTL level
Complies with JEDEC standard no. 7 A
Wide supply voltage range from 2.0 V to 6.0 V
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC3G07DP-Q100 40 C to +125 C
74HCT3G07DP-Q100
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74HC3G07DC-Q100 40 C to +125 C
74HCT3G07DC-Q100
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
4. Marking
Table 2.
Marking code
Type number
Marking code[1]
74HC3G07DP-Q100
74HCT3G07DP-Q100
74HC3G07DC-Q100
74HCT3G07DC-Q100
H07
T07
H07
T07
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
2A
3A
1Y
2Y
3Y
1A
2A
3A
1Y
2Y
1
Y
3Y
1
A
GND mna591
001aah763
001aah762
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one buffer)
6. Pinning information
6.1 Pinning
74HC3G07-Q100
74HCT3G07-Q100
1
2
3
4
8
7
6
5
1A
3Y
V
CC
1Y
3A
2Y
2A
GND
aaa-009065
Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
2 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
6.2 Pin description
Table 3.
Symbol
1A, 2A, 3A
GND
Pin description
Pin
1, 3, 6
4
Description
data input
ground (0 V)
data output
supply voltage
1Y, 2Y, 3Y
VCC
7, 5, 2
8
7. Functional description
Table 4.
Function table[1]
Input nA
Output nY
L
L
Z
H
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
-
Max
7.0
20
-
Unit
V
supply voltage
[1]
[1]
[1]
[1]
[1]
[1]
[1]
input clamping current
output clamping current
output voltage
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V
mA
mA
V
IOK
20
0.5
0.5
25
-
VO
active mode
VCC + 0.5
high-impedance mode
VO = 0.5 V to 7.0 V
7.0
-
V
IO
output current
mA
mA
mA
C
ICC
IGND
Tstg
PD
supply current
50
-
ground current
50
65
-
storage temperature
dynamic power dissipation
+150
300
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
3 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC3G07-Q100
74HCT3G07-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
VI
supply voltage
input voltage
2.0
5.0
6.0
6.0
4.5
5.0
5.5
5.5
V
V
V
0
-
0
-
VO
output voltage
ambient temperature
0
-
+25
-
VCC
+125
625
139
83
0
-
+25
-
VCC
Tamb
t/V
40
40
+125 C
input transition rise
and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
-
139
-
ns/V
1.67
-
1.67
-
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
74HC3G07-Q100
VIH
HIGH-level input
voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
V
V
V
V
V
V
3.15
3.15
4.2
-
4.2
-
VIL
LOW-level input
voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 20 A; VCC = 2.0 V
-
-
-
-
-
-
0
0
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
V
0
0.1
V
0.15
0.16
-
0.33
0.33
0.1
V
V
II
input leakage
current
A
ILO
ICC
CI
output leakage
current
VI = VIH; VO = VCC or GND
-
-
-
-
-
5.0
10
-
-
-
-
10
20
-
A
A
pF
supply current
per input pin; VCC = 6.0 V;
VI = VCC or GND; IO = 0 A;
input capacitance
1.5
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
4 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
74HCT3G07-Q100
VIH
VIL
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
V
V
LOW-level input
voltage
0.8
0.8
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 20 A; VCC = 4.5 V
-
-
-
0
0.15
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA; VCC = 4.5 V
0.33
1.0
V
II
input leakage
current
VI = VCC or GND; VCC = 5.5 V
1.0
A
ILO
ICC
ICC
CI
output leakage
current
VI = VIH; VO = VCC or GND
-
-
-
-
-
-
5.0
10
-
-
-
-
10
20
410
-
A
A
A
pF
supply current
per input pin; VCC = 5.5 V;
VI = VCC or GND; IO = 0 A;
additional supply
current
per input; VCC = 4.5 V to 5.5 V;
VI = VCC 2.1 V; IO = 0 A
-
375
-
input capacitance
1.5
[1] Typical values are measured at Tamb = 25 C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 C; for test circuit, see Figure 6.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ
Max
Min
Max
74HC3G07-Q100
tPZL
tPLZ
tTHL
CPD
OFF-state to LOW
propagation delay
nA to nY; see Figure 5
VCC = 2.0 V
-
-
-
25
9
95
19
16
-
-
-
125
25
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
7
20
LOW to OFF-state
propagation delay
nA to nY; see Figure 5
VCC = 2.0 V
-
-
-
25
11
10
95
23
23
-
-
-
125
30
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
HIGH to LOW output nY; see Figure 5
transition time
VCC = 2.0 V
-
-
-
-
18
6
95
19
16
-
-
-
-
-
125
25
20
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
5
[1]
power dissipation
capacitance
VI = GND to VCC
4
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
5 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 C; for test circuit, see Figure 6.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ
Max
Min
Max
74HCT3G07-Q100
tPZL
OFF-state to LOW
propagation delay
nA to nY; see Figure 5
VCC = 4.5 V
-
11
27
-
32
ns
tPLZ
LOW to OFF-state
propagation delay
nA to nY; see Figure 5
VCC = 4.5 V
-
-
10
6
26
19
-
-
31
22
ns
ns
tTHL
CPD
HIGH to LOW output VCC = 4.5 V; see Figure 5
transition time
[1]
power dissipation
capacitance
VI = GND to VCC 1.5 V
-
4
-
-
pF
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveforms
V
I
V
M
nA input
GND
t
t
PZL
PLZ
V
CC
nY output
V
M
V
X
V
OL
t
THL
001aak034
Measurement points are given in Table 9.
VOL is the typical output voltage level that occurs with the output load.
Fig 5. The input (nA) to output (nY) propagation delays
Table 9.
Type
Measurement points
Input
Output
VM
VM
VX
74HC3G07-Q100
74HCT3G07-Q100
0.5 VCC
1.3 V
0.5 VCC
1.3 V
0.1 VCC
0.1 VCC
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
6 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 6. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
CL
S1 position
tPZL, tPLZ
VCC
tr, tf
RL
74HC3G07-Q100 GND to VCC
74HCT3G07-Q100 GND to 3 V
6 ns
6 ns
50 pF
50 pF
1 k
1 k
VCC
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
7 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 7. Package outline SOT505-2 (TSSOP8)
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
8 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 8. Package outline SOT765-1 (VSSOP8)
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
9 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
MIL
Military
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
74HC_HCT3G07_Q100 v.2 20131211
Product data sheet
-
74HC_HCT3G07_Q100 v.1
Modifications:
• Features and benefits updated (errata).
74HC_HCT3G07_Q100 v.1 20130917
Product data sheet
-
-
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
10 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
16.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
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applications and therefore such inclusion and/or use is at the customer's own
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Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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customer’s third party customer(s). Customers should provide appropriate
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data sheet shall define the specification of the product as agreed between
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customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
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damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
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completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
11 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT3G07_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 December 2013
12 of 13
NXP Semiconductors
74HC3G07-Q100; 74HCT3G07-Q100
Triple buffer with open-drain outputs
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 December 2013
Document identifier: 74HC_HCT3G07_Q100
相关型号：
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