74HC3G07 [NXP]
Buffer with open-drain outputs; 缓冲带漏极开路输出
| 型号： | 74HC3G07 |
| 厂家： | 
NXP |
| 描述： | Buffer with open-drain outputs |
| 文件： | 总14页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HC3G07; 74HCT3G07
Buffer with open-drain outputs
Product specification
2003 Oct 15
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
FEATURES
DESCRIPTION
• Wide supply voltage range from 2.0 to 6.0 V
• High noise immunity
The 74HC3G/HCT3G07 is a high-speed Si-gate CMOS
device. Specified in compliance with JEDEC standard
no. 7A.
• Low power dissipation
The 74HC3G/HCT3G07 provides three non-inverting
buffers.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The outputs of the 74HC3G/HCT3G07 devices are open
drains and can be connected to other open-drain outputs
to implement active-LOW, wired-OR or active-HIGH
wired-AND functions. For digital operation this device must
have a pull-up resistor to establish a logic HIGH-level.
• Multiple package options
• Specified from −40 to +85 °C and −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC3G
HCT3G
11
tPZL
tPLZ
CI
propagation delay nA to nY
propagation delay nA to nY
input capacitance
CL = 50 pF; VCC = 4.5 V
CL = 50 pF; VCC = 4.5 V
9
11
1.5
4
10
1.5
4
ns
pF
pF
CPD
power dissipation capacitance
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑ (CL × VCC2 × fo) = sum of outputs.
2. For 74HC3G07 the condition is VI = GND to VCC
.
For 74HCT3G07 the condition is VI = GND to VCC − 1.5 V.
2003 Oct 15
2
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
FUNCTION TABLE
See note 1.
INPUT
nA
OUTPUT
nY
L
L
Z
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGES
PACKAGE MATERIAL
TYPE NUMBER
TEMPERATURE RANGE PINS
CODE
MARKING
74HC3G07DP
74HCT3G07DP
74HC3G07DC
74HCT3G07DC
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
8
8
8
8
TSSOP8
TSSOP8
VSSOP8
VSSOP8
plastic
plastic
plastic
plastic
SOT505-2
SOT505-2
SOT765-1
SOT765-1
H07
T07
H07
T07
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
6
7
8
1A
data input
3Y
data output
data input
2A
GND
2Y
ground (0 V)
data output
data input
3A
1Y
data output
supply voltage
VCC
2003 Oct 15
3
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
handbook, halfpage
1A
2A
3A
1Y
2Y
7
5
2
1
3
6
handbook, halfpage
1A
3Y
1
2
3
4
8
7
6
5
V
CC
1Y
3A
2Y
07
2A
GND
3Y
MNB135
MNB136
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
1
1
1
3
6
7
5
2
1Y
2Y
3Y
1A
2A
3A
Y
handbook, halfpage
A
MNA591
GND
MNB137
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one driver).
2003 Oct 15
4
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
RECOMMENDED OPERATING CONDITIONS
74HC3G07
74HCT3G07
UNIT
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.0
TYP. MAX. MIN.
TYP. MAX.
VCC
VI
5.0
−
6.0
4.5
0
5.0
5.5
5.5
VCC
V
V
V
input voltage
0
6.0
−
VO
output voltage
0
−
VCC
0
−
Tamb
operating ambient
temperature
see DC and AC
characteristics per
device
−40
+25
+125 −40
+25
+125 °C
tr, tf
input rise and fall times
VCC = 2.0 V
VCC = 4.5 V
−
−
−
−
1000
500
−
−
−
−
−
ns
ns
ns
6.0
−
6.0
−
500
−
VCC = 6.0 V
400
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
UNIT
VCC
IIK
−0.5
−
+7.0
±20
−20
V
input diode current
output diode current
output voltage
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V
mA
mA
V
IOK
VO
−
active mode; note 1
high-impedance mode; note 1
−0.5 V < VO < 7.0 V
note 1
−0.5
−0.5
−
VCC + 0.5
7.0
V
IO
output sink current
VCC or GND current
storage temperature
power dissipation
−25
mA
mA
°C
ICC
Tstg
PD
−
50
−65
−
+150
300
Tamb = −40 to +125 °C; note 2
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 110 °C the value of PD derates linearly with 8 mW/K.
2003 Oct 15
5
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
DC CHARACTERISTICS
Type 74HC3G07
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
1.2
−
−
−
V
V
V
V
V
V
3.15
4.2
−
2.4
3.2
0.8
2.1
2.8
VIL
LOW-level input voltage
LOW-level output voltage
0.5
−
1.35
1.8
−
VOL
VI = VIH or VIL
IO = 20 µA
IO = 20 µA
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
0
0.1
V
V
V
V
V
0
0.1
IO = 20 µA
0
0.1
IO = 4.0 mA
IO = 5.2 mA
VI = VCC or GND
0.15
0.16
−
0.33
0.33
±1.0
±5.0
ILI
input leakage current
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
−
ICC
quiescent supply current
VI = VCC or GND; IO = 0 6.0
−
−
10
µA
Tamb = −40 to +125 °C
VIH HIGH-level input voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
3.15
4.2
−
−
−
−
−
−
−
−
V
V
V
V
V
V
−
−
VIL
LOW-level input voltage
LOW-level output voltage
0.5
1.35
1.8
−
−
VOL
VI = VIH or VIL
IO = 20 µA
2.0
4.5
6.0
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.1
0.1
0.4
0.4
±1.0
±10
V
IO = 20 µA
V
IO = 20 µA
V
IO = 4.0 mA
IO = 5.2 mA
VI = VCC or GND
V
V
ILI
input leakage current
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 6.0
−
−
20
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Oct 15
6
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
Type 74HCT3G07
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1) MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
1.6
1.2
−
V
LOW-level input voltage
LOW-level output voltage
−
0.8
V
VOL
VI = VIH or VIL
IO = 20 µA
IO = 4.0 mA
4.5
4.5
5.5
5.5
−
−
−
−
0
0.1
V
0.15
−
0.33
±1.0
±5.0
V
ILI
input leakage current
VI = VCC or GND
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
−
ICC
quiescent supply current
VI = VCC or GND; IO = 0 5.5
−
−
−
−
10
µA
µA
∆ICC
additional supply current
per input
VI = VCC − 2.1 V; IO = 0
4.5 to 5.5
375
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
V
LOW-level input voltage
LOW-level output voltage
−
0.8
VOL
VI = VIH or VIL
IO = 20 µA
4.5
4.5
5.5
5.5
−
−
−
−
−
−
−
−
0.1
V
IO = 4.0 mA
0.4
V
ILI
input leakage current
VI = VCC or GND
±1.0
±10
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 5.5
−
−
−
−
20
µA
µA
∆ICC
additional supply current
per input
VI = VCC − 2.1 V; IO = 0
4.5 to 5.5
410
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Oct 15
7
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
AC CHARACTERISTICS
Type 74HC3G07
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
WAVEFORMS VCC (V)
Tamb = −40 to +85 °C
tPZL
propagation delay see Figs 5 and 6 2.0
−
−
−
−
−
−
−
−
−
25
9
95
19
16
95
23
23
95
19
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
nA to nY
4.5
6.0
7
tPLZ
propagation delay see Figs 5 and 6 2.0
25
11
10
18
6
nA to nY
4.5
6.0
tTHL
output transition
time
see Figs 5 and 6 2.0
4.5
6.0
5
Tamb = −40 to +125 °C
tPZL
tPLZ
tTHL
propagation delay see Figs 5 and 6 2.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
125
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
nA to nY
4.5
6.0
20
propagation delay see Figs 5 and 6 2.0
125
30
nA to nY
4.5
6.0
26
output transition
time
see Figs 5 and 6 2.0
125
25
4.5
6.0
20
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Oct 15
8
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
Type 74HCT3G07
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
Tamb = −40 to +85 °C
tPZL
propagation delay see Figs 5 and 6
nA to nY
4.5
4.5
4.5
−
−
−
11
10
6
27
26
19
ns
ns
ns
tPLZ
tTHL
propagation delay see Figs 5 and 6
nA to nY
output transition
time
see Figs 5 and 6
Tamb = −40 to +125 °C
tPZL
tPLZ
tTHL
propagation delay see Figs 5 and 6
nA to nY
4.5
4.5
4.5
−
−
−
−
−
−
32
31
22
ns
ns
ns
propagation delay see Figs 5 and 6
nA to nY
output transition
time
see Figs 5 and 6
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Oct 15
9
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
AC WAVEFORMS
V
I
V
nA input
M
GND
t
t
PZL
PLZ
V
CC
nY output
V
M
V
V
X
OL
MNA528
For 74HC3G07: VM = 50%; VI = GND to VCC
.
For 74HCT3G07: VM = 1.3 V; VI = GND to 3.0 V.
For 74HC3G07 and 74HCT3G07: VX = 0.1 × VCC
.
Fig.5 The input (nA) to output (nY) propagation delays and transition times.
S1
V
CC
open
V
CC
GND
R
=
L
1 kΩ
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
=
L
R
T
MNA742
TEST
S1
Definitions for test circuit:
RL = Load resistor.
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
open
VCC
CL = load capacitance including jig and probe capacitance.
GND
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2003 Oct 15
10
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.25
0.65
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2003 Oct 15
11
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.12
0.5
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
2003 Oct 15
12
Philips Semiconductors
Product specification
Buffer with open-drain outputs
74HC3G07; 74HCT3G07
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Oct 15
13
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R44/01/pp14
Date of release: 2003 Oct 15
Document order number: 9397 750 12067
相关型号：
74HC3G07DC-Q100
HC/UH SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8
NXP
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