概述
规格参数
数据手册74HC40105D 概述
4-bit x 16-word FIFO register 4位x 16字FIFO寄存器 FIFO
74HC40105D 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Transferred | 零件包装代码： | SOIC |
| 包装说明： | 3.90 MM, PLASITC, MS-012AC, SOT-109-1, SO-16 | 针数： | 16 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.24 |
| 最长访问时间： | 600 ns | 其他特性： | REGISTER BASED; BUBBLE BACK 750NS |
| 最大时钟频率 (fCLK)： | 14 MHz | 周期时间： | 71.428 ns |
| JESD-30 代码： | R-PDSO-G16 | 长度： | 9.9 mm |
| 内存密度： | 64 bit | 内存集成电路类型： | OTHER FIFO |
| 内存宽度： | 4 | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 端子数量： | 16 |
| 字数： | 16 words | 字数代码： | 16 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 125 °C |
| 最低工作温度： | -40 °C | 组织： | 16X4 |
| 输出特性： | 3-STATE | 可输出： | YES |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP16,.25 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 并行/串行： | PARALLEL |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 2/6 V |
| 认证状态： | Not Qualified | 座面最大高度： | 1.75 mm |
| 子类别： | FIFOs | 最大供电电压 (Vsup)： | 6 V |
| 最小供电电压 (Vsup)： | 2 V | 标称供电电压 (Vsup)： | 4.5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | AUTOMOTIVE | 端子面层： | NICKEL/PALLADIUM/GOLD (NI/PD/AU) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 3.9 mm | Base Number Matches： | 1 |
74HC40105D 数据手册
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DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT40105
4-bit x 16-word FIFO register
1998 Jan 23
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
different shifting rates. This feature makes it particularly
useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop,
which stores a marker bit. A “1” signifies that the position’s
data is filled and a “0” denotes a vacancy in that position.
The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the
FEATURES
• Independent asynchronous inputs and outputs
• Expandable in either direction
• Reset capability
• Status indicators on inputs and outputs
• 3-state outputs
succeeding flip-flop. When a control flip-flop is in the “0”
state and sees a “1” in the preceding flip-flop, it generates
a clock pulse that transfers data from the preceding four
data latches into its own four data latches and resets the
preceding flip-flop to “0”. The first and last control flip-flops
have buffered outputs. Since all empty locations “bubble”
automatically to the input end, and all valid data ripples
through to the output end, the status of the first control
flip-flop (data-in ready output - DIR) indicates if the FIFO is
full, and the status of the last flip-flop (data-out ready
output - DOR) indicates if the FIFO contains data. As the
earliest data is removed from the bottom of the data stack
(output end), all data entered later will automatically ripple
toward the output.
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40105 are high-speed Si-gate CMOS
devices and are pin compatible with the “40105” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40105 are first-in/first-out (FIFO) “elastic”
storage registers that can store sixteen 4-bit words. The
“40105” is capable of handling input and output data at
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYP.
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
t
PHL/ tPLH
CL = 15 pF; VCC = 5 V
MR to DIR, DOR
SO to Qn
16
37
15
ns
35
ns
tPHL
propagation delay
SI to DIR
16
17
33
18
ns
SO to DOR
18
ns
fmax
CI
maximum clock frequency
input capacitance
31
MHz
pF
3.5
3.5
145
CPD
power dissipation capacitance per package notes 1 and 2
134
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz.
fo = output frequency in MHz.
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5
1998 Jan 23
2
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
74HC(T)40105N
74HC(T)40105D
74HC(T)40105DB
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-1
SOT109-1
SOT338-1
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm
74HC(T)40105PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
output enable input (active LOW)
data-in ready output
2
DIR
3
SI
shift-in input (LOW-to-HIGH, edge-triggered)
parallel data inputs
4, 5, 6, 7
D0 to D3
GND
MR
8
ground (0 V)
9
asynchronous master reset input (active HIGH)
3-state data outputs
13, 12, 11, 10
Q0 to Q3
DOR
SO
14
15
16
data-out ready output
shift-out input (HIGH-to-LOW, edge-triggered)
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jan 23
3
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
LOW in order to complete the shift-in
process.
INPUT AND OUTPUTS
Data inputs (D0 to D3)
Shift-in control (SI)
Data is loaded into the input stage on
a LOW-to-HIGH transition of SI.
It also triggers an automatic data
transfer process (ripple through). If SI
is held HIGH during reset, data will be
loaded at the falling edge of the MR
signal.
With the FIFO full, SI can be held
HIGH until a shift-out (SO) pulse
occurs. Then, following a shift-out of
data, an empty location appears at
the FIFO input and DIR goes HIGH to
allow the next data to be shifted-in.
This remains at the first FIFO location
until SI goes LOW (see Fig.7).
As there is no weighting of the inputs,
any input can be assigned as the
MSB. The size of the FIFO memory
can be reduced from the 4 × 16
configuration, i.e. 3 × 16, down to
1 × 16, by tying unused data input
pins to VCC or GND.
Shift-out control (SO)
A HIGH-to-LOW transition of
SO causes the DOR flags to go LOW.
A HIGH-to-LOW transition of
SO causes upstream data to move
into the output stage, and empty
locations to move towards the input
stage (bubble-up).
Data outputs (Q0 to Q3)
Data transfer
As there is no weighting of the
outputs, any output can be assigned
as the MSB. The size of the FIFO
memory can be reduced from the
4 × 16 configuration as described for
data inputs. In a reduced format, the
unused data outputs pins must be left
open circuit.
After data has been transferred from
the input stage of the FIFO following
SI = LOW, data moves through the
FIFO asynchronously and is stacked
at the output end of the register.
Empty locations appear at the input
end of the FIFO as data moves
through the device.
Output enable (OE)
The outputs Q0 to Q3 are enabled
when OE = LOW. When OE = HIGH
the outputs are in the high impedance
OFF-state.
Master-reset (MR)
Data output
When MR is HIGH, the control
The data-out-ready flag
functions within the FIFO are cleared,
and date content is declared invalid.
The data-in ready (DIR) flag is set
HIGH and the data-out-ready (DOR)
flag is set LOW. The output stage
remains in the state of the last word
that was shifted out, or in the random
state existing at power-up.
(DOR = HIGH) indicates that there is
valid data at the output (Q0 to Q3).
The initial master-reset at power-on
(MR = HIGH) sets DOR to LOW (see
Fig.8). After MR = LOW, data shifted
into the FIFO moves through to the
output stage causing DOR to go
HIGH.
FUNCTIONAL DESCRIPTION
Data input
Following power-up, the master-reset
(MR) input is pulsed HIGH to clear the
FIFO memory (see Fig.8). The
data-in-ready flag (DIR = HIGH)
indicates that the FIFO input stage is
empty and ready to receive data.
When DIR is valid (HIGH), data
present at D0 to D3 can be shifted-in
using the SI control input.
As the DOR flag goes HIGH, data can
be shifted-out using the SO = HIGH,
data in the output stage is shifted out
and a busy indication is given by DOR
going LOW. When SO is made LOW,
data moves through the FIFO to fill
the output stage and an empty
location appears at the input stage.
When the output stage is filled DOR
goes HIGH, but if the last of the valid
data has been shifted-out leaving the
FIFO empty the DOR flag remains
LOW (see Fig.9). With the FIFO
empty, the last word that was
Status flag outputs (DIR, DOR)
Indication of the status of the FIFO is
given by two status flags,
data-in-ready (DIR) and
data-out-ready (DOR):
With SI = HIGH, data is shifted into
the input stage and a busy indication
is given by DIR going LOW.
DIR = HIGH indicates the input stage
is empty and ready to accept valid
data;
The data remains at the first location
in the FIFO until DIR is set to HIGH
and data moves through the FIFO to
the output stage, or to the last empty
location. If the FIFO is not full after the
SI pulse, DIR again becomes valid
(HIGH) to indicate that space is
available in the FIFO. The DIR flag
remains LOW if the FIFO is full (see
Fig.6). The SI use must be made
DIR = LOW indicates that the FIFO is
full or that a previous shift-in
operation is not complete (busy);
DOR = HIGH assures valid data is
present at the outputs Q0 to Q3 (does
not indicate that new data is awaiting
transfer into the output stage);
shifted-out is latched at the output
Q0 to Q3.
With the FIFO empty, the SO input
can be held HIGH until the SI control
input is used. Following an SI pulse,
DOR = LOW indicates the output
stage is busy or there is no valid data.
1998 Jan 23
4
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
data moves through the FIFO to the
output stage, resulting in the DOR
flag pulsing HIGH and a shift-out of
data occurring. The SO control must
be made LOW before additional data
can be shifted-out (see Fig.10).
pulses can be applied without regard
Due to the part-to-part spread of the
ripple through time, the SI signals of
FIFOA and FIFOB will not always
coincide and the AND-gate will not
produce a composite flag signal. The
solution is given in Fig.18.
to the status flags but shift-in pulses
that would overflow the storage
capacity of the FIFO are not allowed
(see Figs 11 and 12).
Expanded format
The “40105” is easily cascaded to
increase the word capacity and no
external components are needed. In
the cascaded configuration, all
necessary communications and
timing are performed by the FIFOs.
The intercommunication speed is
determined by the minimum flag
pulse widths and the flag delays. The
data rate of cascaded devices is
typically 25 MHz. Word-capacity can
be expanded to and beyond 32-words
× 4-bits (see Fig.19).
High-speed burst mode
With the addition of a logic gate, the
FIFO is easily expanded to increase
word length (see Fig.17). The basic
operation and timing are identical to a
single FIFO, with the exception of an
additional gate delay on the flag
outputs. If during application, the
following occurs:
If it is assumed that the
shift-in/shift-out pulses are not
applied until the respective status
flags are valid, it follows that the
shift-in/shift-out rates are determined
by the status flags. However, without
the status flags a high-speed burst
mode can be implemented. In this
mode, the burst-in/ burst-out rates are
determined by the pulse widths of the
shift-in/shift-out inputs and burst rates
of 35 MHz can be obtained. Shift
• SI is held HIGH when the FIFO is
empty, some additional logic is
required to produce a composite
DIR pulse (see Figs 7 and 18).
1998 Jan 23
5
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Fig.4 Functional diagram.
(see control flip-flops)
(1) LOW on S input of FF1, and FF5 will set Q output to HIGH independent of state on R input.
(2) LOW on R input of FF2, FF3 and FF4 will set Q output to LOW independent of state on S input.
Fig.5 Logic diagram.
1998 Jan 23
6
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tf = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
ns
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
MR to DIR, DOR
52
19
15
52
19
15
55
20
16
175
35
220
44
265
53
2.0 Fig.8
4.5
30
37
45
6.0
tPHL
propagation delay
SI to DIR
210
42
265
53
315
63
ns
2.0 Fig.6
4.5
36
45
54
6.0
tPHL
propagation delay
SO to DOR
210
42
265
53
315
63
ns
2.0 Fig.9
4.5
36
45
54
6.0
t
PHL/ tPLH propagation delay
116 400
500
100
85
600
120
102
ns
2.0 Fig.14
4.5
SO to Qn
42
34
80
68
6.0
tPLH
propagation delay/
ripple through delay
SI to DOR
564 2000
205 400
165 340
701 2500
255 500
204 425
2500
500
425
3125
625
532
190
38
3000 ns
600
2.0 Fig.10
4.5
510
6.0
tPLH
propagation delay/
bubble-up delay
SO to DIR
3750 ns
750
2.0 Fig.7
4.5
638
6.0
t
t
t
PZH/ tPZL 3-state output enable time
41
15
12
41
15
12
19
7
150
30
225
45
ns
ns
ns
ns
2.0 Fig.16
4.5
OE to Qn
26
33
38
6.0
PHZ/ tPLZ 3-state output disable
140
28
175
35
210
42
2.0 Fig.16
4.5
time
OE to Qn
24
30
36
6.0
THL/ tTLH output transition time
75
95
110
22
2.0 Fig.14
4.5
15
19
6
13
16
19
6.0
tW
SI pulse width
HIGH or LOW
80
16
14
19
7
100
20
120
24
2.0 Fig.6
4.5
6
17
20
6.0
1998 Jan 23
7
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
ns
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tW
SO pulse width
HIGH or LOW
120 39
150
30
26
10
5
180
36
2.0 Fig.9
4.5
24
20
12
6
14
11
58
21
17
55
20
16
22
8
31
6.0
tW
DIR pulse width
HIGH
180
36
225 10
270
54
ns
2.0 Fig.7
4.5
45
38
5
4
5
31
4
46
6.0
tW
DOR pulse width
LOW
12
6
170
34
10
5
215 10
255
51
ns
2.0 Fig.9
4.5
43
37
5
5
29
4
4
43
6.0
tW
MR pulse width
HIGH
80
16
14
50
10
9
100
20
17
65
13
11
−5
−5
−5
155
31
26
2.8
14
16
120
24
20
75
15
13
−5
−5
−5
190
38
32
2.4
12
14
ns
2.0 Fig.8
4.5
6
6.0
trem
tsu
th
removal time
MR to SI
14
5
ns
2.0 Fig.15
4.5
4
6.0
set-up time
Dn to SI
−5
−5
−5
−39
−14
−11
ns
2.0 Fig.13
4.5
6.0
hold time
Dn to SI
125 44
ns
2.0 Fig.13
4.5
25
21
3.6
18
21
16
13
10
30
36
6.0
fmax
maximum pulse
frequency
MHz 2.0 Fig.6, 9, 11
and 12
4.5
SI, SO using flags or
burst mode
6.0
fmax
maximum pulse
frequency
SI, SO cascaded
3.6
18
21
10
30
36
2.8
14
16
2.4
12
14
MHz 2.0 Figs 6 and 9
4.5
6.0
1998 Jan 23
8
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
OE
SI
0.75
0.40
0.30
1.50
0.40
Dn
MR
SO
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tf = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
+25
−40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
MR to DIR, DOR
18
21
20
40
35
42
42
80
44
53
ns
ns
ns
ns
ns
4.5 Fig.8
4.5 Fig.6
4.5 Fig.9
4.5 Fig.14
4.5 Fig.10
tPHL
propagation delay
SI to DIR
53
63
tPHL
propagation delay
SO to DOR
53
63
tPHL/ tPLH propagation delay
SO to Qn
100
500
120
600
tPLH
propagation delay/
ripple through delay
SI to DOR
188 400
244 500
tPLH
propagation delay/
bubble-up delay
SO to DIR
625
750
ns
4.5 Fig.7
t
PZH/ tPZL 3-state output enable time
OE to Qn
18
15
35
30
44
38
53
45
ns
ns
4.5 Fig.16
4.5 Fig.16
tPHZ/ tPLZ 3-state output disable
time
OE to Qn
tTHL/ tTLH output transition time
7
15
19
22
ns
4.5 Fig.14
1998 Jan 23
9
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tW
SI pulse width
HIGH or LOW
16
16
6
6
20
20
5
24
24
5
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.9
4.5 Fig.7
4.5 Fig.9
4.5 Fig.8
4.5 Fig.15
4.5 Fig.13
4.5 Fig.13
tW
SO pulse width
HIGH or LOW
7
tW
DIR pulse width
HIGH or LOW
20
19
7
34
34
43
43
51
51
tW
DOR pulse width
HIGH or LOW
6
5
5
tW
MR pulse width
HIGH
16
15
−5
27
20
19
−4
34
12
24
22
−4
41
10
trem
tsu
th
removal time
MR to SI
7
set-up time
Dn to SI
−14
16
28
hold time
Dn to SI
fmax
maximum pulse frequency
SI, SO using flags or
burst mode
MHz 4.5 Fig.6, 9, 11 and
12
fmax
maximum pulse frequency
SI, SO cascaded
28
12
10
MHz 4.5 Figs 6 and 9
1998 Jan 23
10
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
Notes to Fig.6
1. DIR initially HIGH; FIFO is
prepared for valid data.
2. SI set HIGH; data loaded into
input stage.
3. DIR drops LOW, input stage
“busy”.
4. DIR goes HIGH, status flag
indicates FIFO prepared for
additional data; data from first
location “ripple through”.
5. SI set LOW; necessary to
complete shift-in process.
6. Repeat process to load 2nd word
through to 16th word into FIFO.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
7. DIR remains LOW: with attempt
to shift into full FIFO, no data
transfer occurs.
Fig.6 Waveforms showing the SI input to DIR output propagation
delay. The SI pulse width and SI maximum pulse frequency.
With FIFO full; SI held HIGH in anticipation of empty location
Notes to Fig.7
1. FIFO is initially, shift-in is held
HIGH.
2. SO pulse; data in the output
stage is unloaded, “bubble-up
process of empty locations
begins”.
3. DIR HIGH; when empty location
reached input stage, flag
indicates FIFO is prepared for
data input.
4. DIR returns to LOW; FIFO is full
again.
5. SI brought LOW; necessary to
complete whidt-in process, DIR
remains LOW, because FIFO is
full.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output
and DIR output pulse width.
1998 Jan 23
11
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Master reset applied with FIFO full
Notes to Fig.8
1. DIR LOW, output ready HIGH;
assume FIFO is full.
2. MR pulse HIGH; clears FIFO.
3. DIR goes HIGH; flag indicates
input prepared for valid data.
4. DOR drops LOW; flag indicates
FIFO empty.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
Shifting out sequence; FIFO full to FIFO empty
Notes to Fig.9
1. DOR HIGH; no data transfer in
progress, valid data is present at
output stage.
2. SO set HIGH.
3. SO is set LOW; data in the input
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
4. DOR drops LOW; output stage
“busy”.
5. DOR goes HIGH; transfer
process completed, valid data
present at output after the
specified propagation delay.
6. Repeat process to unloaded the
3rd through to the 16th word from
FIFO.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
7. DOR remains LOW; FIFO is
empty.
Fig.9 Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
1998 Jan 23
12
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
With FIFO empty; SO is held HIGH in anticipation
Notes to Fig.10
1. FIFO is initially empty, SO is held
HIGH.
(1)
SI INPUT
2
V
M
2. SI pulse; loads data into FIFO
and initiates ripple through
process.
(1)
SO INPUT
1
V
M
5
3. DOR flag signals the arrival of
valid data at the output stage.
t
t
PHL
6
PLH
4. Output transition; data arrives at
output stage after the specified
propagation delay between the
rising edge of the DOR pulse to
the Qn output.
ripple through
delay
(1)
t
DOR OUTPUT
V
M
4
/ t
PHL PLH
Q
OUTPUT
3
n
5. SO set LOW; necessary to
complete shift-out process. DOR
remains LOW, because FIFO is
empty.
MBA337
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
6. DOR goes LOW; FIFO is empty
again.
Fig.10 Waveforms showing ripple through delay SI input to DOR output
and propagation delay from the DOR pulse to the Qn output.
Shift-in operation; high-speed burst mode
Note to Fig.11
In the high-speed mode, the burst-in
rate is determined by the minimum
shift-in HIGH and shift-in LOW
specifications. The DIR status flag is
a don’t care condition, and a shift-in
pulse can be applied regardless of the
flag. A SI pulse which would overflow
the storage capacity of the FIFO is
ignored.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing SI minimum pulse width and SI maximum
pulse frequency, in high-speed shift-in burst mode.
1998 Jan 23
13
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Shift-out operation; high-speed burst mode
In the high-speed mode, the burst-out rate is determined by the
minimum shift-out HIGH and shift-out LOW specifications. The
DOR flag is a don’t care condition and a SO pulse can be applied
without regard to the flag.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing hold and set up times for Dn input to SI input.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing SO input to Qn output propagation delays and output transition time.
1998 Jan 23
14
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
handbook, halfpage
MR INPUT
(1)
V
M
t
rem
(1)
V
SI INPUT
M
MBA332
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveforms showing the MR input to SI input removal time.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the 3-state enable and disable times for input OE.
1998 Jan 23
15
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
APPLICATION INFORMATION
The PC74HC/HCT40105 is easily expanded to
increase word length. Composite DIR and DOR
flags are formed with the addition of an AND
gate. The basic operation and timing are
identical to a single FIFO, with the exception of
an added gate delay on the flags.
Fig.17 Expanded FIFO for increased word length; 16 words × 8 bits.
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started (see Fig.7).
Fig.18 Expanded FIFO for increased word length.
1998 Jan 23
16
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words × 4 bits
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, date arrives at the output of FIFOA. Due to SOA being HIGH, a DOR pulse is
generated. The requirements of SIB and DnB are satisfied by the DORA pulse width and the timing between the rising
edge of DORA and QnA. After a second ripple through delay, data arrives at the output of FIFOB.
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SOR pulse, when both FIFOs are initially
full. After a bubble-up delay a DIRR pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred
from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse
width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH.
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFOA and FIFOB. Fig.22 gives an
overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
Fig.19 Cascading for increased word capacity; 32 words × 4 bits.
1998 Jan 23
17
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Notes to Fig.20
1. FIFOA and FIFOB initially empty, SOA held
HIGH in anticipation of data.
2. Load one word into FIFOA; SI pulse applied,
results in DIR pulse.
3. Data out A/data in B transition; valid data
arrives at FIFOA output stage after a specified
delay of the DOR flag, meeting data input
set-up requirements of FIFOB.
4. DORA and SIB pulse HIGH; (ripple through
delay after SIA LOW) data is unloaded from
FIFOA as a result of the data output ready
pulse, data is shifted into FIFOB.
5. DIRB and SOA go LOW; flag indicates input
stage of FIFOB is busy, shift-out of FIFOA is
complete.
6. DIRB and SOA go HIGH automatically; the
input stage of FIFOB is again able to receive
data, SO is held HIGH in anticipation of
additional data.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
7. DORB goes HIGH; (ripple through delay after
SIB LOW) valid data is present one
propagation delay later at the FIFOB output
stage.
Fig.20 FIFO to FIFO communication; input timing under
empty condition.
Notes to Fig.21
1. FIFOA and FIFOB initially empty, SIB held
HIGH in anticipation of shifting in new data as
empty location bubbles-up.
2. Unload one word into FIFOB; SO pulse
applied, results in DOR pulse.
3. DIRB and SOA pulse HIGH; (bubble-up delay
after SOB LOW) data is loaded into FIFOB as
a result of the DIR pulse, data is shifted out of
FIFOA.
4. DORA and SIB go LOW; flag indicates the
output stage of FIFOA is busy, shift-in to
FIFOR is complete.
5. DORA and SIB go HIGH; flag indicates valid
data is again available at FIFOA output stage,
SIB is held HIGH, awaiting bubble-up of
empty location.
6. DIRA goes HIGH; (bubble-up delay after
SOA LOW) an empty location is present at
input stage of FIFOA.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.21 FIFO to FIFO communication; output timing under
full condition.
1998 Jan 23
18
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Fig.22 Waveforms
showing the
functionally and
inter-
communication
between two
FIFOs
(refer to Fig.19).
Note to Fig.22
Sequence 4 (Both FIFOs full, starting shift-out process):
SIA is held HIGH and two SOB pulses are applied (8).
These pulses shift out two words and thus allow empty
locations to bubble-up to the input stage of FIFOB, and
proceed to FIFOA (9). When the first empty location arrives
at the input of FIFOA, a DIRA pulse is generated (10) and
a new word is shifted into FIFOA. SIA is made LOW and
now the second empty location reaches the input stage of
FIFOA, after which DIRA remains HIGH (11).
Sequence 1 (Both FIFOs empty, starting shift-in process):
After a MR pulse has been applied FIFOA and FIFOB are
empty. The DOR flags of FIFOA and FIFOB go LOW due
to no valid data being present at the outputs. The DIR flags
are set HIGH due to the FIFOs being ready to accept data.
SOB is held HIGH and two SIA pulses are applied (1).
These pulses allow two data words to ripple through to the
output stage of FIFOA and to the input stage of FIFOB (2).
When data arrives at the output of FIFOB, a DORB pulse is
generated (3). When SOB goes LOW, the first bit is shifted
out and a second bit ripples through to the output after
which DORB goes HIGH (4).
Sequence 5 (FIFOA runs empty):
At the start of sequence 5 FIFOA contains 15 valid words
due to two words being shifted out and one word being
shifted in sequence 4. An additional series of SOB pulses
are applied. After 15 SOB pulses, all words from FIFOA are
shifted into FIFOB. DORA remains LOW (12).
Sequence 2 (FIFOB runs full):
After the MR pulse, a series of 16 SI pulses are applied.
When 16 words are shifted in, DIRB remains LOW due to
FIFOB being full (5). DORA goes LOW due to FIFOA being
empty.
Sequence 6 (FIFOB runs empty):
After the next SOB pulse, DIRB remains HIGH due to the
input stage of FIFOB being empty (13). After another 15
SOB pulses, DORB remains LOW due to both FIFOs being
empty (14). Additional SOB pulses have no effect. The last
word remains available at the output Qn.
Sequence 3 (FIFOA runs full):
When 17 words are shifted in, DORA remains HIGH due to
valid data remaining at the output of FIFOA. QnA remains
HIGH, being the polarity of the 17th data word (6). After the
32th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
1998 Jan 23
19
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1998 Jan 23
20
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1998 Jan 23
21
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-01-14
95-02-04
SOT338-1
MO-150AC
1998 Jan 23
22
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-07-12
95-04-04
SOT403-1
MO-153
1998 Jan 23
23
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
WAVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
DIP
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
SO, SSOP and TSSOP
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
REPAIRING SOLDERED JOINTS
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
1998 Jan 23
24
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jan 23
25
74HC40105D 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 74HC40105D,652 | NXP | 74HC(T)40105 - 4-bit x 16-word FIFO register SOP 16-Pin | 获取价格 |
|
| 74HC40105D,653 | NXP | 74HC(T)40105 - 4-bit x 16-word FIFO register SOP 16-Pin | 获取价格 |
|
| 74HC40105D-T | ETC | x4 Asynchronous FIFO | 获取价格 |
|
| 74HC40105DB | NXP | 4-bit x 16-word FIFO register | 获取价格 |
|
| 74HC40105DB,118 | NXP | 74HC(T)40105 - 4-bit x 16-word FIFO register SSOP1 16-Pin | 获取价格 |
|
| 74HC40105DB-T | NXP | IC 16 X 4 OTHER FIFO, 600 ns, PDSO16, 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16, FIFO | 获取价格 |
|
| 74HC40105N | NXP | 4-bit x 16-word FIFO register | 获取价格 |
|
| 74HC40105N,652 | NXP | 74HC(T)40105 - 4-bit x 16-word FIFO register DIP 16-Pin | 获取价格 |
|
| 74HC40105PW | NXP | 4-bit x 16-word FIFO register | 获取价格 |
|
| 74HC40105PW,112 | NXP | 暂无描述 | 获取价格 |
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